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WHITE PAPER:

HIGH SPEED RULES - PART 1 SIGNAL INTEGRITY IS HERE

Are you aware of signal integrity problems you may face in you next high-speed embedded design? In this paper, we review the high speed design related signal integrity issues, and briefly introduce facts behind these effects. The document brings the basics of high-speed technology like transmission line effects, crosstalk, ground bounce into a reality. Having solid knowledge of the high-speed design requirements helps you to survive in the digital domain.
Jyrki Keinnen jyrki.keinanen@chilidevices.com

o survive in the wild world of shrinking electronics that operates on ever increasing speeds, an engineer needs to be aware of the new set of design challenges. Effects like impedance mismatch, transmission line effects, crosstalk and ground bounce may prevent your product from operating as expected. Similarly, these effects may create hard-to-find and hardto-solve problems that may keep your product off the market for unforeseeable time. This white paper discusses of the signal integrity issues that electronics designer will face sooner or later. Background of signal integrity related effects is briefly explained in the document. Signal integrity issues have been explained in details, and guidelines for avoiding typical design errors have been given in the other white papers.

sues in low speed digital devices. Now, the things are changing here, and not for the better. Understanding and controlling signal integrity (signal quality) related issues becomes essential for you in order to get your design done as expected. There are multiple driving forces for the importance of the signal integrity
Miniaturization High packing densities Decreasing trace widths Decreasing trace spacing Incompatible technologies close to each others Low power supply voltages High power supply currents Low logic levels Low noise margins High frequency digital signals Fast data rates Fast switching devices with high switch currents Devices with high I/O pin counts Transmission line effects

Signal integrity is the new sheriff in town

Digital designs have traditionally been quite immune to the problems that are familiar to analog domain systems. Noise or careful printed circuit board routing have not been big is-

Miniaturization of devices forces electronic designers to place components close to each other. There is simply no extra space available on printed circuit boards. High packing densities require decreasing both trace widths and trace spacing as well. Printed circuit board traces that run close to each

other are prone to crosstalk, inductive or capacitive. As system integration level gets higher, it brings different technologies (like power supply, digital circuitry, analog subsystems, RF modules) close to each others. The operating frequencies, impedance levels as well as voltage and current levels vary to great extent, and they may interfere with the other systems located close to them. Power supply voltage levels decrease due to changes in semiconductor processes. Today, voltages like 5V, 3.3V, 2.8V, 2.5V, 1.8V, 1.5V and even lower are common in embedded systems. Low voltage devices use low logic levels, and as a result the system noise margins tend to decrease. In high performance systems where the power consumption is high, low supply voltage leads to extremely high supply currents. High performance devices

need to utilize high clock signal frequencies and fast data streams. Increasing data rates require using fast switching devices, and therefore high switching currents. Fast devices can not tolerate long PCB traces without proper terminations due to transmission line effects that may ruin the signal quality. At low speeds, the frequency response of the trace has little influence on the signal, unless the trace is particularly long. As speed increases, number of high-speed effects take over. Printed circuit board trace inductance with high I/O pin counts may introduce new challenges like ground bounce effects. Most of these issues have a significant effect on the embedded designs.

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AC circuit model comes into play

Load Ideal Conductor Model

Load

AC Model of a Conductor

Load

Simplified AC Model

Circuit models of a conductor

High speed issues

Common problems and effects that the designer faces during the high speed embedded device design and test are typically
Transmission line effects Impedance mismatch Crosstalk Ground bounce Signal attenuation

The signal source and load have typically been connected together by means of conductive medium. Typically, these connections include wires, cables and printed circuit board traces (tracks). At low frequencies a printed circuit board trace may be considered to be ideal from the signal transmission point of view. The resistance, inductance and capacitance of the physical trace can be ignored, so they do not effect the signal at all. When the signal frequency increases, the AC circuit characteristic (AC model) starts to dominate. The physical constraints (resistance, inductance and capacitance) come into play, and they become prevalent in the printed circuit

board trace. Series inductance of the conductor is typically designers main concern when it comes to ensuring signal quality in digital systems. The series inductance both limits the signal slew rate and generates voltage glitches due to abrupt current changes. Similarly, parasitic capacitances (at load input, from a trace to ground, from a trace to another trace) play a role here. As a result, at high frequencies the printed circuit board trace impedance is no more constant, but depends on the frequency.

straints. At high frequencies, the inductance and capacitance of the printed circuit board trace tend to attenuate signal. When the signal speeds increase, the dielectric losses of the printed circuit board laminate will increase. Traditional FR-4 material will cope with signals up some 2-3 GHz, but may not be the best solution for higher frequency applications. Printed circuit board laminate influence to signal will be discussed in detail later in this paper.

Time vs. frequency domain

Signal attenuation

As the AC model of conductor denotes the impedance of a trace is not constant, but depends on the frequency as well as the other physical con-

Today, most of the embedded system designs operate mainly on digital domain. Analog signals are typically converted to digital world as early as possible. These digital signals will then be processed by the

These effects may seriously hamper the integrity (quality, response) of the signal. You can only overcome these issues by firstly understanding the background of these symptoms, secondly carefully studying your design to pinpoint the most likely problematic areas, and thirdly by following good design techniques and layout guidelines, as described in the other white papers of this series. Neglecting these effects, and just closing your eyes during the design phase will leave you standing in the dark by yourself. That may be a long and windy road in your way to get the product on markets. Locating the origin of the problems that may exist in the prototype board, not even to mention fixing them may put you between the rock an a hard place. As with the low speed designs, soldering a wire to the printed circuit board may not fix anything, but merely creates even more problems. With high-speed designs, knowledge and engineering talent are the key factors in order to prevent these problems to come to the forefront.

Clock signals (rise times 2 ns and 100 ps)

Frequency spectrums of the clock signals

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microprocessors, logic devices like FPGAs and software. The bandwidth of a digital signal depends on the signal shape, rise and fall times, modulation methods etc. However, signal bandwidth spreads over wide spectrum that exceeds the base band frequency due to sharp edges of the digital signal. The figures (see the previous page) show two clock signals and their frequency spectrums. The frequencies of the signals are equal (100MHz), but the rise times (edge rates) are different (2 ns vs. 100 ps). As the edge rates of the signals get faster, the frequency spectrum spread increases. The faster the signal edges are, the more likely they will give you transmission line related headaches.

Transmission line effects

As signal speed increases, the transmission line effects need to be considered in the design. Transmission line effects come into play when the lengths of a printed circuit board trace (or any other cable or conductor carrying the signal) are so long that the signal delay back and forward down the trace becomes longer than signals rise or fall time. Mismatches between the traces characteristic impedance and drivers output impedance or loads input impedance create signal reflections. These reflections in turn cause overshoot and undershoot and distort the signal waveform.

The reflections reduce noise margins of the system and may cause unwanted glitches in signals as well. Note, that the transmission line effects depend on the signal edge rate, not the signal frequency. It is clear that applications handling fast signals need to need to have fast devices to survive. So, transmission line effects will most likely to be checked out while designing such systems. However, you may decide to use a single fast device (that generates fast edge signals) in the low speed system. In this case, the transmission line effects may caught you unprepared. Transmission line effects should be taken into consideration in all systems that contain fast (edge rate) signals, no matter what the clock signal frequency is. The following figure shows clock signals (green) that have identical frequency, but different rise times. Note, that slow edge rates result in good quality signals at the load (green), but fast edge rates generate excessive ringing and overshooting at the load.

nate is, the higher propagation delay will be. As a thumb rule, the propagation delay tPD of a typical FR-4 based printed circuit board trace is about 1.7 ns/ft (5.5 ns/m). The length of a printed circuit board trace at which the transmission line effects (ringing) and overshooting) should be considered depends on the propagation delay and signal edge rate. The maximum length of an unterminated transmission line is:
lmax = lmax tr tPD tr 2 tPD maximum trace length signal rise or fall time propagation delay

Termination Need for termination depends on the following constraints 1. Propagation delay of the signal (from source to load) 2. Signal rise and fall times 3. Source impedance 4. Load impedance 5. Characteristic impedance of the transmission line 6. Circuit characteristics and behavior (response speed etc.) 7. Logic threshold voltage (noise margins)

Termination

As stated earlier, the transmission line effect severity depends on the edge rate and the propagation delay of the signal. The printed circuit board material (dielectric material) effects to the propagation delay of a signal. The higher relative dielectric constant of the lami-

For example, if the signal rise/fall time (tr) is 2 ns, and the propagation delay of the signal is 1.7ns/ft, the maximum length of a routed trace without terminations is 0.6 ft (180 mm). If there are multiple loads connected to the trace (aka lumped load), the capacitance of these loads increase the propagation delay even further. So, as a result heavily loaded trace requires termination even with shorter traces than lightly loaded trace.

Characteristic impedance

Every conductor has so called characteristic impedance (also known as natural impedance), that depends on the physical constraints of the conductor. Characteristic impedance ZO refers to the equivalent

impedance of a conductor (or a transmission line) if it were infinitely long. A uniform conductor terminated in its characteristic impedance will have no standing waves (reflections) from the other end. So, it has a constant ration of voltage to current at a given frequency at every point of the conductor. The characteristic impedance of each type of conductor depends on the construction of that conductor: the dimensions, how close to the signal return path that conductor is, dielectric properties etc. Printed circuit boards typically contain microstrip and stripline type PCB traces. As with all conductor types, the characteristic impedance of these traces depend on the trace dimensions and PCB construction. Typically the impedance of a microstrip trace is in a range of 50...150 Ohm, and in a range of 30...80 Ohm for a stripline trace due to closer proximity of a ground plane.

Impedance matching

Connecting a signal source (generator) to a load is needed for transferring the electromagnetic signal. If the source and load impedances differ from another (impedance mismatch), that would inevitably result in reflections and signal losses. By adjusting (impedance matching) the impedances of various part of the system a designer can minimize these reflections and ensure the proper signal quality. For example, a video distribution system requires using either 50 or 75 Ohm connections in order to connect various systems together. With video, the reflections due to
Clock edge rate makes the difference

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impedance mismatch may cause ringing and ghosting in the final picture. In digital systems, impedance mismatches may result distorted clock signal, spurious interrupts, or even wrong data read from a peripheral device. These may cause severe malfunction of the system. In digital systems, various termination methods are used for impedance matching.

Crosstalk

Crosstalk will become an issue for printed circuit board designers as the packaging densities keep on increasing. Embedded devices contain even more mixed signal systems packed into a small area of a printed circuit board or an enclosure. Some systems contain sensitive analog systems like amplifiers and A/D converters, as the other may contain power electronics (DC motor controls, solenoid drivers or similar). Typical mechanism of crosstalk in embedded system are
Power supply coupling Capacitive crosstalk Inductive crosstalk

Ground noise due to series inductance

Crosstalk issues will be discussed in the following chapters.

edge rates routed close to the high impedance circuitry (for example a CMOS or analog circuitry) are just some examples of systems susceptible to capacitive crosstalk. Signals running on closely adjacent printed circuit board traces can disturb signals running on other traces, if the length of parallel traces is long enough.

Inductive crosstalk

from the high frequency point of view the ground is no more homogenous equal reference potential. Voltage differences generated by high frequency signals cause easily other problems in addition to signal integrity issues. Too often symptoms of inadequate design can be notified during the EMI measurements as high emissions or poor immunity level.

but finite inductance present in the wiring. High switching currents generate voltage differences in these inductances. This phenomenon known as ground bounce may affect the total board. Ground bounce is contributed by multiple factors, and there is no standard methods available for predicting ground bounce related problems.

Power supply crosstalk

Various parts of the design share some of the power supplies, so, the digital parts of the design may interference the analog part or vice versa. Fast transitions of high voltages tend to connect to other parts of the circuitry through mutual capacitance of the circuits. In some systems, the return currents may share same path, which results in crosstalk due to mutual impedance: changes in current flowing through the impedance is seen by the other subsystem.

In high speed digital systems, the inductances of the wires play important role. The digital return currents return to ground through a non-zero impedance. The impedance exists mainly due to resistive and inductive effects of the printed circuit board wiring. Inductance of the signal path generates voltage differences between various points of the printed circuit board ground -

Ground bounce

Simultaneous switching

As digital devices become faster, their switching times decrease. To switch fast, devices outputs need to drive (charge or discharge) load capacitances with high currents. As traces, pins and semiconductor packages (bonded wires from package pins to the actual chip) are not ideal conductors, there is always small

Current from power supply

Voltage Drop

Capacitive crosstalk

High density designs have components and traces close to each others. As every part or wire is actually connected to surrounding circuitry with parasitic capacitance, they are prone to crosstalk through the capacitance. High speed signals with fast

Logic Gate VCC Usig Current from generator

Uout Load Ground Bounce u2 Ground Bounce u3

Ground Bounce u1

Logic Gate Input V oltage: Voltage Over Load:

Uin = Usig - u1 - u2 Uload = Uout + u2 - u3

Inductances play a big role in digital design

Today, embedded designs contain large scale integrated devices and programmable logic devices that may have very high I/O pin counts. Just consider for example a Altera Stratix FPGA device with 1020-pin FBGA package. When multiple output drivers switch simultaneously, they induce a voltage drop in both the device power distribution. At the same time, the switching current momentarily raises the ground voltage of the device relative to the system ground. The higher the device ground connection inductance is, the higher ground voltage bounce is. Controlling the ground bounce heavily relies on the PCB design, as there is not so much left to be done in the architecture level of design. High transient currents due to simultaneous switching of the digital devices may generate excessive amount of ground noise, just like the

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Signal Integrity Basics The main threats of your next design are 1. Transmission line effects and improper terminations 2. Power supply considerations 3. Capacitive crosstalk 4. Inductive crosstalk 5. Ground bounce 6. Simultaneous switching with high I/O count 7. Poor component placement (locations) on printed circuit board (PCB) 8. Poor clock signal routing 9. Poor signal routing 10. Poor power arrangement 11. Improper PCB build-up (use of layers, construction) 12. Wrong PCB material selection

ground bounce effect. High levels of ground noise make the system prone to increased emissions (EMI). In addition to this, the system may suffer from poor reliability and time-to-time operational failures.

Signal routing

Careful signal routing on high speed digital printed circuit board becomes essential in order to avoid functional problems, or even to make embedded devices to operate in the first place. Transmission line effects set the maximum lengths for a PCB trace without a termination. Signal reflections in long traces simply can ruin the signal integrity and prevent the design from operating as expected. A group of fast signals often need to arrive the load within a time slot in order to process the parallel information correctly. Length variation in the signals traces leads to timing variations that can be difficult to correct. The propagation delay of a trace depends on the trace construction and loading,

so signals connected to short traces arrive well before signals connected to long traces. Timing of the clock signal compared to other signals often makes the difference here. There are other considerations other than just the trace lengths. Trace impedance depends on the physical constraints of the trace (width, thickness) as well as the buildup of the printed circuit board (dimensions, dielectric material etc.). Trace impedance is related to impedance matching and termination requirements. Clock signal distribution should be carefully designed to minimize delays and jitter, and to ensure the clock signal can be used safely in different parts of the printed circuit board. There may be other control signals in addition to the actual clock signals that require special care while routing. Small trace spacing (separation) allow high routing density on the board, but running multiple traces in parallel may lead to excessive capacitive crosstalk between signals. Likewise, using narrow traces to increase available routing channels on PCB increases trace inductance and may make signal integrity issues worse.

1-Side PCB Parallel Traces

2-Side PCB or Multilayer PCB Microstrip Ground Plane Ground Plane Multilayer PCB Stripline Ground Plane Basic Printed Circuit Board Constructions

Layer 01 - Routing Layer 02 - Routing Layer 03 - Routing Layer 04 - Mixed Layer 05 - Power Layer 06 - Ground Layer 07 - Mixed Layer 08 - Routing Layer 09 - Routing Layer 10 - Routing Example of High Density Interconnect (HDI) PCB Build-Up

Ensuring good signal integrity may be the your next design challenge
ference between two nodes, not the absolute voltage level. Therefore, digital signals can travel reliably over greater lengths of trace while maintaining a clear and consistent data stream. to keep the device ground and power connections short. Further, the ground plane offers low inductance return paths for the high speed signals. High density designs call for extremely dense board constructions. It may not be the routing density that rules, but also using small pitch ball grid packages (BGA, Ball Grid Array) often require microvias (laser drilled or plasma etched vias) and fine line technology for begin able to route all the pins of a single package.

Differential signal routing

Differential signals (like LVDS, Low Voltage Differential Signaling) may help designer in order to maintain signal integrity on large PCBs. Unlike with normal digital signals, differential signals do not depend on the voltage difference between the source/ load and common ground. Instead, digital signal value is distinguished by voltage dif-

Board build-up

Desired printed circuit board construction (build-up) depends on the component packages used in the design, required signal trace density, impedance matching requirements, assembly facilities etc. Traditional two layer boards use routed power and ground connections. This board type should not be used with high speed circuitry, as providing solid reference level (ground) for these signals is impossible. For the high speed boards, using a multilayer PCB with buried ground and power supply planes is mandatory. Solid copper planes allow designer

PCB laminate selection

Today, FR-4 PCB laminate material is widely used in electronic industry. The FR-4 material is economical solution for most of the digital designs as long as frequencies on board can be kept below some 2.5-3 GHz range. At high speeds the digital signal may be affected by the

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parameters of the printed circuit board laminate that it travels on. Dedicated high speed laminates (like Rogers RO4350) have better properties at higher frequencies than FR4 does. Using right materials would help designer to reach his design target easier and more reliably than with FR-4 material. Firstly, a signal travelling through the printed circuit board has a velocity that is dependent on the dielectric constant of the printed circuit board. For example, when the signal frequency goes beyond 5GHz, the typical dielectric constant of FR-4 (round 4.7) drops close to 4. However, the relative dielectric constant of the Rogers RO4350 material is constant (roughly 3.5) from 0 up to 15 GHz. If the dielectric constant of the printed circuit board changes versus frequency, then different frequency components of the signal will have different velocities. This means, that these components will reach the load at different times. As a result, this will be causing distortion of the digital signal. Secondly, the signal losses due to printed circuit board material increase with frequency. Again, each harmonic

Crosstalk from one PCB trace to another may cause unwanted glitches

of the digital signal will be attenuated according to that frequency of operation. Increased loss of the signal components will add to the distortion of the digital signal.

Ignoring signal integrity issues is just asking for trouble

guesswork as it becomes too time consuming and expensive from now on. Following good design guidelines and using proper tools help an embedded system designer in his work, and partly guarantee high quality results. To put it together: It is time for you to take signal quality precautions into consideration. About the author: Jyrki Keinnen works as a principal staff engineer at the CHILIdevices International. He has experience of more than 15 years with embedded systems and devices. He is responsible of the technology development of the modular system-in-package product line at CHILIdevices Intl.

Summary

Signal integrity issues gain importance day by day due to increasing speeds and packing densities. There is really no substitute for both deep understanding of the high speed related issues and taking them seriously. It is indeed time to stop the

Fast Switching Devices

Edge rate makes the difference
As time goes by, the more likely you will end up using fast switching devices in your design - simply just because they are only ones available for your design at the moment. As the propagation delay of the printed circuit board depends on the dielectric material properties, the delay will be constant on the board under construction. Short rise times at the output of the driver allow only short trace lengths without terminations. The faster the signal edge gets at given trace length, the worse the reflections and signal distortion. Similarly, the longer the traces get at given rise time, the worse the reflections and signal distortion.
Load Slow Signal Edges Source

Load Medium Signal Edges Source

Load Fast Signal Edges Source

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