Digital IC Implementation Strategies Outline

Outline
Implementation Strategies for Digital ICs

Introduction From Custom to Semicustom and Structured Array Design Approaches Custom Circuit Design Cell-Based Design Methodologies Standard cell Macrocells, Megacells, and IP Semi-custom design flow Array-Based Implementation Approaches
Prediffused (Mask Programmable) Arrays Prewird Arrays
Introduction
Logic Transistors per Chip (K)
10,000,000 .10 1,000,000 100,000 .35 10,000 1000 100 2.5 10 1 1987 1989 1981 1983 1985 Xx XX X X X 21% Yr. compound Productivity growth rate 1991 1993 1995 1997 1999 2001 2003 2005 2007
A Generic Digital Processor
Logic Transistors / Chip Transistors/Staff Month

58% Yr.compound Complexity growth rate
100,000,000 10,000,000 1000,000 100,000 10,000 1000 100 10 2009
(Trans./Staff-Month) Productivity (Trans./Staff
Memory Input-Output
Control
Datapath
From Custom to Semicustom and Structured-Array Design Approaches

Choosing an effective methodology function to be implemented, Design priorities performance, power, area, .. High performance and low cost Large sales volume Supercomputing and defense applications Cost: Nonrecurring expense Production cost per part
Implementation Methodologies
Digital Circuit Implementation Approaches
Custom
Semi-custom
Cell-Based
Array-Based
Standard Cells Compiled Cells
Macro Cells
Pre-wired (FPGA)
Pre-diffused (Gate Arrays)
Custom Design
When performance or design density is a primary requirement Cost paid: High design cost + long time to market Instances that custom design seems to be a reasonable approach: Many times reusable (library cell) Large volume production (microprocessors, memories) Cost is not a primary criterion (supercomputers)
Intel Pentium-4 Processor
Virtually all portions: A semi-custom design Except: PLL and clock buffer
Cell library design; is the only area that custom design is intensively used
Digital Circuit Implementation Approaches
Cell-Based Design Methodology

Automated design process Reduced integration density and performance Rule: The shorter the design time the larger the penalty incurred
Custom
Semi-custom
Cell-Based
Array-Based Advantage: Reusing library cells
Macro Cells
Pre-wired (FPGA)
Disadvantage: Reduced possibility of fine-tuning a design
Cell-Based Design Methodology
Standard Cell Approach
Standard Cells Compiled Cells Macrocells, Megacells
Cell Library:
Logic gates with various fan-in and fan-out counts, Basic logic function: AND, OR, XOR, NAND, Complex logic functions: Adder, Multipliers, Counter, Decoders, MUX, Comparators,
Standard Cell Approach

Feed through cell Logic cell
Standard Cell Design
Rows of cells
Routing channel
Functional module (RAM, multiplier, ) Three-layer metal technology.

Implementation Strategies for Digital ICs Implementation Strategies for Digital ICs
Size and Elements Variety ? Documentation

Layout, Functionality, terminal positioning, Delay, and Power consumption, (as a function of load capacitance and input rise and fall times) Seven-layer metal technology, 90% logic density
Three-Input NAND Gate

3-input NAND Gate in 0.18 micron CMOS technology Five versions of the cell supporting capacitive loads: 0.18 pF 0.72 pF, Areas 16.4 m2 32.8 m2

A very popular approach
Exceptions: Very high performance, Energy efficient designs, Very regular structures (memories) Other reasons for success of this approach: Automatic cell placement and routing tools, Advent of logic-synthesis tools
A Historical Perspective
Product terms
A Historical Perspective
f 0 = x0 x1 + x 2 f1 = x0 x1 x 2 + x 2 + x0 x1
AND plane
x0 x1 x2
OR plane
f 0 = ( x0 x1 ) + x 2
f0 x0 x1 x2
f1
f 1 = ( x0 x1 x 2 ) + x 2 + ( x0 x1 )
PLA Layout Implementation
Compiled Cells
Regenerating Cell Library because of: Migration from one technology to a new one Changes and modifications in a given technology
Hence: the quest for automated cell generation. Developed tools such as: AbraCAD, Pro Geninsis
Macrocells, Megacells
Complexity higher than what can be found in Standard Cell Library
Hard Macrocells
A module with a given functionality and a predetermined physical design Complex custom design of a requested function Examples: Multipliers and Memories Advantage: Custom Design Disadvantage: Hard to translate to other technologies, or other manufactures
Two types: Hard Macrocell Soft Macrocell

An Example of a Hard Macrocell
Soft Macrocells
A module with a given functionality, but without a physical implementation
While stepping away from custom design advantage, Its major advantage: Hard macrocell of a memory, 256 x 32 bits, in 0.18 CMOS Technology, 0.094 mm2
Can be ported over a wide range of technologies and processes
Soft Macrocell Generators
Input: Desired function, requested parameters Output: A netlist from standard cells, timing constraints
Advantage: Does its best for implementation using, all knowledge available in literature
A 8x8 Soft Macrocell Multiplier Generated by: ModuleCompiler tool from Synopsis
A Processor for Wireless Communication
A Processor for Wireless Communication
Test Interface 1 kB 1 $ 64 kB 1RAM 64 kB DRAM
Baseband Interface
CPU
Protocol MAC
Audio
On- chip Network
Flash Ctrl
flash Interface
I/O
I / O Bus
2 Mbt flash
Host Interface
Semicustom Design Flow

Design Capture HDL
Behavioral Structure
Design Iteration
Pre layout Simulation
Logic Synthesis
Post layout Simulation
Floor planning Placement
Physical
Circuit Extraction
Routing Tape out
RTL (Timing) constraints Digital Circuit Implementation Approaches
Physical synthesis
Custom Macromodules fixed netlists Netlist with place-and-route info Semi-custom
Cell-Based
Array-Based
Place-and-route Optimization
Artwork
Macro Cells
Pre-wired (FPGA)
Array-Based Implementation Approaches

Design automation reduces design time, but require a complete run through the fabrication run.
Delay in introduction of the product Extra masking and dedicated process expenses
Array-Based Implementation Approaches
Array-based implementation approaches
Array-based approaches do not require a complete run through the manufacturing process
Lower NRE Suitable for small series
Prediffused arrays
Gate Array Sea of Gates
Prewired arrays
Comes at the expense of:

Lower integration density Lower performance Higher power dissipation
Gate Array
polysilicon VD D metal GND possible contact
In 1 In 2 In 3 In4
Gate Array
rows of uncommitted cells
Out
routing channel
Primitive gate-array Cell
Programmed Cell (4-input NOR)

Channeled Architecture
Gate Array
cells
Sea-of-Gate Primitive Cells

Oxide-isolation
cells
Rows of uncommit ted cells
PMOS PMOS
NMOS
Routing channel
NMOS NMOS
Channelless (or sea of gates)
Channelled
Channeled Architecture
A FLIP-FLOP Implemented in a Gate-Array Approach
Embedded Gate Array

Random Logic
Memory Subsystem
M. Smith, Application-Specific Integrated Circuits, Addison-Wesley, 1997
LSI Logic LEA300K (0.6 m CMOS)

Via Programmable Gate Array
Prewired Arrays
Prewired Arrays or Field-Programmable Grate Arrays (FPGA):

Fuse-based (Write-once) Non-volatile EEPROM based Volatile or RAM-based
Programmable Logic Devices

Programmable OR array
Array-based Cell-based
PLA
Programmable AND array

O3 O2 O1 O0
PAL PROM
PLA
PROM
PAL
Partitioned PLA
Programmable AND array (2i X jk) Product terms k macrocells
Partitioned PLA
j wide
OR array D Q Out
j j
Advantages: Regular structure, Parasitics estimation, and prediction of area, power, speed is possible Provides an efficient implementation for 2-level logic description Disadvantages: Higher overhead; Lower performance, some parts are left with no usage
macrocells CLK A B C i
i inputs
Cell-Based Programmable Logic
Multiplexer-Based Approach
Configuration
A 0 B 0 X Y Y 0 0 1 0 0 1 S 0 1 1 X Y X X X Y 1 F= 0 X Y XY
Multiplexer-based approach Look-Up table approach
A B
0 F 1
0 0 0 X Y Y 1 1 1
XY XY
X+Y
X Y 1
A B SA C D SB S0 S1
1
A B SA C D SB 1 1 1 Y
1 Y 1
0 In1 0 1 In1 In2
Logic Cell Used in the Actel Fuse-Based FPGA Any 2 and 33-input logic function Can be realized
2-Input XOR
S0 S1
A B 1
LUT Based Programmable Logic Cell
Y 1
Memory
In1
SA C D 1
In
0 Out 1
Out 0 1 1 0
00 01 10 11
4-Input Multiplexer In1 In2
In1 In2
SB
S0 S1
Programmable Interconnects
Array-Based Programmable Wiring

Programmed interconnection Input/output pin
Array-based programmable wiring Switch-box-based programmable wiring
Cell Antifuse Horizontal tracks
Vertical tracks
Programming interconnect using anti-fuses

Switch-Box-Based Programmable Wiring
Altera MAX Series
Array-Based Routing
Xilinx XC40xx Series
Look-up table approach Mesh-based Routing

Xilinx XC4025 1000 CLB 32 x 32 25000 Gates 422 Kbits RAM 250 MHz

Digital IC Implementation Strategies Outline

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Outline

Implementation Strategies for Digital ICs

Implementation Strategies for Digital ICs

A Generic Digital Processor

Logic Transistors / Chip Transistors/Staff Month

100,000,000 10,000,000 1000,000 100,000 10,000 1000 100 10 2009

(Trans./Staff-Month) Productivity (Trans./Staff

Implementation Strategies for Digital ICs

Implementation Strategies for Digital ICs

From Custom to Semicustom and Structured-Array Design Approaches

Standard Cells Compiled Cells

Pre-diffused (Gate Arrays)

Implementation Strategies for Digital ICs

Intel Pentium-4 Processor

Implementation Strategies for Digital ICs

Implementation Strategies for Digital ICs

Cell-Based Design Methodology

Array-Based Advantage: Reusing library cells

Standard Cells Compiled Cells

Pre-diffused (Gate Arrays)

Disadvantage: Reduced possibility of fine-tuning a design

Implementation Strategies for Digital ICs

Implementation Strategies for Digital ICs

Cell-Based Design Methodology

Standard Cell Approach

Standard Cells Compiled Cells Macrocells, Megacells

Implementation Strategies for Digital ICs

Implementation Strategies for Digital ICs

Standard Cell Approach

Standard Cell Design

Functional module (RAM, multiplier, ) Three-layer metal technology.

Standard Cell Design

Standard Cell Design

Size and Elements Variety ? Documentation

Three-Input NAND Gate

Standard Cell Design

Implementation Strategies for Digital ICs

Implementation Strategies for Digital ICs

PLA Layout Implementation

Two types: Hard Macrocell Soft Macrocell

An Example of a Hard Macrocell

A module with a given functionality, but without a physical implementation

Can be ported over a wide range of technologies and processes

Implementation Strategies for Digital ICs

Soft Macrocell Generators

Implementation Strategies for Digital ICs

Implementation Strategies for Digital ICs

A Processor for Wireless Communication

A Processor for Wireless Communication

Test Interface 1 kB 1 $ 64 kB 1RAM 64 kB DRAM

On- chip Network

Semicustom Design Flow

Pre layout Simulation

Post layout Simulation

Floor planning Placement

Routing Tape out

Implementation Strategies for Digital ICs

Implementation Strategies for Digital ICs

Standard Cells Compiled Cells

Pre-diffused (Gate Arrays)

Implementation Strategies for Digital ICs

Array-Based Implementation Approaches