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An Introduction
COURSE
ILP Pipelined VLIW DSP Architectures Superscalar DLP SIMD Associative & Neural Architectures Systolic Architectures Vector Architectures
ADAVNCED VLSI AECHITECTURES K.R.ANUPAMA 2
COURSE
MIMD Multi-threaded Distributed memory MIMD Shared memory MIMD
Case Studies Simulation based Performance Evaluation Studies MIPSit, Simple Scalar
EVALUATION
EC No. 1 2 3 Evaluation Component Test I Test II Assignment & Case Studies, Class Room Interactions Comprehensive Duration Weightage (min) (%) 60 60 ----20 20 20 Nature of Component Closed Book Closed Book
180
40
Closed/Open Book
SPEED UP
Deeply pipelined machines
Many instructions/cycle
Out-of-order execution of instructions Aggressive branch prediction techniques 2010 1 billion transistors clock frequencies >10GHz
ISA
Contract between software and hardware
ISA
Development is very slow
ISAs varied No. of operands Implied operands Operands may be stored in stack
10
DSI
Program (Software) Compiler Complexity Exposed to software
Static
Architecture
Hardware Complexity Exposed to hardware Dynamic
Machine (Hardware)
11
DSI
DEL CISC VLIW RISC HLL
Hardware
12
13
CPU
TN T3 T2 T1
14
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Problem 2
Problem 3
Problem 4
PARALLEL COMPUTING
The compute resources might be: A single computer with multiple processors An arbitrary number of computers connected by a network A combination of both
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PARALLEL COMPUTING
The computational problem should be able to: Be broken apart into discrete pieces of work that can be solved simultaneously Execute multiple program instructions at any moment in time Be solved in less time with multiple compute resources than with a single compute resource.
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AMDAHLS LAW
Ttotal = Timproved 1 [ Ttotal - Tcomponent ]+ Tcomponent n
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