HOMEWORK 1 Problems 1-5 carry 5 points each Problem 6 carries 10 points Problem 7 carries 15 points [Partial credit allowed

for correct concepts]

SOLUTIONS
1. Use the laws of Boolean algebra to prove the following identity: x'yz' + xyz' + xyz = yz' + xy (where ' denotes complementation). LHS = x'yz' + xyz' + xyz = x'yz' + xyz' + xyz' + xyz = yz' (x + x') + xy(z' + z) = yz' + xy = RHS. It is okay to start from the RHS as well.

2. Consider a CMOS inverter with the following parameters: Wn=2m, Wp=4m, Ln=Lp=0.8m, K'n= n.Coxn=20A/V2, K'p= p.Coxp=10A/V2, VTn=1V, VTp= -1V, VDD=5V,VSS=GND=0V. Find the value of VM (the inverter threshold) of the above inverter. K' is the process trans-conductance. [Hint: VM is the midpoint voltage on the voltage transfer characteristic, where Vin=Vout.]
Vo

VM

Vi

Vin = Vout happens in the nearly vertical segment of the VTC where both the PMOS and the NMOS transistors are in saturation. equating the saturation drain current equations, we get: (K'n/2).( Wn/ Ln).(Vin - VTn)2 = (K'p/2).( Wp/ Lp).(VDD - Vin - VTn)2

or, or, or, or,

[(VDD - Vin - VTn)/ Vin - VTn)] = [(K'n/ K'p).( Wn / Ln).( Lp / Wp)]1/2 [(5 VM 1)/(VM 1)] = [(20/10). (2.0/0.8).(0.8/4.0)] 1/2 [(4 VM )/(VM 1)] = 1 VM = 2.5

The threshold is at 2.5 V Give full credit if students use direct formula from text book. 3. Identify the logic function implemented by the following circuit that has 2 inputs IN1 and IN2 and one output OUT. [Hint: Construct a truth table with various input combinations and try to find the output for each case.]

VDD

IN1

IN2

OUT

IN1 IN2 OUT 0 0 0 0 1 1 1 0 1 1 1 0

The above circuit implements the XOR function

4. Draw the transistor-level circuit of the following complex gate: OUT = [(a + bc + def)g]' (where ' denotes complementation).

f OUT d b e c f

5. Do a stick-diagram-based layout of the function f = (a + bc)'. Use the following color convention: Yellow = P-diff, Green = N-diff, Red = Poly, Blue = Metal 1, Black cross = contact (via). VDD

c VSS

6. Draw the transistor-level shematic of an inverter. Assign Wn=2m and Wp=4m. Assume an output load of 0.5 pF. Using a circuitsimulation tool (e.g., HSPICE) of your choice, perform a DC analysis to plot the voltage transfer characteristic of the inverter. Feel free to use a reasonable value for VDD (e.g., 5 V) and default values for the other transistor parameters as specified in the default model used by the chosen CAD tool. [Hint: A tutorial or example in the manual for the simulator you are using is likely to show an inverter simulation example. A common method is to produce an input circuit description or deck, invoke the simulator, read in the deck, and run the simulator]. Lab project. Give full credit for correct analysis output and for any transistor width and voltage and any circuit simulator as long as the input deck is specified properly. 7. Using a layout editor of your choice, do a layout of the above inverter. Make sure that the layout is design-rule correct (for the technology you are using). Perform a layout simulation by tying the terminals to appropriate power supplies and applying a one-cycle

square wave at the input of the inverter. Verify the inverted output for correct results. Submit layout plot and simulation results. Lab project. Give full credit for any form of layout with any transistor width as long as the layout is design-rule correct. Students should demonstrate some evidence of correct layout (e.g., a plot without the cross-hatched mark that is usually present in case of a DRC violation). Some evidence of correct functionality of the inverter layout (e.g., LVS or circuit extraction and DC analysis or circuit extraction and transient analysis or layout logic simulation, etc) is necessary to get full credit.