PVT Variation Tolerant Standby Power Reduction Techniques for Submicron SRAMs

Yue Lu, Thura Lin Naing Department of Electrical Engineering and Computer Science, University of California, Berkeley {yuelu,thura} @ eecs.berkeley.edu
Abstract- Suppressing the leakage current in memories in standby mode is the key to save power in modern SoC mobile application. Scaling / to its limits can reduce leakage power 2-5 times. In this paper, we are going explore the literature and propose that in addition to supply scaling, adaptive body biasing can improve PVT variation tolerance to achieve further standby leakage power reduction. 1.0 Introduction One of the negative side effects of technology scaling is that the leakage power of on-chip memory increases dramatically and becomes one of the main challenges for many systems-on-a-chip (SoC) designs in both active and standby mode. For battery-constrained devices, the reduction of the standby leakage power is important for longer battery life. Since SRAMs is the largest component in many modern SoC, its leakage power during standby mode usually dominates the overall standby power of the whole system [4]. Therefore, an efficient memory leakage suppression scheme is critical for the success of ultra low power design. Various techniques have been developed to reduce SRAM leakage power. At the circuit level, dynamics control of substrate-source back bias were exploited to reduce leakage power [6], but this approach requires some layout modifications on the SRAM cell structure, resulting in some area overhead. At the architectural level, leakage reduction techniques including scaling of of idle memory sections ([3], [4]) and using dynamic sleep transistor (DST) to tune virtual ground [5]. These approaches can achieve leakage energy savings by 2-5 times, but the question remains on how to find the lower/higher bound of standby / that still preserves data. Another negative side effect of technology scaling is the increasing transistor threshold voltage variations across memory arrays. In standby mode, conventional 6T SRAM cell will degrade its static noise margin (SNM) harshly across the memory [2]. As the result, we need to add some margins while scaling / such that SRAMs preserves data. Therefore, in order to get the best advantage of rail-torail scaling, it is desirable to reduce leakage current level of SRAMs in the FF corner (FF corner of threshold voltage) to that in the TT/SS corners by using adaptive body biasing. This technique not only reduces the margins in scaling / but also reduces the overall leakage current. Even though there is some area overhead, it is much less than using bit-cells with more 6T (e.g., [1]). In SRAM design, the Data Retention Voltage (DRV) defines the minimum under which the data in a memory is still preserved. Understanding DRV not only gives the insight of VDD scaling but also helps to understand VSS scaling, thus an analytical model of leakage currents mechanism and DRV is reviewed in section 2. The recent discoveries and circuit techniques in reducing leakage power have been discussed and reviewed in section 3. Section 4 shows some simulation results of how 6T bit-cells leakage current and SNM varies across process variation, rail-to-rail supply scaling, and body biasing. Rail-to-rail supply scaling with adaptive body biasing is proposed in section 5. Finally section 6 concludes our finding and future works. 2.0 Leakage Current and DRV models As shown in Fig. 1, there are three kinds of leakage current: sub-threshold leakage, gate leakage, and junction leakage. When is reduced to DRV, the sub-threshold leakage dominates, thus the destruction of cell data (hold failure) in standby mode is a strong function of the subthreshold leakage of NMOS transistor connected to the node storing 1 [3]. When an SRAM cell is in standby mode, the currents at the storage nodes are balanced. Node : + = , (1) Node : + = , (2) Assuming that = 0 and = (3) Since the bit-lines are set to , is negligible and Eq. 2 becomes: Node : = , (4) In Eqs. (1, 2, 4), is the current of the transistor (Fig. 1) in the sub-threshold region, thus can be modeled as exponential function as in BJT [3]: = e

.e

. 1 e

(5)

where Si is the transistor (W/L) ratio; I0 is a process-specific current at VGS=Vth for a transistor with W/L=1; T is the chip temperature; and ni is the sub-Vth factor (~60mV at room temperature). We further define: =
.

(6)

When scales down to DRV, the voltage transfer curves (VTC) of the two storage nodes degrades such that

SNM of the cell becomes zero. This condition is given by [3]:

when = , =

(7)

wake up power penalty incurred during transitions between two modes. Therefore, this power trade-off is an important system-design parameter.

Fig. 1: Standard 6T SRAM cell [6]

(a) (b) Fig. 2: VDD scaling leakage reduction schemes. (a) dynamic sleep transistor (b) canary bit-cell [4].

Substituting the current models (Eqs. 5 & 6) into Eqs. 1 & 4, we obtain the VTCs of the inverters in the cell, and together with the condition in Eq. 7, the value of the DRV can be derived. Numerical iterations are required to get a general equation. Using the approximation in Eq. 3, we can avoid the iterations and estimate the initial of DRV (DRV1): = The final expression for DRV is obtained:
.

. log +

(8) = + + The above DRV formula relies on the values of Ai and ni, which are only a function of process variations in transistors, sizing Si, and temperature. Then the optimal DRV can found by capturing the leakage mechanism due to process variation.

3.0 Leakages reduction techniques 3.1. VDD scaling (DRV) VDD scaling leakage reduction techniques using dynamics sleep transistor (DST) have been studied (e.g., [3]) and implemented [7]. The standard scheme is shown in Fig. 2a. The SRAM supply rail is connected to the active VDD and the standby VDD through two big power switches. The standby VDD is generated from a adjustable DC-DC converter with high conversion efficiency. In an actual implementation, reducing VDD all the way down to DRV, however, is not possible as other random noise mechanism (e.g., noise in supply and radiation particles) will change the state of the memory cell. An overhead noise margin has to be provided to counter these unexpected noise sources. The main considerations in dual voltage design is the delay overhead due to power switch resistance, memory wake up delay, and the power penalty during mode transition. A reasonable large PMOS power switch is desirable to reduce the switch resistance and memory wake up delay. On the other hand, the net power saving over one standby period has to be larger than the

Canary bit cell is another proposed approach to bring down VDD close to DRV. Unlike DST, the core SRAM cell is a standard 6T cell as shown in Fig. 1. The VDD is determined by the Canary bit cell, which duplicates the impact of global changes on the core SRAM cell stability. Also, the canary cell must fail before the core SRAM cells to prevent data loss. The standard Canary bit cell is shown in Fig. 2b, [4]. The 1 data reset is done through M7 when wordline (W) is high. A PMOS (M8) is inserted between the supply voltage of the canary cell and VDD and the signal VCTRL gives ability to tune how large the VDD overhead is above the core cell DRV. By tracking the state of the Canary cell in feedback loop, VDD can be reduced to DRV of the Canary cell while still maintaining some headroom for the core SRAM cell. Besides considerations in common dual supply design, the Canary cells ability to track process variation of the core SRAM cell is an issue thus a good floor plan is desirable. 3.2. VSS scaling. VSS scaling can be implemented very similar to VDD scaling with dynamics sleep transistor. Specifically, the virtual VSS of the memory cell is connected to the real VSS trough a NMOS transistor. By changing the strength of NMOS transistor, virtual VSS can be scaled up. In [5], programmable NMOS bias transistors are implemented with binary-weighted N NMOS transistors to obtain 2 virtualground voltage. Similar to VDD scaling, memory wake up delay and the power penalty during mode transition still present. Also, the IR effect in the virtual VSS rail needs careful design for active mode. In standard process, the body of the NMOS is tight to the real VSS, thus if the voltage between the virtual VSS and real VSS is large, the read and write performance of the memory can be harshly affected.

3.3. Adaptive Body Biasing. The sub-threshold leakage current is exponentially dependent on Vth as in Eq. 5, thus low-Vth increases the hold failures. This is because of the fact that, lowering Vth (particularly NMOSs) increases the trip-point of the inverter. Since Vth is a function of body bias, changing the body bias effectively change the probability of hold failure. Fig. 3 shows that hold failure increase as NMOS body bias shifted to positive: almost in exponential dependency.

distribution and inter-die die process proces corner distribution makes it difficult to distinguish different process corners. However, if the memory size is large, the separation of with-die with Vth distribution from process corner Vth variation increases significantly [6]. . In other words, in large memory cell, which is usually the case in modern SoC system, the adaptive body biasing can reduce overall leakage and hold failures. 4.0 Simulation Results

Fig. 4: SNM distribution of VDD=0.3 & 1 V for different process corners.

(a)

To get a better understanding of the problem, we simulated a 6-T SRAM cell using 45 nm PTM model. NMOS and PMOS are sized to have a 80 nm width and 45 nm length. Fig. 4 shows the distribution of SNM for different corners at VDD=0.3 and 1V. The local distribution is pretty consistent across different process corners and VDD. The standard deviation () for all distributions is 5-6.6mV. The difference between different corners corners SNM mean value of VDD=1V is quite larger than that of VDD=0.3V (e.g., the difference between TT and FF is about 40 mV VDD=1V while it is only 10mV for VDD=0.3V)
Corners TT FF SS Mean (mV) 155 177 137 (mV) 13.4 12 15

(b)
Fig. 3: : (a) effect of body bias on cell failure (b) Adaptive body biasing scheme [6]

Dies in the FF corner have relatively much lower Vth than dies in SS corner, thus have more leakage current. Using adaptive body-biasing ing which is implemented using leakage monitor scheme as shown in Fig. 3b [6], we can reduce both leakage current and hold failures. The leakage current measured from the online leakage monitor in Fig. 3b is compared with the reference currents ents to identify the process corner, and then the appropriate body bias voltage is applied to the SRAM array. The he overlapping of with-die with Vth

Fig. 5: DRV distribution for different process corners.

Similar to SNM behavior at low VDD, the DRV distribution for different process corners are overlapping quite a lot as shown in Fig. 5. . The difference of means between FF and SS is 40mV.

Further, the he leakage current distribution of FF corner has both higher average age value and wider spread range, thus FF corner has the lower SNM, and the larger DRV requirement. The standby leakage power is then increased due to the larger DRV and leakage current.

(a) Fig. 7: SNM vs. Temperature

(b) Fig. 6: Total leakage current distribution of an SRAM for (a) TT process corner (b) all process corners

On the other hand, the total leakage current distribution has clear separation between different corners, and it is approximately a Log-Normal Normal distribution as shown in Fig. 6a. . The mean of leakage current in the SS corner is 2nA while in the FF corner is 76nA, which is about 40 times larger than SS corner. The in the FF corner 20nA and 0.8nA in the SS corner as shown in Fig. 6b. Fig. 7 shows SNM dependency on temperature for different VDD. The SNM sensitivity ivity to temperature is higher with larger VDD. At VDD=0.3V (or r at DRV), the variation of SNM is about 50mV for temperature range of 160 C and it changes little as temperature changes. 5.0 Design proposal and future direction Leakage current is reduced significantly by scaling / , thus a dynamics / line is desirable. DRV ( scaling) of 212mV is required in the TT process corner, but a 100mV extra guard band is desirable to prevent other random noise [3]. . Also, this extra guard band should be enough for temperature variation.

In order to reduce the leakage power and increase PVT tolerance, a dynamic / adjustable peripheral circuit is required, and more ore leakage current and hold failures can be reduced by using adaptive body biasing to shift the FF corner back to TT/SS corner. However, the penalty will be a larger bit cell area and overall SRAM area. A Another possible penalty will be a longer memory wake up time compared to a standard SRAM block with only dynamic / adjustment. In the future work, work we will study how much more power is saved using this design typology and how performance changes. Particularly, we need to understand how different transistors parameters parameter in the 6-T cell affect SNM/leakage, and how varying body-biasing body on certain transistors changes the performance. performance More importantly, we will design new or utilize the existed peripheral circuit to realize our proposed solution. 6.0 Conclusion In this paper, we have introduced the importance of standby leakage power reduction and reviewed the concept of DRV. After a short summary of several existed power reduction techniques, we did preliminary simulations to figure out how SNM/leakage/DRV changes with intraintra and inter-die die variations. With this knowledge, we proposed our PVT tolerant olerant standby leakage power reduction technique and pinpointed our future work.

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