Root Locus Compensation

Digital Control Systems

Root Locus Design of Lag Compensators

C (s) = KcD (s) = Kc

s + zo s + po

Traditional Approach Input The plant transfer function P (s), design point sd.

Design Procedure
1. Choose design point sd = |sd |ej (desired dominant closed loop poles) for transient response. Find minimum gain Kcmin at sd for steady-state accuracy.

Kcmin = |1/P (sd )|

2. Find required lead factor, to achieve desired gain ( [3, 20])

= C (0)/Kcmin
3. Choose pole po very close to the origin (po as possible the shape of the root locus near sd .

{sd }) to preserve as much

4. Find the compensator zero location that achieves required lead factor

zo = po
5. Set Kc = Kcmin to obtain compensator

C (s) = Kc

s + zo s + po

6. Verify design by simulation. If steadystate accuracy not acceptable, or transient response unacceptable, redesign.

c J.C. Cockburn

Review

Root Locus Compensation

Digital Control Systems

Root Locus Design of Digital Lag Compensators

C (z ) = KcD (z ) = Kc

z + zo z + po

Classical Approach Input The plant transfer function P (z ), Design point zd.

Design Procedure
1. Choose design point zd = |zd |ej (desired dominant closed loop poles) for transient response. Find minimum gain Kcmin at zd for steady-state accuracy.

Kcmin = |1/P (zd )|

2. Find required lead factor, to achieve desired gain ( [3, 20])

= C (1)/Kcmin
3. Choose pole po suciently close to one to preserve as much as possible the shape of the root locus near zd . 4. Find the pole location that achieves desired lead factor

zo = (1 + zo ) 1
5. Set Kc = Kcmin to obtain compensator

C (z ) = Kc

z + zo z + po

6. Verify design by simulation. If steadystate accuracy not acceptable, or transient response unacceptable, redesign.

c J.C. Cockburn

Review

Root Locus Compensation

Digital Control Systems

Design Example: Lag Compensator

Plant

1 P ( s) = s(s + 2)
Performance Specs 1. Steady state error 0.2 for a unit ramp input. 2. Damping ratio 0.707. 3. Settling time 4.5 sec. Step 0 Step 1 Control Structure: 1DOF unity feedback Acceptable Region for dominant poles

= sin( ) 0.707 = arcsin(0.707) 45 ln(1/100) 1 4 .5

Step 2

Steady State constraints

ess,1 =

1 1 2 = lim = s0 sC (s)P (s) Kv C (0)

C (0)

2 ess,1

2 = 10 .2

c J.C. Cockburn

Review

Root Locus Compensation

Digital Control Systems

Step3

Design point (from TR specs.)

sd (1 + j cot ) = 1 + j
Step 4 Compensator Design

C (s) = KcD (s) = Kc C (0) = Kc,

Step 4.1

s + zo s + po

zo [3, 20](lag factor) po

Compensator Gain (to satisfy TR specs.) 1 Kc = 2 | P ( sd ) | Lag factor (to satisfy SS specs.)

Step 4.2

C (0) =5 Kc

Step 4.3 Pole: Choose po close to the origin (po |Re {sd} |) to preserve the RL shape . Try

po = 0.02
Step 4.4 Zero:

zo = zo = 5 0.02 = 0.1
Final Design

C ( s) = 2
Step 5 Verify design
c J.C. Cockburn

s + 0 .1 s + 0.02

Review

Root Locus Compensation

Digital Control Systems

RL does not pass through design point sd. Settling time is very large (why ?).

c J.C. Cockburn

Review