Ted Borys - CSI 404

2/3/2004
Page 1-1
2004 by Ted Borys. All rights reserved.
1
Digital Logic Circuits Digital Logic Circuits
Section 1 Section 1
2
Digital Computer Digital Computer
Binary
Two discrete values
True 1 3.0 volts
False 0 0.5 volts
Very reliable
Hardware
Electronic components
Electromechanical devices
Software
Instructions and data manipulated by hardware
3
Hardware Hardware
Central Processing Unit (CPU)
Arithmetic and logic unit (ALU)
Registers holding data
Fetch and execute control circuits
Random Access Memory (RAM)
Input Output Processor (IOP)
Transfer data between computer and outside world
Input, output, and input/output (I/O) devices
4
Definitions Definitions
Computer organization
How hardware components interoperate within the
computer system
Computer design
Determine which hardware should be used and how
parts are connected
Computer architecture
User perspective of computer structure and behavior
Design deals with component specs and combining
them to build a computer
5
Logic Gate Logic Gate
Input
One or two signal lines
Naming convention: A and B
Output
One signal line
Naming convention: x
Process
Binary logic function
6
Logic Gates Logic Gates
AND
OR
Exclusive-OR
Buffer
NAND
NOR
Exclusive-NOR
Inverter
Ted Borys - CSI 404
2/3/2004
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2004 by Ted Borys. All rights reserved.
7
AND AND
algebraic function
x = AB
1 1 1
0 0 1
0 1 0
0 0 0
x B A
truth table
graphic symbol
A
B
x
8
OR OR
algebraic function
x = A + B
1 1 1
1 0 1
1 1 0
0 0 0
x B A
truth table
graphic symbol
A
B
x
9
Exclusive Exclusive- -OR OR
algebraic function
x = A B
x = AB + AB
0 1 1
1 0 1
1 1 0
0 0 0
x B A
truth table
graphic symbol
x
A
B
10
Buffer Buffer
graphic symbol
algebraic function
x = A
1 1
0 0
x A
truth table
A x
11
NAND NAND
algebraic function
x = (AB)
0 1 1
1 0 1
1 1 0
1 0 0
x B A
truth table
graphic symbol
A
B
x
12
NOR NOR
algebraic function
x = (A + B)
0 1 1
0 0 1
0 1 0
1 0 0
x B A
truth table
graphic symbol
A
B
x
Ted Borys - CSI 404
2/3/2004
Page 1-3
2004 by Ted Borys. All rights reserved.
13
Exclusive Exclusive- -NOR NOR
1 1 1
0 0 1
0 1 0
1 0 0
x B A
truth table
graphic symbol
A
B
x
algebraic function
x = (A B)
x = AB + AB
14
Inverter Inverter
graphic symbol
algebraic function
x = A
0 1
1 0
x A
truth table
A x
15
Logic Gates >2 Inputs Logic Gates >2 Inputs
AND
x = 1 if and only if all inputs = 1
OR
x = 1 if any input = 1
Exclusive-OR
x = 1 if an odd number of inputs = 1
16
Logic Gates >2 Inputs Logic Gates >2 Inputs
NAND
Complement of AND
NOR
Complement of OR
Exclusive-NOR
Complement of exclusive-OR
17
Boolean Algebra Boolean Algebra
Deals with binary variables and logic operations
Variable naming convention: A, B, x, y
Boolean function can yield either 0 or 1
Truth table for n variables has 2
n
rows
Algebraic expression can be expressed as a
combination of AND, OR, and Inverter gates
Goal is to simplify circuits by reducing gates
18
F = x + F = x + yz yz
0 1 1 0
1 0 0 1
1 1 0 1
1 0 1 1
1
0
0
0
x
1 1 1
1 0 1
0 1 0
0 0 0
F z y
x
y
z
F
Ted Borys - CSI 404
2/3/2004
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2004 by Ted Borys. All rights reserved.
19
Boolean Algebra Identities Boolean Algebra Identities
Basic postulates
1x = x identity element
0 + x = x identity element
xx = 0 inverse element
x + x = 1 inverse element
xy = yx commutative law
x + y = y + x commutative law
x(y + z) = xy + xz distributive law
x + yz = (x + y)(x + z) distributive law
20
Boolean Algebra Identities Boolean Algebra Identities
Derivations
x0 = 0
x + 1 = 1
xx = x
x + x = x
x(yz) = (xy)z associative law
x + (y + z) = (x + y) + z associative law
(xy) = x + y DeMorgans theorem
x + yz = (x + y)(x + z) DeMorgans theorem
(x) = x
21
Reduction Example Reduction Example
F = ABC + ABC + AC 6 gates
F = AB(C + C) + AC
F = AB + AC 4 gates
22
Another Reduction Example Another Reduction Example
F = ABC + ABC + AC 6 gates
F = AC(B + B) + AC
F = AC + AC
F = A(C + C)
F = A no gates!
23
Karnough Karnough Map Map
Helps reduce Boolean function complexity
Transforms a Boolean function truth table
into a picture
Combination of input variable values for each
truth table row is called a minterm
It is a binary number that is converted to decimal
Truth table can be expressed at the sum of the
minterms that generate a value of 1
24
Minterm MintermExample Example
0 1 1 0
1 0 0 1
1 1 0 1
1 0 1 1
1
0
0
0
x
1 1 1
1 0 1
0 1 0
0 0 0
F z y
F = x + yz
F (x, y, z) = (2, 4, 5, 6, 7)
Ted Borys - CSI 404
2/3/2004
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2004 by Ted Borys. All rights reserved.
25
Two Two- -Variable Map Variable Map
3 2 1
1 0 0
1 0
A
B
A
B
26
Three Three- -Variable Map Variable Map
6 7 5 4 1
2 3 1 0 0
10 11 01 00
A
BC
A
C
B
27
Four Four- -Variable Map Variable Map
10 11 9 8 10
14 15 13 12 11
6 7 5 4 01
2 3 1 0 00
10 11 01 00
AB
CD
A
B
D
C
28
Simplification Rules Simplification Rules
Insert a 1 into each square that the function
generates a value of 1
Form one or more rectangles by grouping
together adjacent squares containing a 1
Number of squares in each rectangle must be a
power of 2
Top and bottom squares in a column are adjacent
Left- and right-most squares in a row are adjacent
All four corner squares are adjacent
Minimize number of rectangles
29
Redo Reduction Example Redo Reduction Example
F = ABC + ABC + AC
1 1 1
1 1 0
10 11 01 00
A
BC
A
C
B
1 1 1 0
0 0 0 1
0 1 0 1
1 0 1 1
1
0
0
0
A
1 1 1
0 0 1
1 1 0
0 0 0
F C B
F = AB + AC
30
Logically Equivalent Logically Equivalent
Sum of products
Function generates a 1
F = AB + AC
Two AND gates ORed together
Product of sums
Function complement generates a 0
F = AB + AC
F = (A + B)(A + C)
Two OR gates ANDed together
Ted Borys - CSI 404
2/3/2004
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2004 by Ted Borys. All rights reserved.
31
Complement Example Complement Example
F = AB + AC
1 1 1
1 1 0
10 11 01 00
A
BC
A
C
B
F = AB + AC
F = (A + B)(A + C) 32
Don Don t t- -Care Conditions Care Conditions
Sometimes it doesnt matter if the function
generates a 1 or a 0 for a given minterm
Mark those squares on the map with an X
Can use the dont care squares to further
simplify the algebraic expression
33
Combinational Circuit Combinational Circuit
Cluster of logic gates with some number of
inputs and outputs
Output values are determined by the binary
computations performed on the input values
Can be described by
A truth table
A Boolean function for each output
34
Half Half- -Adder Adder
Add 2 bits of input and generate 2 bits of output
Input bits are called augend and addend
Input symbols are x and y
Output bits are called sum and carry
Output symbols are S and C
35
Half Half- -Adder Adder
1
0
0
0
C
0
1
1
0
S
1 1
0 1
1 0
0 0
y x
truth table
x
y
S
C
S = xy + xy = x y
C = xy

36
Full Full- -Adder Adder
Add 3 bits of input and generate 2 bits of
output
Input bits are called augend, addend, and carry
Input symbols are x, y, and z
Output bits are called sum and carry
Output symbols are S and C
Ted Borys - CSI 404
2/3/2004
Page 1-7
2004 by Ted Borys. All rights reserved.
37
Full Full- -Adder Adder
0 1 1 1 0
1 0 0 0 1
0 1 1 0 1
0 1 0 1 1
1
1
0
0
y
1
0
0
0
C
1
1
1
0
S
1 1
0 0
1 0
0 0
z x
S = x y z
C = xy + (x y)z
x
y
z
S
C
FA
38
Flip Flip- -Flops Flops
Binary cell that can hold the value of one bit
Two outputs
Normal value
Complement
Maintains state until next clock pulse
39
Flip Flip- -Flop Types Flop Types
SR
Set Reset
D
Data
JK
Like Set Reset, except both on causes output bit flip
T
Toggle
40
SR SR Flip Flip- -Flop Flop
Indeterminate ? 1 1
Set to 1 1 0 1
Clear to 0 0 1 0
No change Q(t) 0 0
Q(t+1) R S
41
D D Flip Flip- -Flop Flop
Set to 1 1 1
Clear to 0 0 0
Q(t+1) D
42
JK JK Flip Flip- -Flop Flop
Complement Q(t) 1 1
Set to 1 1 0 1
Clear to 0 0 1 0
No change Q(t) 0 0
Q(t+1) K J
Ted Borys - CSI 404
2/3/2004
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2004 by Ted Borys. All rights reserved.
43
T T Flip Flip- -Flop Flop
Complement Q(t) 1
No change Q(t) 0
Q(t+1) T
T
44
Edge Edge- -Triggered Flip Triggered Flip- -Flop Flop
Synchronize state change during clock pulse
transition
Rising edge (positive)
Falling edge (negative)
cant change can change
45
Flip Flip- -Flop Excitation Table Flop Excitation Table
What input values generate a given pair of
current and next values of Q?
46
SR SR Flip Flip- -Flop Flop
Indeterminate ? 1 1
Set to 1 1 0 1
Clear to 0 0 1 0
No change Q(t) 0 0
Q(t+1) R S
X
0
1
0
S
0 1 1
1 0 1
0 1 0
X 0 0
R Q(t+1) Q(t)
Excitation Characteristic
47
D D Flip Flip- -Flop Flop
Set to 1 1 1
Clear to 0 0 0
Q(t+1) D
1
0
1
0
D
1 1
0 1
1 0
0 0
Q(t+1) Q(t)
Excitation Characteristic
48
JK JK Flip Flip- -Flop Flop
Complement Q(t) 1 1
Set to 1 1 0 1
Clear to 0 0 1 0
No change Q(t) 0 0
Q(t+1) K J
X
X
1
0
J
0 1 1
1 0 1
X 1 0
X 0 0
K Q(t+1) Q(t)
Excitation Characteristic
Ted Borys - CSI 404
2/3/2004
Page 1-9
2004 by Ted Borys. All rights reserved.
49
T T Flip Flip- -Flop Flop
Complement Q(t) 1
No change Q(t) 0
Q(t+1) T
0
1
1
0
T
1 1
0 1
1 0
0 0
Q(t+1) Q(t)
Excitation Characteristic
50
Sequential Circuit Sequential Circuit
Flip-flops and gates connected together
Combinational circuit block
Gates only
Input from external sources and flip-flop output
Output goes to external destinations and flip-flops
Flip-flops
Input from clock and combinational circuit
Output to external destinations and combinational
circuit
51
Sequential Circuit Block Diagram Sequential Circuit Block Diagram
Combinational
circuit
Flip-flops
Clock
Inputs
Outputs
Time sequence of external inputs, external outputs,
and internal flip-flop binary states
52
Sequential Circuit Diagram Sequential Circuit Diagram
Q
Q
SET
CLR
D
Q
Q
SET
CLR
D
Clock
A
A
B
B
x
y
D
A
= Ax + Bx
D
B
= Ax
y = Ax + Bx
53
State Table for Sequential Circuit State Table for Sequential Circuit
0 0 1 1 1 1
1 0 0 0 1 1
0 0 1 1 0 1
1 0 0 0 0 1
0 1 1 1 1 0
1 0 0 0 1 0
0 1 0 1 0 0
0 0 0 0 0 0
y B A x B A
Out Next In Present D
A
= Ax + Bx
D
B
= Ax
y = Ax + Bx
54
State Diagram State Diagram
Same information as state table
Different representation
Circle is state
Flip-flop values inside
Line connecting circles is transition
input value / output value for present state
Ted Borys - CSI 404
2/3/2004
Page 1-10
2004 by Ted Borys. All rights reserved.
55
State Diagram of Sequential Circuit State Diagram of Sequential Circuit
00 10
01 11
0 0 1 1 1 1
1 0 0 0 1 1
0 0 1 1 0 1
1 0 0 0 0 1
0 1 1 1 1 0
1 0 0 0 1 0
0 1 0 1 0 0
0 0 0 0 0 0
y B A x B A
Out Next In Present
0/0 1/0
1/0
1/0
0/1
0/1
1/0
56
Design Problem Design Problem
Clocked sequential circuit that is a two bit
binary counter
Increment when input x is 1
Remain unchanged when input x is 0
Construct
State diagram
Excitation table
Logic circuit diagram
57
Binary Counter State Diagram Binary Counter State Diagram
00
01
10
11
x = 0
x = 0
x = 0
x = 0
x = 1 x = 1
x = 1 x = 1
58
Binary Counter Excitation Table Binary Counter Excitation Table
1
0
0
0
X
X
X
X
K
A
X
X
1
0
X
X
1
0
J
B
X
X
X
X
1
0
0
0
J
A
1 0 0 1 1 1
0 1 1 0 1 1
X 1 1 1 0 1
X 0 1 0 0 1
1 0 1 1 1 0
0 1 0 0 1 0
X 1 0 1 0 0
X 0 0 0 0 0
K
B
B A x B A
Flip-flop inputs Next In Present
59
Map For Each Flip Map For Each Flip- -Flop Input Flop Input
X X X X
1
A
x
B
J
A
= Bx
X X 1
X X 1
A
x
B
J
B
= x
1
X X X X
A
x
B
K
A
= Bx
1 X X
1 X X
A
x
B
K
B
= x
60
Binary Counter Logic Diagram Binary Counter Logic Diagram
J
A
= Bx
K
A
= Bx
J
B
= x
K
B
= x
J
Q
Q
K
SET
CLR
J
Q
Q
K
SET
CLR
Clock
x
A
B