DOC/LP/01/28.02.

2002

LESSON PLAN
LP VL9221
Sub Code/Name: VL9221-CAD FOR VLSI CIRCUITS LP Rev. No: 00
Unit : I
Branch : EC
Semester: III Date: 28/06/13
Page 01 of 06
UNIT I

VLSI DESIGN METHODOLOGIES

Syllabus:
Introduction to VLSI Design methodologies - Review of Data structures and
algorithms -Review of VLSI Design automation tools - Algorithmic Graph
Theory and Computational Complexity - Tractable and Intractable problems general purpose methods for combinatorial optimization.

Objective:
To understand the VLSI design methodologies and to various design
automation tools.
Session
No.
1
2

Topics to be covered

Time

Ref

Introduction to VLSI Design methodologies

Review of Data structures and algorithms

50m
50m

Review of VLSI Design automation tools

50m

Algorithmic Graph Theory

50m

5
6

Computational Complexity
Tractable problems

50m
50m

7
8

Intractable problems
General purpose methods for combinatorial
optimization.

50m
50m

1(1-3)
1(3- 5)
2(6-7)
1(11-19)
2(8-11)
1(21-24)
2(22-24)
1(41-42)
1(42-44)
2(28-29)
1(44-50)
1(53-79)

General purpose methods for combinatorial

optimization (cont.)

50m

1(53-79)

Teaching
Method
BB/PPT
BB/PPT
BB/P PT
BB/PPT
BB/PPT
BB/PPT
BB/PPT
BB/PPT

BB/PPT

DOC/LP/01/28.02.2002

LESSON PLAN
LP VL9221
Sub Code/Name: VL9221-CAD FOR VLSI CIRCUITS LP Rev. No: 00
Unit : II
Branch : EC
Semester: III Date: 28/06/13
Page 01 of 06
UNIT II

DESIGN RULES

Syllabus:
Layout Compaction - Design rules - problem formulation - algorithms for
constraint graph compaction - placement and partitioning - Circuit
representation Placement algorithms partitioning
Objective:
To understand the various design rules, Symbolic layout and Constraint-graph
compaction.
Session
No.

Topics to be covered

Teaching
Method

Time

Ref
1(83-84)
2(31-36)
1(84-85)
2(36-46)
1(86-90)
1(91-97)
2(65-73)

BB/PPT

10

Layout Compaction

50m

11

Design rules

50m

12
13

problem formulation
algorithms for constraint graph
compaction

50m
50m

14

algorithms for constraint graph

compaction

50m

1(91-97)
2(65-73)

BB/PPT

15

placement and partitioning

50m

BB/PPT

16
17

Circuit representation
Placement algorithms

50m
50m

1(101-102)
2(107-109)
1(102-105)
1(106-110)
2(112-119)

18

partitioning

50m

1(112-118)
2(173-182)

BB/PPT

CAT-I

75m

BB/PPT
BB/PPT
BB/PPT

BB/PPT
BB/PPT

DOC/LP/01/28.02.2002

LESSON PLAN
LP VL9221
Sub Code/Name: VL9221-CAD FOR VLSI CIRCUITS LP Rev. No: 00
Unit : III
Branch : EC
Semester: III Date: 28/06/13
Page 01 of 06
UNIT III

FLOOR PLANNING

Syllabus:
Floor planning concepts - shape functions and floor plan sizing - Types of local
routing problems - Area routing - channel routing - global routing - algorithms
for global routing.
Objective:

To understand the concepts of floor planning and various routing

algorithms.

Session
Topics to be covered
No.
19
Floor planning concepts

Time

Ref

Teaching
Method
BB/PPT

50m

1(119-124)
1(125-126)
2(183-286)
1(126-129)
2(286-289)
1(133-134 )
2(193-194)

BB/PPT

20

shape functions

50m

22

floor plan sizing

100m

23

Types of local routing

problems

50m

25

Area routing

100m

1(134-135 )
2(195-198)

BB/PPT

26

channel routing

50m

1(138-146)
2(200-209)

BB/PPT

27

global routing

50m

1(150-153)

BB/PPT

28

Algorithms
routing.

50m

1(154-163)
2(210-212)

BB/PPT

for

global

BB/PPT
BB/PPT

DOC/LP/01/28.02.2002

LESSON PLAN
LP VL9221
Sub Code/Name: VL9221-CAD FOR VLSI CIRCUITS LP Rev. No: 00
Unit : IV
Branch : EC
Semester: III Date: 28/06/13
Page 01 of 06
UNIT IV

SIMULATION

Syllabus:
Simulation - Gate-level modeling and simulation - Switch-level modeling and
simulation - Combinational Logic Synthesis - Binary Decision Diagrams - Two
Level Logic Synthesis.
Objective: To introduce the fundamental concepts of various modeling and simulations and
synthesis.
Session
No.
29

Topics to be covered

Time

Ref

Teaching
Method
BB/PPT

Simulation

50m

1(167-168)

30

Gate-level modeling

50m

1(171)

BB/PPT

31

Switch-level modeling

50m

1(170)

BB/PPT

32

Gate-level modeling simulation

50m

1(169-176)

BB/PPT

33

Switch-level modeling simulation

50m

1(180-183)

BB/PPT

34

Combinational Logic Synthesis

50m

1(195-199)

BB/PPT

35

Binary Decision Diagrams

50m

1(201-219)

BB/PPT

36

Two Level Logic Synthesis

50m

1(222-225)

BB/PPT

37

Two Level Logic Synthesis

50m

1(222-225)

BB/PPT

CAT-II

180m

DOC/LP/01/28.02.2002

LESSON PLAN
LP VL9221
Sub Code/Name: VL9221-CAD FOR VLSI CIRCUITS LP Rev. No: 00
Unit : V
Branch : EC
Semester: III Date: 28/06/13
Page 01 of 06

UNIT V MODELLING AND SYNTHESIS

Syllabus:
High level Synthesis - Hardware models - Internal representation - Allocation assignment and scheduling - Simple scheduling algorithm - Assignment
problem High level transformations.
Objective:
To understand the concept of various synthesis and scheduling algorithm in CAD VLSI.
Session
No.
38

Topics to be covered

Time

Ref

High level Synthesis

50m

1(235-237)

Teaching
Method
BB/PPT

39

Hardware models

50m

1(237-238)

BB/PPT

40

Internal representation

100m

1(239-245)

BB/PPT

42

Allocation

50m

1(247-251)

BB/PPT

44

assignment and scheduling

100m

1(247-251)

BB/PPT

46
48
51

Simple scheduling algorithm

Assignment problem
High level transformations
CAT-III

100m
50m
50m
75m

1(253-260)
1(261-265)
1(266-270)

BB/PPT
BB/PPT
BB/PPT

DOC/LP/01/28.02.2002

LESSON PLAN
LP VL9221
Sub Code/Name: VL9221-CAD FOR VLSI CIRCUITS LP Rev. No: 00
Unit : I -V
Branch : EC
Semester: III Date: 28/06/13
Page 01 of 06
Course Delivery Plan:
Week
UNIT

I II I II I II I II

I II I II I II
C
A
1 1 1 1 1 2 2 2 2
3 3 3 3
T
1

10

11

12

13

I II I II I II I II I II I II
C
C
A
A
3 4 4 4 4 4
5 5 5 5
T
T
2
3

REFERENCES:
1. S.H. Gerez, "Algorithms for VLSI Design Automation", John Wiley & Sons, 2002.
2. N.A. Sherwani, "Algorithms for VLSI Physical Design Automation", Kluwer Academic
Publishers, 2002.

Signature
Name
Designation
Date

Prepared by

Approved by

Mrs.R.Gayathri

Dr.S.Ganesh Vaidyanathan

AP

HOD-EC