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This article discusses the structural and connective considerations involved in multisheet design, then describes the different browsing tools that let you verify net connectivity across source documents.
Engineers turn to multi-sheet design for various reasons, the primary one being project size; some projects are too large or complex to fit on a single sheet. Even when the design is not particularly complicated, there can be advantages in organizing the project across multiple sheets. For example, the design may include various modular elements. Maintaining these modules as individual documents would allow several engineers to work on a project at the same time. Another reason is that this method allows you to use small format printing, such as laser printers. There are two decisions to make for each multi-sheet project - the structural relationship of the sheets and the method employed for electrical connectivity between circuitry on those sheets. Your choices will vary according to the size and type of each project and your personal preferences.
When your multi-sheet project is compiled, the logical relationship between the modular blocks of the design is realized and a structural framework is created. This is a tree structure, beginning with the schematic top sheet and branching down to include all other schematic sub-sheets and HDL files at one level or another. Figure 1 shows two examples of compiled design hierarchy. On the left, the structural hierarchy for a compiled PCB design project (*.PrjPcb). On the right, the structural hierarchy for a compiled FPGA design project (*.PrjFpg).
Previous versions of Protel incorporated a Schematic Editor which allowed schematic sub-sheets to be represented by components as an alternative to sheet symbols. When you open a legacy database in Altium Designer, any such components will automatically convert into sheet symbols with appropriately labeled sheet entries.
Figure 1. Compiled multi-sheet design projects showing the hierarchical relationship between source documents.
Top-Down Design
The following commands are available that allow you to build the hierarchy of your design in a top-down fashion:
It is important to remember that for hierarchical designs a project can contain only one top sheet; all other source documents must be referenced by sheet symbols. No sheet symbol may reference the sheet its on, or any sheet higher up the ladder, as this will create an irresolvable loop in the structure.
Create sheet from symbol use this schematic editor command to create a sheet below the nominated sheet symbol. Matching Ports will be added to the sub-sheet, ready to wire. Create VHDL file from symbol use this schematic editor command to create a shell VHDL file, with an entity declared that includes port definitions to match the sheet entries in the nominated symbol. Create Verilog file from symbol use this schematic editor command to create a Verilog file, with a module declared that includes port definitions to match the sheet entries in the nominated symbol. Push part to sheet use this schematic editor command to push a placed part onto a new schematic sub-sheet, replacing the original part on the parent sheet with a sheet symbol pointing to the new sub-sheet. Matching ports will be added and wired to the part on the sub-sheet. Right-click on a component to access this command.
Bottom-Up Design
The following commands are available that allow you to build the hierarchy of your design in a bottom-up fashion: Create symbol from sheet or HDL use this schematic editor command to create a symbol from the nominated schematic sheet, VHDL file or Verilog file. Make the sheet that is to include the sheet symbol the active document before launching this command. Convert part to sheet symbol use this schematic editor command to convert a chosen part into a sheet symbol. The symbol's Designator field will initially be set to the part's designator, with the Filename field set to the part's comment text. Change the filename to point to the required sub-sheet; change the sheet entries in accordance with the ports defined on that sub-sheet. Right-click on a component to access this command.
Figure 2. Document hierarchy is created by placing sheet symbols to represent the document below
Maintaining Hierarchy
Once you have defined the hierarchical structure of your multi-sheet design, you need to be able to maintain it. Altium Designer provides features that help you do just that.
For detailed information on this synchronization process, refer to the Synchronizing Sheet Entries and Ports section of the Sheet Symbol topic. This topic can be quickly accessed by pressing F1 while the cursor is over a placed sheet symbol.
The article Multi-Channel Design Concepts gives more information on how to capture a design with repeated sections. Refer to the tutorial, Creating a Multi-channel Design for step-by-step instructions on building a multi-channel design.
Instrumentation.SchDoc
Protection.SchDoc
These pictures show how wires can be replaced by net labels, ports and power ports, respectively. These are known as net identifiers, and will be discussed in detail in the next section. The pictures below illustrate a common misconception: that net identifiers of different types (such as net labels and ports) will connect logically if their names match. In fact, the opposite is true: different kinds of net identifiers may have distinct names, but still be wired together to form a single net.
These diagrams are all concerned with net identifiers replacing physical connections within a single sheet. What they do not show is that net identifiers give you the freedom to transfer nets between sheets in a multi-sheet project. How this happens depends upon the net identifiers used in your design, and the scope setting.
Net Identifiers
The most basic net identifiers are net labels. Their primary function is to alleviate the traffic of wire connections in a sheet. While there are ways and circumstances in which net labels can be made to correspond between sheets, you should generally consider them for local (in-sheet) connections. Ports, like net labels, will always connect locally to matching ports on the same document. Unlike net labels, ports are specifically designed for inter-sheet connections. This can happen horizontally or vertically. Horizontally is the broadest option,
AR0123 (v1.8) July 30, 2008
Net label
connects vertically if used in conjunction with ports and sheet symbols and either the Hierarchical or Automatic scope is applied. It connects horizontally to all matching net labels when the Flat scope is applied. connects vertically if it is matched to a sheet entry on the parent sheet symbol and either the Hierarchical or Automatic scope is applied. It connects horizontally to all matching ports when either the Flat or Ports Global scope is applied. always connects vertically down to a port on the sheet referenced by the symbol. connects horizontally to matching off-sheet connectors, but is limited to sheets referenced within a single, sub-divided sheet symbol. connects globally to all matching power ports across your entire project.
Port
Sheet Entry
Hidden Pin
connects globally to all hidden pins in your project that have a matching Connect To value.
For detailed information on Net Labels, Ports, Sheet Entries, Off-Sheet Connectors and Power Ports, press F1 while the cursor is over one of these placed objects.
Connectivity Examples
The following four illustrations will show how the detected or selected scope will affect the connectivity of net labels and ports in the same inter-sheet structure. The fifth shows how off-sheet connectors work.
Example 1 Hierarchical
This schematic project will automatically be detected for hierarchical scope, due to the presence of sheet entries within the sheet symbols on the parent sheet. The net labels C1 and C2 on each sub-sheet will not connect to matching net labels on the other sub-sheet, but remain within the confines of their local sheets. The ports in this example have different names, but even if they had matching names, they would not make horizontal connections with one another between sub-sheets when the hierarchical scope was in effect. Instead, ports will only make trans-sheet connections vertically, up to the parent sheet. For this to work, the port on the sub-sheet must find a matching sheet entry inside the corresponding sheet symbol. That connection may then be wired to pins or other net identifiers from the sheet entry on the parent sheet.
The presence of ports in this design, along with the absence of any sheet entries, causes the scope to automatically change to ports global. This essentially flattens the project as far as ports are concerned; they will make logical connections to all ports with matching names anywhere in the project. Net labels do not share this same ability; they will remain local to individual sheets. As this design project is flat, the top-sheet could be removed from the project and the design would still compile correctly. Remember, Altium Designer uses the project file to determine which sheets are in the design project.
This project is entirely devoid of both sheet entries and ports. This is the only case in which net labels will automatically make global connections in a multi-sheet design. These net labels will connect with all matching net labels in the project, regardless of the structure. Again, as this design project is flat, the top-sheet could be removed from the project and the design would still compile correctly.
This scope is not available through automatic detection, but has been continued in Altium Designer to provide support for legacy designs. In it, both net labels and ports make global connections with matching net identifiers in a horizontal fashion. The only way to achieve this kind of connectivity is to browse to the Options tab of the Options for Project dialog, and change the Net Identifier Scope to Global (Netlabels and ports global). As this design project is flat, the top-sheet could again be removed from the project and the design would still compile correctly (the project file itself holding the information about which source documents form the design).
In this example, the top sheet references four sub-sheets with only two sheet symbols. This is done by referencing multiple schematic files in the sheet symbols Filename field, separated by a semicolon. Off sheet connectors will then create flat connections between all sheets grouped within a single sheet symbol even if other sheets in the project are using vertical connectivity. The grouping of sheets has no effect on any net identifiers except for off-sheet connectors. It creates a haven within your design that can accommodate flat connections but this will only occur between matching off-sheet connectors. Notice how these connections are maintained within groups only. They do not cross into other groups, even if they contain off-sheet connectors with matching names.
Using Buses
Many schematics contain buses, which symbolize grouped signals. They are conventionally drawn with a greater thickness than wires, making them easy to identify. This graphical aspect of buses can be a useful tool in itself, but bused signals can also be transferred between sheets, according to the general rules of connectivity described previously.
The example circuitry in Figure 6 above contains four buses: two graphical and two logical. Logical buses are attached to net identifiers (net labels and/or ports) which use bus syntax. To understand bus syntax, consider one of the logical buses in this example more closely: These eight nodes are eligible for inclusion in a bus because they have net labels that share the same prefix, followed by a numeric suffix. The logical bus is created by a net label with the syntax D[0..7], where D is the shared prefix, and the numbers 0 and 7 mark the smallest and largest numbers in the suffix. Any non-negative numbers can be used in this suffix, and the order is only important so long as it agrees with any other net identifiers on the same bus. For example, we could change the net label D[0..7] to D[7..0], so long as we also changed the order both in the attached port and in the sheet entry it matches on the top sheet of this design. It is recommended that the net labels prefix does not end with a number, for example, Headphone[1..8] netlabel where the Headphone prefix only has alpha characters. The Headphone1[1..8] netlabel has a number 1 at the end of the prefiix which expands to Headphone11..Headphone 18, which can cause net naming conflicts in your design.
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Any combination of these options can be enabled. For example, you might want to have all filtered objects zoomed, centered and selected in the main design window, whilst applying masking to take away the clutter of other design objects.
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Figure 8 shows an example of the connective graph when navigating to a net object (bus, net, pin, bus line, wire or net identifier). This line is drawn in red, showing all of the connected net objects that you have set to display. The line is solid, meaning that the pins are connected physically, rather than logically, which would be shown by a dotted red line. Figure 9 shows an example of the connective graph when navigating to a component. Component graphs are displayed with green lines, showing the other components which are immediately connected to the component to which you have navigated. The navigation tools can operate on multiple sheets at once. Navigating to a bus or net will apply the highlighting options to all sheets where they are found. Of course, this will be hard to notice if your entire screen is filled with a single document. Crosssheet highlighting becomes helpful when the project documents are arranged (tiled) on one or more monitors. For detailed information on the Navigator panel, press F1 while the cursor is over the (focused) panel.
Spatial Navigation
At the top right of the Navigator panel is an Interactive Navigation button. Clicking this turns your cursor into a crosshair target in the active schematic document. This gives you a spatial alternative to the logical list presented in the panel itself. Click on a net to highlight all objects in the net, click on a port to jump to the sheet entry it connects to, and so on. The Navigator panels contents will update according to the object you choose. The cursor will remain in this navigation mode until you right-click or press the Esc key.
Navigating Hierarchy
Use the Up/Down Hierarchy feature, accessed by clicking on the button, to navigate up or down through the design hierarchy. If you click on a sheet entry you will be presented with the matching port on the sub-sheet, if you click on a sheet symbol you will be presented with the entire sub-sheet. To navigate up through the hierarchy, click a port to be presented with the matching sheet entry on the parent sheet. Hierarchy can also be navigated directly by pressing Ctrl and double-clicking over a port, sheet entry or sheet symbol.
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Connectivity Insight
Connectivity Insight, part of Design Insight, is interactive with the added benefit of displaying connectivity at a highly-visual, project level. Hover over a Sheet Symbol to see a preview of the child sheet as shown below. This document preview is available prior to compiling your project.
Compile your project to establish and view the connective relationship between net objects.. After compilation, hover over a net object to gain insight into the connectivity of that net object across your whole project. Alternatively, use the keyboard shortcut Alt+Double Click on any net object to show Connectivity Insight on demand. Connectivity Insight shows the active document displayed in preview mode, with the net information displayed as a hint. The selected net is highlighted with all other objects masked. If the net object is connected to nets on other documents, these documents will be displayed with respect to your project hierarchy, with the selected net highlighted for ease of navigation.
Figure 10. Connectivity Insight in action the active document is displayed with the selected net highlighted
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Revision History
Date 09-Dec-2003 09-Dec-2004 10-Aug-2005 30-Sep-2005 28-Nov-2005 31-Oct-2007 Version No. 1.0 1.1 1.2 1.3 1.4 1.5 Revision New product release Information added on flat designs no longer needing a top sheet Updated for Altium Designer Update to information on negating net identifiers Updated for Altium Designer 6 Updated for Altium Designer 6.8 the FirstInstance index of the Repeat statement for Sheet Symbols need to start at a value of 1 or greater and screenshots updated. 14-Mar-2008 20-May-2008 1.6 1.7 Updated Page Size to A4. Added recommendations on netlabels attached to bus objects. Added information for Connectivity Insight 30-July-2008 1.8 Revised formatting issues.
Software, hardware, documentation and related materials: Copyright 2008 Altium Limited. All Rights Reserved. The material provided with this notice is subject to various forms of national and international intellectual property protection, including but not limited to copyright protection. You have been granted a non-exclusive license to use such material for the purposes stated in the end-user license agreement governing its use. In no event shall you reverse engineer, decompile, duplicate, distribute, create derivative works from or in any way exploit the material licensed to you except as expressly permitted by the governing agreement. Failure to abide by such restrictions may result in severe civil and criminal penalties, including but not limited to fines and imprisonment. Provided, however, that you are permitted to make one archival copy of said materials for back up purposes only, which archival copy may be accessed and used only in the event that the original copy of the materials is inoperable. Altium, Altium Designer, Board Insight, DXP, Innovation Station, LiveDesign, NanoBoard, NanoTalk, OpenBus, P-CAD, SimCode, Situs, TASKING, and Topological Autorouting and their respective logos are trademarks or registered trademarks of Altium Limited or its subsidiaries. All other registered or unregistered trademarks referenced herein are the property of their respective owners and no trademark rights to the same are claimed. v8.0 31/3/08
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