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Ultra-Low Power Microcontrollers for Portable, Wearable, and Implantable Medical Electronics
Srinivasa R. Sridhara
MCU Development, Texas Instruments, Inc., 12500 TI Blvd, M/S 8661, Dallas, TX 75243, USA. E-mail: sridhara@ti.com. Phone: +1 214 567 9247
Abstract - An aging population, coupled with choices on diet and lifestyle, is causing an increased demand for portable, wearable, and implantable medical devices that enable chronic disease management and wellness assessment. Battery life specifications drive the power consumption requirements of integrated circuits in these devices. Microcontrollers provide the right combination of programmability, cost, performance, and power consumption needed to realize such devices. In this paper, we describe microcontrollers that are enabling todays medical applications and discuss innovations necessary for enabling future applications with sophisticated signal processing needs. As an example, we present the design of an embedded microcontroller system-on-chip that achieves the first sub-microwatt per channel electroencephalograph (EEG) seizure detection.

11 2 33445 6 8 7 5 76

AM AM /PM /PM

mg mg /dL /dL

32 kHz 16-bit CPU 60kB Flash MSP LCD FGSegs 4 xxx 128 Contrast Control RTC

SPI USCI_A1

2kB - RAM CR2032 BOR & SVS 16-bit Timer A 16-bit Timer B

CC1100 or CC2500

UART USCI_A1 UART TUSB3410

USB

Basic Timer

Sensor OA0 12-bit DAC

CompA 16-bit ADC TEMP

USART 12-bit DAC GPIO

DEBUG

OA1 Sensor MSP430

I.

Introduction

Fig. 1. Blood glucose meter with MSP430 MCU.

Medical electronics that enable chronic disease management, preventive healthcare, and wellness assessment have become a reality [1]-[3]. These devices include portable devices such as blood glucose meters, wearable devices such as continuous health monitors, and implantable devices such as pacemakers. Microcontrollers (MCUs) provide the right combination of features to enable this class of medical electronics [2]. A key feature for integrated circuits in personal health devices is power consumption. Battery life of these devices determines both the form factor and the ownership cost. Reducing the size and the cost leads to more widespread use of preventive health management devices, which in turn leads to reduction in fatalities due to preventable diseases. MCUs have ultra low-power consumption compared to other programmable processors. MCUs with 16-bit datapath and system power consumption as low as 160 A/MHz are available [4]. Though application specific integrated circuits can achieve lower power consumption, they lack programmability needed for mapping different medical algorithms. Families of 16-bit and 32-bit MCUs are available to match memory and performance needs of various medical applications [2]. Despite such excellent power consumption characteristics, battery life requirements of many implantable devices are not satisfied by todays MCUs. For example, an implantable medical SoC needs to consume less than 10 A on average, if it needs to operate for 10 years on a single 1 A-hour battery. Such ultra-low power operation cannot be achieved in todays devices with sophisticated signal processing needs.

Meeting these power levels will open a large opportunity for advanced therapy in severely debilitating illnesses. Achieving such ultra-low power consumption requires innovations in all aspects of the design of MCUs including system architecture, microarchitecture, circuit design, digital implementation, and process selection. In this paper, we describe the design of an embedded MCU system-on-chip (SoC) that incorporates novel system architecture with low-voltage operation in an ultra low-leakage process. An electroencephalograph (EEG) seizure detection application with less than 1 W power consumption is demonstrated on the MCU [5]. The rest of the paper is organized as follows. In Section II, we introduce MCUs that are enabling todays medical applications. In Section III, we present the system architecture innovations needed for the next generation MCU. In Section IV, we describe the circuit innovations required for low voltage operation. In Section V, we discuss the design of the medical platform MCU and present results from the implementation of the EEG seizure detection application. In Section VI, we conclude with a summary of the work.

II. Microcontrollers in Medical Devices

Microcontrollers are used in several portable medical devices including pulse oximeter, blood glucose meter, and digital thermometer. A blood glucose meter employing an MSP430 MCU is shown in Fig. 1. The internal operational amplifier (OA) is used to convert a very small current output

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from the test strip to a voltage. This OA is shut down for power management when not used. The voltage output of the OA is measured by MSP430s internal 16-bit ADC. The ADC also has an internal temperature sensor. This is used to measure the local temperature, which is required in determining the accurate glucose level. The glucose level is calculated and displayed on the LCD. A portion of the on-chip Flash memory can be used to data-log the patients glucose measurements. MSP430 operates in low-power mode running an embedded real-time clock consuming approximately 1 A [4]. The static LCD is always on, and consumes an additional 0.8 A. In total, the application runs in standby under 2 A. A glucose measurement is made 46 times a day and lasts less than 1 minute. This means that the active duty cycle is very low and has little effect on the total current consumption. The total system standby current of 2 A will allow the instrument to operate from a CR2032 220-mAh coin cell battery for over 10 years. As seen in this application, a feature of many portable medical devices is that they are intermittently used. Active duty cycle and, hence, active current consumption is very low in intermittent usage. However, there are other applications such as wearable health monitors and implantable devices that require continuous operation. For such applications, active power reduction can be achieved by a combination of system architecture innovation and low-voltage operation.

Fig. 2. Energy optimization analysis of an FFT accelerator.

needed for the voltage range of interest. As an example, Fig. 2 shows the relative energy consumption of several FFT implementation options as a function of supply voltage. The FFT implementation options differ in the number cycles taken to complete an FFT butterfly. Though both 2-cycle and 4-cycle achieve the best energy above the minimum energy point, 4-cycle FFT is preferred as it has lower area.

IV. Low-Voltage Operation

Biomedical signals tend to have useful information at frequencies less than 1 kHz [5]-[10]. Typically, processor clock frequencies for digital processing of such signals are below 1 MHz. The chosen system architecture and microarchitecture enable further reduction of the required processor clock frequency to the 10-100 kHz range. Such low clock frequencies motivate voltage scaling into subthreshold and near-threshold voltages [12]-[17]. Digital design at such ultra-low voltages requires reliable SRAMs [14]-[16], efficient DC-DC converters [17]-[18], and leakage optimized digital implementation flows. An ultra-low leakage process is important as leakage is a significant portion of the power consumption in these applications due to low-frequency operation and low duty cycles [12]-[16]. A. Low-Voltage SRAM The biggest challenge in enabling near-threshold and subthreshold operation is the reliability of SRAM bits [14]-[16]. Random dopant fluctuation and other process variations cause bit failures in traditional 6T SRAMs during read and/or write operations as supply voltage is reduced into this regime. Modifying the 6T bit cell to improve read reliability degrades write and vice versa. Bit cells with more transistors such as 8T SRAM [8], [16] that optimize read and write independently have been explored. These higher transistor bit cells require larger area and more dynamic power. An area-optimal solution is to employ periphery

III. System Architecture

Many medical algorithms routinely employ signal processing operations. For example, finite impulse response (FIR) filtering is employed to remove DC and other spurious frequency domain components from biomedical sensor data [6]. Fast Fourier transform (FFT) is employed in epilepsy detection to identify data signatures in specific frequency bins [7]. General-purpose MCUs are ill-suited to efficiently implement FIR filtering and FFT processing. It has been shown in [5] that a hardware accelerator can implement an FFT at 30X lower power than a 32-bit Cortex-M3 MCU. Similarly, a hardware accelerator is shown to reduce the power consumption of a finite impulse response (FIR) filter by 144X compared to an MSP430 [8]. Therefore, system architecture for such applications needs to incorporate a judicious combination of programmable and hard-wired processing elements to ensure the ability to map different algorithms, while consuming significantly lower power than fully programmable architectures. Other useful accelerators include median filter for noise spike removal and CORDIC for trigonometric functions [8]. Depending on the targeted applications, a single hardware accelerator [5] or a suite of accelerators [8] is appropriate. At the microarchitecture level, several options exist for signal processing accelerator implementation [11], [12] that trade-off leakage power, dynamic power, memory bandwidth, and run time. To obtain the best energy at the application level, an energy-optimal microarchitecture is

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assist techniques that enable lowering the supply voltage of the 6T SRAM without sacrificing the reliability [5]. 6T SRAMs with assist circuits cannot operate at as low voltages as 8T SRAMs but provide significant area and power benefits. B. Low-Voltage Digital Design Leakage minimization and hold timing closure are essential aspects of digital design for low voltage operation. As voltage and clock frequency are reduced, the dynamic power reduces leading to leakage power becoming a larger portion of the total power consumption. To obtain the full benefit of voltage scaling, leakage power must be reduced by employing techniques such as power gating and near minimum width transistors for 1X drive strength cells in the standard cell library. As voltage is reduced, the sensitivity of delay to local variation among transistors increases. Specifically, a combination of fast data path and relatively slow clock path can cause hold violations. A digital design flow that emphasizes hold timing closure is needed and additional hold buffering should be considered. C. Power Delivery Efficient power delivery is necessary to ensure full benefit of voltage scaling. Without the ability to deliver power efficiently at ultra-low power loads, the power savings achieved from the architectural features of the system, which enable low voltage operation, will not translate into significantly increased battery life. Linear regulators have poor efficiency as the voltage drop across them increases. DC-DC converters are an alternative that achieve high efficiency. Two options exist for on-chip DC-DC converters: inductor-based buck and switched capacitor. Buck converters have small area but require off-chip inductors [5]. Switched capacitor converters employ on-chip capacitor networks but have larger area [16].

Fig. 3. Embedded MCU medical platform and demonstration setup.

V. Medical Embedded Processor SoC

In this section, we describe an embedded processor SoC using an ARM Cortex-M3 suitable for mapping medical applications requiring microwatt power consumption. Ultra-low power operation is achieved via 0.5-1.0 V operation, a 28 fW/bit fully differential subthreshold 6T SRAM, a 90%-efficient DC-DC converter, and a 100-nJ fast Fourier transform (FFT) accelerator that reduces processor workload. Using a combination of novel circuit design, system architecture, and SoC implementation, the first sub-microwatt per channel electroencephalograph (EEG) seizure detection is demonstrated. A. SoC Design The system architecture combines a 32-bit ARM Cortex-M3 (CM3) microcontroller, an FFT accelerator,

a memory subsystem, a DC-DC converter, a power management unit (PMU), and several peripheral components to interface with external devices such as analog-to-digital converters (ADC) as shown in Fig. 3. These are interconnected by a shared system bus, where CM3, FFT, direct memory access (DMA), and ADC interface have the ability to initiate a memory transaction, while all the other peripherals can only receive a transaction. The FFT accelerator employs radix-2 butterfly architecture with a throughput of 4 cycles per butterfly [5]. This architecture requires less than 15K gates and employs a hardware multiplier and two hardware adders. Signal to quantization noise of 65 dB is achieved via a bit-width optimal block floating-point architecture, which optimizes the precision requirement to 16-bit real and imaginary data. The 32-bit memory access per cycle matches the Cortex-M3 system bus. Increasing the throughput further requires additional memory bandwidth [12] and is not beneficial as seen in Fig. 2. The accelerator consumes 100 nJ to compute a 256-point real FFT. We have designed the first fully differential subthreshold 6T SRAM capable working at 0.5 V [5]. The SoC integrates 16 banks of 2 kB SRAM, which employs an area-optimized 1.95 m2 6T bit cell. With the help of floating supply write assist, the SRAM achieves 5 reliability at low voltages in the presence of local process variations. The SRAM is operational down to 0.5 V consuming 5 nW/kHz and retains data till 0.3 V consuming 28 fW/bit. Compared to the 0.13-m 6T subthreshold SRAM in [15], the proposed SRAM employs a 2.5X smaller bit cell, consumes 3 orders of magnitude lower leakage, and provides differential reads. The buck DC-DC converter is capable of efficiently delivering power at ultra-low load levels [5]. In this architecture [18], frequency is the independent variable directly regulated by the PI-law control loop, which automatically compensates for variability due to process and temperature. Extremely low quiescent losses are achieved by employing 1K-gate digital controller. The DC-DC converter achieves 62-90% efficiency 1-100 W load @ 0.75 V, while [3] achieves 80-86% efficiency over a 1-100 load @ 0.5V. The medical platform is implemented in 0.13m CMOS

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Technology Voltage Dynamic Power - Core Dynamic Power - SRAM Leakage Power - SRAM Area Core Area SRAM Area DC-DC Performance
2.98 mm

0.13-m CMOS 0.5 1.0 V 29 nW/kHz (0.5 V) 114 nW/kHz (1.0 V) 5 nW/kHz (0.5 V) 19 nW/kHz (1.0 V) 7 nW @ 0.3 V 28 fW/bit 1.6 mm2 1.3 mm2 1.95 m2 bit cell 0.04 mm2 7 kHz (0.5 V) 5 MHz (1 V)

EEG Signal

Collect 1 s of data every 0.5 s

Convert to frequency domain (FFT)

BG= bg[n] + (1-) bg[n-1] R = FG/BG Seizure Detection: R > THRESHOLD

Collect frequencies in sub-band 1

Calculate Energy

DC-DC
4-point median filter once every 1 s

FFT
SRAM
2.98 mm
120-point median filter once every 1 s

Cortex-M3

SRAM

FG

bg

SRAM

Fig. 5. EEG seizure detection: algorithm and demonstration.

Fig. 4. Chip microphotograph and SoC metrics.

technology [5]. The digital logic portion of the SoC is implemented using a synthesis and place-and-route flow customized towards leakage minimization and hold timing closure. Hold timing closure ensures 0.5-1.0 V operation of the digital design. The standard cell library is optimized for low gate capacitance and leakage current by employing near minimum width transistors for 1X drive strength cells. Extensive clock and power gating are employed to reduce active and standby power, respectively. The chip microphotograph of the 2.98x2.98-mm2 SoC is shown in Fig. 4. The metrics of SoC are also summarized in the figure. The maximum clock frequency of operation is 5 MHz at 1V and 7 kHz at 0.5 V. The dynamic power consumption for Cortex-M3 is 29 nW/kHz. B. Epileptic Seizure Onset Detection One of emerging medical applications with sophisticated signal processing needs and ultra-low power requirements is implantable closed-loop neuro-stimulation. A specific example is the deep-brain stimulation (DBS) system for epilepsy with 40-50 million patients worldwide [3]. DBS system requires three key components: sensing electrodes to capture electroencephalograph (EEG) in digital samples, a signal processing engine to detect an epileptic seizure onset, and stimulation device to generate neuro-stimulus signals to prevent epilepsy or mitigate its intensity [19]. Since the seizure monitoring needs to be always active, the sensing electrodes and signal processing engine are always powered

up. Therefore, ultra-low power seizure detection leads to longer battery life in closed-loop neuro-stimulation systems. Fig. 5 shows the flow chart of the implemented epileptic seizure onset detection algorithm [7]. The sampling frequency for EEG data is 256Hz and every 0.5 s a 256-point FFT is run on the 1-second long input data with 50% overlap in time. First, the energy in the band is computed at every 0.5-second. Then, a 4-point median filter produces the foreground (FG) signals and, using the two newly computed FGs, a 120-point median filter is run to produce an intermediate background signal (bg). The final background signal (BG) is computed using a simple IIR filtering: BG[n] = bg[n] + (1- )bg[n-1], where is the filter coefficient. Then, the ratio of FG over BG is computed and compared against a threshold to detect a potential epileptic seizure onset event. We implemented the epileptic seizure onset detection algorithm and the validation set-up is presented in Fig. 3, where the EEG data from the University of Freiburg EEG database [20] are employed. The digital samples are loaded into a waveform generator and the output is routed to a 12-bit SAR ADC. The ADC samples are fed into the test chip via the serial peripheral interface (SPI). To bring in samples, the CM3 sets up the ADC timer and the multi-channel ADC interface to control the sampling timing and then the CM3 goes to deep-sleep mode. This enables sample collection in the designated data memory location without CM3 operation. While 128 samples are collected, the multi-channel ADC interface, SRAM, and system bus are powered up. At every 128th ADC sample, the ADC interface interrupts the CM3 via wake-up interrupt control (WIC), which triggers the CM3 to power up the system and

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program the DMA to move 256-sample data block (with 50% time-domain overlap) to the FFT input buffer. Then, the CM3 kicks off a 256-point real-value FFT and goes back to a deep-sleep mode, since no further processing is required until the 256-point FFT is completed. Upon completion of the FFT computation, the accelerator interrupts the CM3 and the CM3 puts the FFT accelerator back in the power-off mode. The FFT accelerator consumes 100 nJ to compute a 256-point FFT. In [10], an equivalent bank of filters is shown to consume 234 nJ. Compared to employing the CM3 for converting the EEG data into the frequency domain, the FFT accelerator provides a 30X reduction in power consumption. This translates to an 18X power savings for the entire application. The energy computation, the FG median filtering, the BG median filtering, and the IIR filtering are executed on the CM3 via software code. To monitor the application, the CM3 outputs FG, BG, and the ratio of FG/BG via serial interface to a personal computer. The collected data is plotted in Fig. 5 to illustrate the seizure detection operation. The entire epileptic seizure onset detection is implemented on-chip. Throughput requirements of the application dictate a supply voltage of 0.8V. The entire seizure detection operation described above consumes less than 1 W at a supply voltage of 0.8V. When a 1.8-V battery is used to drive the DC-DC converter, the SoC draws less than 1 A from the battery.
slyb148a [3] International Neuromodulation Society. [Online]. Available: http://www.neuromodulation.com/mc/page.do?sitePageId=78803 [4] MSP430x5xx/MSP430x6xx Family User's Guide, Texas Instruments, Dallas, TX. [Online]. Available: http://focus.ti.com/ general/docs/lit/getliterature.tsp?literatureNumber=slau208g &fileType=pdf [5] S. R. Sridhara, M. DiRenzo, S. Lingam, S.-J. Lee, R. Blazquez, J. Maxey, S. Ghanem, Y.-H. Lee, R. Abdallah, P. Singh, and M. Goel, Microwatt Embedded Processor Platform for Medical System-on-Chip Applications, in Proc. IEEE Symp. VLSI Circuits, 2010, pp. 15-16. [6] C.-C. Tseng and S.-C. Pei, Sparse FIR notch filter design and its application, Electronics Letters, vol. 33, no. 13, pp. 1131-1133, Jun. 1997. [7] S. Ravindran and R. Cole, Low complexity algorithms for heart rate and epileptic seizure detection, in Int. Sym. Applied Sciences in Biomedical and Communication Tech., 2009, pp. 1-5. [8] J. Kwong and A. Chandrakasan, An energy-efficient biomedical signal processing platform, in Proc. European Solid State Circuits Conf., 2010, pp. 526-529. [9] A. T. Avestruz, W. Santa, D. Carlson, R. Jensen, S. Stanslaski, A. Helfenstine, and T. Denison, "A 5 W/Channel Spectral Analysis IC for Chronic Bidirectional Brain-Machine Interfaces," IEEE J. Solid-State Circuits, vol. 43, no. 12, pp. 3006-3024, Dec. 2008. [10] N. Verma, A. Shoeb, J. Bohorquez, J. Dawson, J. Guttag, and A.P. Chandrakasan, A Micro-Power EEG Acquisition SoC With Integrated Feature Extraction Processor for a Chronic Seizure Detection System, IEEE J. Solid-State Circuits, vol. 45, no. 4, pp. 804-816, Apr. 2010. [11] A. Oppenheim and R. Schaffer, Discrete-time Signal Processing. Englewood Cliffs, NJ: Prentice Hall, 1989. [12] A. Wang and A. P. Chandrakasan "A 180 mV FFT processor using subthreshold circuit techniques", in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, 2004, pp. 292-293. [13] H. Soeleman and K. Roy, "Ultra-low power digital subthreshold logic circuits", in Proc. Int. Symp. Low Power Electronics and Design, 1999, pp. 94-96. [14] M. Seok, S. Hanson, Y.-S. Lin, Z. Foo, D. Kim, Y. Lee, N. Liu, D. Sylvester, and D. Blaauw, "The Phoenix Processor: A 30 pW platform for sensor applications", in Proc. IEEE Symp. VLSI Circuits, 2008, pp. 188-189. [15] B. Zhai, S. Hanson, D. Blaauw, and D. Sylvester, A Variation-Tolerant Sub-200 mV 6-T Subthreshold SRAM, IEEE J. Solid-State Circuits, vol. 43, no.10, pp.2338-2348, Oct. 2008. [16] J. Kwong, Y. K. Ramadass, N. Verma, and A. P. Chandrakasan, A 65 nm Sub-Vt Microcontroller With Integrated SRAM and Switched Capacitor DC-DC Converter, IEEE J. Solid-State Circuits, vol. 44, no.1, pp. 115-126, Jan. 2009. [17] Y. Ramadass and A. Chandrakasan, Minimum Energy Tracking Loop With Embedded DC-DC Converter Enabling Ultra-Low-Voltage Operation Down to 250 mV in 65 nm CMOS, IEEE J. Solid-State Circuits, vol. 43, no. 1, pp. 256-265, Jan. 2008. [18] G. Wei and M. Horowitz, A Fully Digital, Energy-Efficient, Adaptive Power Supply Regulator, IEEE J. Solid-State Circuits, vol. 34, no. 4, pp. 520-528, Apr. 1999. [19] W. Santa, R. Jensen, K. Miesel, D. Carlson, A. Avestruz, G. Molnar, and T. Denison, Radios for the brain? A practical micropower sensing and algorithm architecture for neurostimulators, in IEEE Int. Symp. Circuits and Systems, 2008, pp. 348-351. [20] EEG Database - Seizure Prediction in Freiburg, Germany. [Online]. Available: https://epilepsy.uni-freiburg.de/freiburgseizure-prediction-project/eeg-database

VI. Summary and Conclusions

Microcontrollers play a key role in enabling portable, wearable, and implantable medical electronics. The ultra-low power consumption of MCUs extends the battery life of these personal health devices. Further reduction in power consumption in embedded MCU SoCs is possible via novel system architectures and low-voltage operation. Such ultra-low power operation is a must in enabling advanced signal processing algorithms for the next generation battery-powered medical devices. A medical platform MCU employing such innovations has been designed. The medical platform MCU demonstrates the first sub-microwatt EEG seizure detection.

Acknowledgements
The author thanks M. DiRenzo, S. Lingam, S. Lee, R. Blazquez, J. Maxey, S. Ghanem, R. Abdallah, Y. Lee, P. Singh, and M. Goel for contributions to the system-on-chip design. The author thanks R. Verma and M. Raju for useful discussions on microcontrollers in medical applications.

References

[1] J. Fayn and P. Rubel, Toward a personal health society in cardiology, IEEE Trans. Inf. Technol. Biomed., vol. 14, no. 2, pp. 401-409. Mar. 2010. [2] Consumer Medical Applications Guide, Texas Instruments, Dallas, TX. [Online]. Available: http://www.ti.com/litv/pdf/

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