JORGE RUBINSTEIN

Newton, MA. 02460, U.S.A. Tel. (617) 244-3775 E-mail: Jorge@ASICEng.com Update: Nov 18, 13

PROFESSIONAL SUMMARY
More than 30 years of experience in Electrical Engineering and Computer Science research, development, system design, implementation, modelling, documentation, verification and testing of electronic hardware and software. Working knowledge of all aspects of integrated circuit technology full custom, gate aray, ASIC, FPGA. Inventor, chief architect and implementer of worlds first massively parallel ultra-low power VLSI commercial video encoder. Lead designer of SoC core for multi-million dollar industrial process control product family a testimony of vision and boldness to challenge the conventional. Experience in large organizations and startups. Has managed his own engineering firm since 1985. Has solid science background, excellent computer skills, and has demonstrated mastery to manage complexity, and large engineering systems. Motivated, self starter. Effective teacher, mentor and de facto leader. Positive interpersonal skills. Good writer and communicator.

AREAS OF STRENGTH
Integrated circuit design, synthesis, test, simulation, documentation and verification. ASIC, FPGA, SOC. Computer software development. Computer architecture. Video compression. Spread spectrum. Communications. DSP. Massive computational parallelism in VLSI.

CURRENT PROFESSIONAL GOAL

Capitalize on the success of massively parallel distributed memory IC design from video compression to other areas, such as super computers and imaging processing for higher speed and lower power.

PROFESSIONAL EXPERIENCE ASIC Engineering, Inc., Newton MA Principal Engineer 1985 to Present
Involved in all aspects of business, administration, marketing, promotion, sales and engineering. List of projects: Inventor, chief architect and principal designer in its entirety of a single chip fully functional VLSI H.264 video encoder using massively parallel architecture, distributed memory and no CPU. This design is a first in its class, about 100 times more power-efficient than competing designs, covered by a number of patents. Designed an H.264 video compression core software library from the ground up. Implemented singlehandedly encoder/decoder plus live camera and display applications for teleconferencing applications in C/C++ Windows/Linux/TMS320 platforms, including relevant IP/UDP/RTP networking aspects. (Infinesse). Architected and built "System on a Chip" for process control using VHDL and synthesis before the term SoC had been coined. Integrates 186 microprocessor, HDLC, UART, dual tone FSK communications, SPI and scan testing. Verification using real embedded software. The resulting single chip became the main single component in a major product line of an entire family of successful process control products (Invensys). Serviced and client companies: Intel, EMC, Invensys/The Foxboro Company, Motorola, Maxim Integrated Products, VLSI Technology, Sanders Associates, Calcomp, Viewlogic Systems, Valid Systems, ADX/Infinesse, California Devices, SoundVision, Neurogen. See ADDITIONAL PROJECTS ASIC Engineering, Inc. at end of document

Analogic Corp., Wakefield MA - Senior Engineer -

1984 to 1985

Involved in all phases of the specification, design, test, system incorporation and production of gate array integrated circuits for vector processor products. Introduced first-time Valid Systems CAD capability for ASIC design. Innovated custom IC test capability, including the creation of modular test system software based on HP-IB. Implemented CMOS circuit for a floating point pipelined multiplier.

Digital Equipment Corporation, Hudson MA - Senior Engineer

1980 to 1983

Participated in the development of a 2.0 micron CMOS process. Designed test structures for modeling and evaluation as a foundation for undersanding latch-up and launching merged CMOS/bipolar technology. Participated in the design of a 55 nsec 4Kx4 static CMOS RAM, used as an internal standard product, and also for CMOS process characterization. The VAX chip set was later fabricated with this process. Innovated CMOS circuit analog design techniques for digital applications. Resulted in a patent in compact multi-ported pipelined memory array, requiring less layout area than traditional dual-rail designs. Coauthored with Prof. Paul Penfield Jr. of MIT an efficient hierarchical algorithm to compute tight bounds on wire delay for signals propagating through distributed RC trees. The resulting model has been widely

JORGE RUBINSTEIN referenced in technical literature, and has been used commercially with great success in timing verification of MOS digital systems, particularly gate arrays and standard cells. Ported Stanford's HP-1000 code of the MOS device simulator GEMINI to VAX/VMS. Created a fully documented, device-independent, user-formatted, general-purpose scientific data-plotting and associated three-dimensional graphics program. No such application program was available at the time. The software was later perfected and marketed as a commercial product.

EDUCATION Massachusetts Institute of Technology, Cambridge MA MSEE 1977-1979

Thesis: A Two- Dimensional Model for the Static Characteristics of the Charge-Flow Transistor. Grade point average during the Master degree program: 5.0/5.0. Qualifed for the doctoral program in Electrical Engineering and Computer Science at MIT.

Universidad Anhuac, Mexico City, Mexico BSEE CONFERENCES AND PUBLICATIONS

1972-1977

Thesis: Introduction to the Quantum Study of Matter (614 pages). Magna Cum Laude (Mencin Honorfica).

M. Kuperstein, J. Rubinstein, Implementation of an Adaptive Neural Controller for Sensory-Motor Coordination, IEEE Control Systems Mag., vol. 9, no. 3, Apr. 1989, pp. 25-30. S.D. Senturia, J. Rubinstein, S.J. Azoury, and D. Adler, Determination of the Field-Effect in LowConductivity Materials with the Charge-Flow Transistor, J. Appl. Phys., May 1981. S.D. Senturia, J. Rubinstein, S.J. Azoury, and D. Adler, Charge Centroid Determination in Field-Effect Experiments, Ninth International Conference on Amorphous and Liquid Semiconductors , Grenoble, France, July 2-8, 1981. J. Rubinstein and P. Penfield Jr., Signal Delay in RC Tree Networks, IEEE Trans. on CAD, vol CAD-2 No. 3, July 1983. F. Walczyk and J. Rubinstein, A Merged CMOS/Bipolar VLSI Process, ISSCC Dig. Tech. Papers, 1983, pp. 59-62.

PATENTS
Single Rail CMOS Register Array and Sense Amplifier Circuit Therefor. US Patent 4,792,924, Dec 20, 1988. Parallel, Pipelined, Integrated-circuit Implementation Of A Computational Engine. Pending. Multi-Bus Architecture for a Video Codec. US Patent 8,503,534 B2, Aug 6, 2013. Memory Subsystem. US Patent 8566515, Oct 22, 2013. Video Acquisition And Processing Systems. Pending.

AWARDS
IEEE Darlington Award, 1985. National Prize Best Students in Mexico, 1976.

MISCELLANEOUS TECHNICAL
Computer: C/C++, APL, LISP MS Windows,.NET, Linux, UNIX. VHDL, Verilog. Technology: ASIC, gate arrays, FPGA, full custom, standard cell, board level design.

MISCELLANEOUS
Volunteered for 5 years as treasurer for non-profit organization with 300 members. Set up and managed new overall accounting system with QuickBooks. US citizen. Languages: Fluent in English, Spanish, French and Hebrew.

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JORGE RUBINSTEIN

ADDITIONAL PROJECTS ASIC Engineering, Inc.

Designed FPGA for fault tolerant control processor combined with HDLC and Ethernet communications. Developed VHDL model and simulation of the corresponding Ethernet fault tolerant system as a verification vehicle. This design was key for a new generation of fault tolerant process control processors (Invensys). Implemented a low power ASIC multi-block design for use in industrial instrumentation, using VHDL and synthesis. This chip drives the communications and control logic of a family of battery-powered flow meters, replacing a bulkier more expensive printed circuit board component (Invensys) Created exhaustive hardware verification diagnostics for a commercial high-speed 32-bit synchronous buscontroller integrated circuit. To verify the success of a reverse engineering project (EMC). Developed verification functions for testing scan-testable ASICs in mid-range computer memory boards. To ensure successful implementation of third partys functionality (EMC). Built from scratch a VHDL verification model for INTELs programmable counter IC from INTELs design blueprints. Simulation results match full structural simulation exactly. As a result, INTEL approved the CAE vendor as an official tools supplier (Viewlogic Systems). Designed digital transmitter/receiver for wireless spread spectrum communications system, including all testing software. Used in wireless telephony (ADX). Designed a digital communications polyphase filter bank integrated circuit for wireless communications with multirate digital processing techniques. Used as spectral filter bank and for adding digital baseband channels in FDM communications (ADX). Designed a digital controller FPGA for a digital camera. Controls NTSC video, audio, flash memory, DRAM and printer (SoundVision). Designed an HDLC serial communications controller megacell, for use in microprocessor-based systems. HDLC is intended for fast serial bit transfer of digital data, similar to firewire and USP. Completed several gate array and standard cell design projects for an A/D and D/A process control system, from specifications to test vector generation. The resulting chips are used world-wide in process control hardware (Foxboro). Built a pioneering neural network robot arm controller that learns how to control motion from previous visual learning experience. The novel robotic prototype is a dramatic demonstration of a sensory-motor robot that can first learn and then perform with no knowledge of geometry or trigonometry in the controlling software. Also built a neural network visual character recognizer that operates with no need for pattern matching.

Other projects include: Design of industry standard ASIC IP (CRT controller, multiplier- accumulator, asynchronous communications device UART). ASIC design kits for IC vendors. JTAG testability. HART verification.

LinkedIn Profile
http://www.linkedin.com/in/jorgerubinstein/

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