Lab 5 DSP and FPGA Embedded Resources Signal Filtering and Display

Design and implement a digital circuit that calculates and shows the magnitude of a filtered signal. Your circuit must generate all control and data signals for producing the signal, filtering it, and displaying the magnitude on both the seven segment display and a display via the VGA output of the BASYS2 board. Please refer to the introductory lab slides for information about the signal and filtering. Use the clock frequency of 25 MHz generated by a DCM, and the resolution as close as possible to 640x480 pixels. This Lab can be done in teams or individually, but teams are required to finish more tasks. Task 1 (for individuals: required, 1 point; for teams: required, 0.75 points) Design a circuit that generates a sine wave (often called a Numerically Controlled Oscillator, or NCO.) The NCO output frequency is determined by six switches [5:0]. The NCO outputs the amplitude of a sine wave every 195 clocks. The sine wave frequency ranges from 0 to 63.1 kHz in ~1 kHz increments. When the switches are all in the 0 position, the frequency is 0 Hz. When the switches are all in the 1 position, the frequency is 63.1 kHz. Task 2 (for individuals: required, 2 points; for teams: required, 1.5 points) Design a circuit that performs a Finite Impulse Response (FIR) filter. The filter has 256 taps (supplied in a coefficient file.) Use the Coregen application to generate a 1024x18 dual port read-only-memory (ROM) that contains the coefficients using a Block RAM. This is called the Tap Buffer. The dual-output of the Tap Buffer is called the Taps. Implement a circular buffer by inferring a 256x18 dual-port distributed RAM to store the most recent 256 NCO outputs. This is called the Sample Buffer. The dual-output of the Sample Buffer is called the Samples. Using two multipliers (performed by instantiating the multiplier primitive), iterate through 128 pairs of products (where one product is[ Sample(i) * Tap(i)]) while storing the accumulated sum of the products. At the end of the 128 cycles, the final sum is output and the accumulator resets for the next iteration. When a new Sample is input to the Sample Buffer, the iterative process starts again.

Task 3 (for individuals: required, 1 point; for teams: required, 0.75 points) Design a circuit that calculates the magnitude of a signed input and scales it (using a generic). Use the Coregen application to generate a 1024x18 Block RAM. Implement a circular buffer with the core. The circular buffer is uses as a shift register to calculate the moving average of the most recent 1024 values. Task 4 (for individuals: required, 1 point; for teams: required, 0.75 points) Combine Task 1-3 into a top-level FPGA file. Display the moving-average result on the seven-segment display. Task 5 (for individuals: required, 1 point; for teams: required, 0.75 points) In Task 2, the supplied coefficient file and Coregen-erated Block RAM contains 4 distinct sets of filters, each 256 taps long, and each with a different frequency response. Expand Task 4 so that switches [7:6] selects one of the four sets of taps. When the switches are 00, the first 256 taps are used. When the switches are 01, the next 256 taps are used, etc. The first set of taps has a low-pass frequency response. Select several frequencies to verify the frequency response. Approximate the frequency response of the other three filter sets. For each of the four sets, sketch the frequency response (magnitude vs frequency.) Include the sketches in your report. Task 6 (for individuals: bonus, 1 point; for teams: required, 0.75 points) Expand Task 5 to display a bar on the screen that has a height proportional to the moving-average result. The magnitude needs to be scaled differently than Task 3. When the scaled-magnitude of the filter output is at the maximum theoretical value, the height of the bar is just below 480 pixels. When the scaled magnitude of the filter output is 0, the height is 0 pixels. The bar width is 10 pixels wide. The horizontal position of the bar is determined by switches [5:0]. When the switches are all 0, the bar spans from 0 to 9 pixels in the horizontal axis. When the switches are all 1, the bar spans from 630 to 639 pixels in the horizontal axis. Thus the bars horizontal position indicates the frequency of the NCO.

Task 7 (for individuals: bonus, 1 point; for teams: required, 0.75 points) Expand Task 6 to show one of three internal values on an oscilloscope using an 8-bit parallel digital-to-analog converter (DAC): NCO output, Filter output, or the magnitude output. Signed inputs must be converted to biased unsigned representation. Then they need to be scaled so that the full-scale range is within the 8-bit DAC range. Button[0] cycles through the three choices. When the NCO is selected, also turn on LED[0]. When the filter output is selected, also turn on LED[1]. When the magnitude output is selected, also turn on LED[2]. The DAC isnt supplied in the ECE448 kit; you must purchase it separately. To properly analyze the timing, all the used FPGA inputs must be registered before they are used by logic, and all outputs must be registered before leaving the FPGA.

For the all tasks, determine the following properties: 1. Number of CLB slices 2. Minimum clock period after synthesis [ns] 3. Maximum clock frequency after synthesis [MHz] 4. Minimum clock period after implementation [ns] 5. Maximum clock frequency after implementation [MHz] 6. Minimum latency after implementation [ns] As a part of the design process: 1. Draw an optimized block diagram of your NCO, filter, magnitude and scaling, bar fill, and DAC driver circuits. 2. Translate your block diagram (and the rest of the circuits) into RTL VHDL. 3. Write a separate testbench capable of verifying the functionality of the circuits. 4. Synthesize, implement, and load your design on the Basys board to verify functionality. In the lab report include: 1. Optimized block diagrams (hand-drawn hardcopy submitted in class and used during an exit quiz, and an electronic copy submitted using Blackboard in the pdf or MS Word format (preferably, the scanned version of the hand-drawn hardcopy.) 2. Electronic copy of the frequency response of each of the four filter sets. 3. VHDL source codes for: a. Sine wave generator (NCO) b. Filter c. Magnitude, scaling, and averaging d. Bar Fill e. DAC Driver f. VGA Sync generator g. Clock management unit h. Top Level Unit 4. User Constraint File (UCF) 5. Testbench and waveforms from the functional simulation (electronic versions submitted using Blackboard) for the last Task that you implement. The testbench should exercise most of the functionality of the design.

Monday Section Introduction to the Experiment Demonstration and Deliverables Due (Schedule A) Demonstration and Deliverables Due (Schedule B)** 04/04/2011 04/18/2011 05/02/2011

Tuesday Section 04/05/2011 04/19/2011 05/03/2011

Wednesday Section 04/06/2011 04/20/2011 05/04/2011

Thursday Section 04/07/2011 04/21/2011 05/05/2011