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06cs33
(08 Marks)
(08 Marks)
(04 Marks)
(05 Marks)
(05 Marks)
Third Semester B.E. Degree Examination, June/July 2013
Logic Design
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Time: 3 hrs.
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Max. Marks:1O0
Notez Answer FIYE
full
questions, selecting
atleast TWO questions
lfrom
each part.
PART_A
I a. Why NAND and NOR gates are universal gates? Simptifo the following Boolean
expression using k
-
map and implement the same using
i) NAND gates only (SOP form)
ii) NOR gates only
IPOS
form
)
.
F(A, B C,D)
-
>* (0;1, 2,4, s,12,14)
+
dc(8, 10). (r0 Marks)
b.
Find the prime implicants and essential prime implicants for the following Boolean
expression using
Quine
McClusky's method.
F(A,B,C,D):r',,(1,3,6,7,9,10,
12, 13, 14, 15). (l0Marks)
a. Realize the Boolean expression
l.
F(A, B, C, D): t'. = (2.3.4,5, 13. 15)
+
dc(8, 9, 10, 11) using 8 : I multiplexers and
external gates.
b.
Generate the Boolean expression for
...
a. Design a 2
-bit
carry look ahead adder and explain, with an eprnple. (10 Marks)
b. Draw the block diagram of4
-
bit adder/ subtractor circuit using full adder and explain the
Yo
:
A' B', yr
:
ABC, yz = dg, y:
:49'
C using PROM.
c. Write the HDL code for full adder.
same.
c. Compute the sum in each of the following :
i) 7s+38
ii) 8r6
+
Fr6.
a. What is a fliplfop? Explain the different types of flipflops
diagram, and excitation table.
b. Convert the SR flipflop into JK and D flipflops.
c. Write a note on edge trigged flipflps.
along with truth table, circuit
(10 Marks)
(06 Marks)
(04 Mrrks)
PART
_
B
5 a. What is a register? Explain the tlpes of register along with their applications.
b. Design a synckonous mod- 5 counter using JK flipflop.
c. What are presettable counters? Explain with an example.
(10 Marks)
(05 Marks)
(05 Marks)
1of 2
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06cs33
6 a. Differentiate Mealy and Moore models. (05 Marks)
b. Design an aslmchronous sequential logic circuit for the following state transition diagram.
I _
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$f-_
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r1g.
Qo(b)
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c. Draw the'sffi,trarsition diagram by row elimination method foy!*toilowinS :
dr:1
-
r' ,,i
'd
.t.
,lr
/o
dS
Fig'
Q6&[
-=." (roMarks)
a. Draw and exptqirFtd4-Uit binary ladder D/A converter. C.,:
(t0 Marks)
b. Discuss any twQ)Gthods of A,/D conversim.
'q{"
(r0 Marks)
*se
*'i;-.
a. Defure(lflTl parameters ii) Open
-
collector gate.
-, t
(05 Marks)
b. WhA{W CMOS characteristics? Explain.
l,
}
(05 Marks)
".
ffih"
aid of a circuit diagram, explain the operation of a 2
-
input Ttl,
$.gND
gate with
_*.p*op"n
-.ollector
method.
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2 of2
Fie.
Q6(b)
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