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FUZZY LOGIC

FUZZY CONTROLLED PHASE LOCKED LOOP

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PPTSWorld.blogspot.com ABSTRACT

Phased locked loop operates on the principle of feed back control, except that the feed back quantity is not the amplitude but the phase of the sinusoidal input signal. f the input sinusoid is noise, the P!! not only tracks the sinusoidal signal, but also cleans it up. The P!! can be used as an "# demodulator and frequency synthesi$er. The P!!, being a relati%ely inexpensi%e integrated circuit, has become one of the most frequently used communication circuit. P!! is also used in space&%ehicle&to&earth data links where there is a premium on transmitter Weight or where the loss along the transmission path is %ery large.

' classic P!! consists of a %oltage controlled oscillator ()*+,, a multiplier ser%ing as a phase detector (P-, and a low pass filter. The )*+ ad.usts its own frequency until it is equal to that of the input sinusoidal signal such that the frequency and phase of the two signals are in synchronism.

This paper deals with the some aspects of design and analysis of "u$$y *ontrolled P!!. t considers control of the loop gain by studying the phase %ariation between the two signals. The fu$$ification deals with triangular membership functions for phase angle of the input signal and the %oltage ) dc of the output signal. "u$$y interference is drawn using "&T/01 rules. -efu$$ification is carried out using height defu$$ification method. We report impro%ement in S12 and the lock in range frequency of a fu$$y controlled P!! as compared with that of classic P!!.

CONTENTS

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PPTSWorld.blogspot.com 1. INTRODUCTION TO PHASE LOCKED LOOP 2. DESIGN ASPECT OF CLASSIC PHASE LOCKED LOOP 3. POSSIBILITIES OF FUZZY CONTROL IN PLL 3.1 CONTROL OF THE LOOP GAIN 3.2 CONTROL OF THE PHASE DETECTOR 4. DESIGN ASPECTS OF THE FUZZY CONTROLLED PLL 5. STEPS INVALUED IN FUZZY CONTROLLED PHASE LOCKED LOOP 5.1 FUZZIFICATION 5.2 KNOWLEDGE REPRESENTATION 5.3 INFERENCE 5.4 DEFUZZIFICATION 6. FREQUENCY LOCKIN RANGE OF FCPLL . CALCULATING CRISP VALUE !. CONCLUSION

1.

INTRODUCTION TO PHASE LOCKED LOOP" n a feed back system, the signal fed back tends to follow the input signal, if

the signal feed back is not fed to the input signal, the difference will change signal feed back until it is close to the input signal. ' P!! operate on the same principle that the quantity feed back and compared is not the amplitude but the phase. )*+ ad.usts its own frequency until it is equal to that of input sinusoidal signal. 't this point the frequency and phase of the signal are in synchronism.

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PPTSWorld.blogspot.com P!! has emerged as one of the fundamental building block in electronics technology. The P!! principle is used in "# demodulators, frequency synthesi$ed transmitters and recei%ers, "S3 decoders for the generation of local oscillator frequency. "u$$y controlled phase locked loops are comparati%ely lower lock in range, higher signal to noise ratio. ' few applications of fu$$y controlled phase locked loops are4 5. "u$$y logic approach to direct phase control con%erter -* machine dri%e. 6. "u$$y control for output current phase controlled rectifier. 7. 'pplication of fu$$y logic in the phase locked speed control of induction motors. 8. -igital loop present synthesi$er (-!PS, for high&speed frequency switching. 9. -esign of a control system implementing fu$$y logic in programmable switching. The P!! consists of4 5. a phase detector, 6. a low pass filter, 7. a %oltage controlled oscillator. The phase detector compares the input frequency f in with the feedback frequency fout. The output of the phase detector is proportional to the phase difference between fin and fout. The output %oltage of a phase detector is -* %oltage () dc,, is often referred to as the error %oltage. The output of the phase detector is then applied to the low pass filter, which remo%es the high frequency noise and produces a dc le%el. This -* le%el, in turn is the input to the )*+. The !P" also helps in establishing the dynamic characteristics of the P!! circuit. The output frequency of the )*+ is directly proportional to input -* le%el. The )*+ frequency is compared with the input frequency and ad.usted until it is equal to the input frequency. n short the P!! works in three states4 free running, capture and phase lock. :efore input is applied the P!! is in free running state. +nce input is applied the )*+ frequency starts to change and P!! is said to be in the capture mode. The )*+ frequency continues to change until it is equal to the input frequency and phase locked

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PPTSWorld.blogspot.com state is obtained. When phase locked, the loop tracks any change in the input frequency through its repetiti%e action. n many applications the dynamic characteristics of P!! play an important role, mainly in the reduction of acquisition time and impro%ement in noise immunity. The time needed to reach the quasi&stationary regime, for a gi%en hop in frequency;phase is most usually determined in terms of equi%alent number of periods. These characteristics are important in "#;"S3 demodulator and in the fast switching frequency synthesi$ers that must often change the output frequency. n the last two decades, P!!s turned from the analog technology to -igital one, due to some important ad%antages like high frequency range, insensiti%ity to changes in temperature and power supply %oltage, programmable bandwidth and center frequencies. n the digital technology, %ery high loop gain is achie%ed, and higher order loops are easy to construct by simple cascading. Unlike in the analog P!!, Where the error signal pro%ided by the P- corrects the )*+ frequency, in digital P!! the error signal controls the direction of the up&down counter. ' class of integrated hybrid P!!s, including an analog )*+, an input signal amplifier and a low pass filter, are commercially a%ailable. 0x4 S0;10 9<= series, some digital P!! *s 8=8<, SP>>9=.-igital P!! *s using *#+S or TT! technologies are usually hybrid while the true digital P!!s are named ?all digital P!!s@.

fin

PHASE DETECTOR

!+W P'SS " !T02

)d
c

VOLTAGE CONTROLLED OSCILLATOR

#out

"eedback Path

2.

DESIGN ASPECT OF CLASSIC PHASE LOCKED LOOP"

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"or 10 9<9 P!! circuit 25A59kohms, *5A=.=5f,*6A5=f, *7A=.==5f, supply %oltageA9.B%, "requency range is 56k/$ to 5.96k/$.The lock&in& range (f !, and output frequency (fout, can be calculated as ( 825*5 ,. The frequency lock&in& range for classic P!! is 5.8=k/$.The output frequency of phase locked loop is 6k/$.These %alues are corresponds to the classic P!!. To obtain smaller %alues of f! larger %alues of fout with higher s;n ratio, we consider application of fu$$y logic controller to the classic P!!. f!A> fout ; %, foutA5.6 ;

3.

POSSIBILITIES OF FUZZY CONTROL IN PLL$4 :oth analog and digital P!!s can be controlled by fu$$y phase controller ("Ph*,.

#oreo%er the control may act at %arious stages of the loop, according to the typical applications. ' brief analysis of different ways of control is discussed as follows.

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PPTSWorld.blogspot.com 3.1 C%&'(%) %# '*+ )%%, -./&4 "or the analog P!!s, probably the simplest method to control the loop is that of changing the loop gain and thus input control %oltage to the )*+. This may be simply performed using an automatic gain control ('C*, amplifier in the loop. Such 'C* amplifiers can be implemented either by using a controlled resistance in the input or output attenuator or in the feed back loop of an amplifier. n case of second order analog P!!, the gain loop control, also has another ad%antage, namely it can speed&up loop acquisition time and also compensate for the change of static lock Din characteristics. ndeed it is well know that the lock& n characteristics of an analog P!! change with input frequency. t is relati%ely simple to achie%e the desired performance of the P!! at a fixed frequency by design, but the change of frequency causes the %ariation of certain internal parameters. Thus, the transient beha%ior of the loop as well as sideband noise is degraded. )arying either the phase detector characteristics, or the loop filter characteristics can alter the loop gain frequency characteristics. +n the other hand the loop filter characteristic is rather difficult to alter, as this operation requires switching of 2, and;or * components. Switching capacitors or resistors are undesirable since change in -* %oltage on the switched capacitors can introduce se%ere transient inputs into the P!!. n general, the 2 and * components of the filter are fixed %alue, components. 'lthough it is possible to use "0T as %ariable resistor, or acti%e filters to get a controlled filter, technological reasons limit the use of this alternati%e. ' reasonable control will pro%ide a high loop gain in the acquisition phase to achie%e fast acquisition and a constant gain %ersus frequency in the almost locked in situation to minimi$e the phase noise and to maximi$e spurious signal suppression. ' fu$$y control seems to perform this task. /ence this paper deals with the fu$$y control of an analog P!! (S0;10 9<9,.

3.2

FUZZY CONTROL OF THE PHASE CO0PARATOR"

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PPTSWorld.blogspot.com The use of a controlled phase comparator (Ph*, in an adapti%e P!! is a standard solution e%en in the crisp P!!. This can be easily extended to pro%ide a fu$$y control of the Ph*, thus turning the crisp loop into a fu$$y loop. n fact this possibility is used, in our first attempt, to demonstrate the feasibility of an all digital fu$$y control P!!.The ad%antage of the fu$$y control of the Ph* is the of ease of continuous control o%er the entire frequency range, while in most mplementations of crisp adapti%e P!!s, at least one range of control is discrete. 4. DESIGN ASPECTS OF THE FUZZY CONTROLLED PLL" The figure shows the fu$$y control is inserted between the phase detector and the low pass filter, based on the classical diagram of the P!! de%ice. )5 represents the first input in the fu$$y controller and stands for the phase error d (n, on the current moment (tAtn, and )6 represents the second input in the fu$$y controller and stands for the phase error d(n&5, the antecedent moment (tAtn&5,. The controller inputs are d(n&5,Ainput(n&5,&%co(n&6, d(n,Ainput(n&5,&%co(n&5, Where
input

is the input signal,%co is the )*+ signal and the symbols (n&5,, (n,

represents the %alues of the %ariables at successi%e moments. The fu$$y control is determined fi%e membership functions in antecedence on each of the inputs. The membership functions are sketched in fig. This number of input membership functions is a compromise between the quality of the control and dimension of 2ule base. "i%e triangular membership functions with equal bases o%erlapping, sketched in fig used as consequent (i.e. output,. The fu$$y controller yields a control %oltage ) %co applied to the )*+ input.

"u$$y #odule
V! FUZZIFICATION Rulebase INFERENCE Database LO PASS FILTER

f in
P/'S0 -0T0*T+2

V2

DEFUZZIFICATION PPTSWorld.blogspot.com Powered VOLTAGE by UandiStar.org CONTROLLED fout OSCILLATOR

Vdc

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Steps in%ol%ed in "u$$y control phase locked loop4 5. "u$$ification, 6. 3nowledge representation, 7. nferences,

8. -efu$$ification.

5.1

FUZZIFICATION"

The first step is the fu$$ification of input and output %ariables after carrying out experimental obser%ations. Phase difference (, is selected as input %ariable and the output, )dc is output %ariable. These two %ariables are fu$$ified o%er their practical domains as shown in fig. The fu$$y set ha%e been linguistically labeled as4 '2 (around,, E2AEero, )!A%ery low. !Alow, #!A#edium !ow, #/Amedium high /Ahigh.

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PPTSWorld.blogspot.com 5.2 KNOWLEDGE REPRESENTATION" The whole process of the phase locking is rule based on one hand and data based on other hand. Thus knowledge representation consists of rule base and database D.'.1.$+4 This module pro%ides information like domainsF membership functions for input parameters and %d. R2)+ B.$+4 The following rules ha%e been formulated to optimi$e the phase locking process. The membership functions were tuned to decide the weightage of each rule. 5.3 FUZZY INFERENCE" +urs is the single input single output (S &S+, System. Therefore #amadaniGs inference scheme is used. /ere contribution of each fu$$y rule is e%aluated to compute o%erall fu$$y decision outcome about output the dc %oltage. n the process of inference, each rule is indi%idually fired by crisp %alue of phase angle. This in turn generates clipped fu$$y sets (*"S,. These represent o%erall fu$$y output )dc. -atabase for and )dc nput data '2= (,A! (, =,89, '289 (,A' (, =,89,H=, '2H= (,A' (, 89,H=,579, '2579 (,A' (, H=,579,5>=, '2579 (,A(,579,5>=,. output data )!()dc,A!()dc,8.8,<.6, !()!dc,A'()ddc,8.9,<.6,>.56, #!()dc,A'()dc,<.6,>.56,5=.5>, #/()dc,A'()dc,>.56,5=.5>,56.=, /()dc,A()dc,5=.5>,566, 5.4 DEFUZZIFICATION Fu""# $f t%e& 'ules Rule !($f $s AR )*+, t%e& Vdc $s H Rule 2($f $s AR )-.+, t%e& Vdc $s /H Rule 0($f $s AR)1*+, t%e& Vdc /L Rule -($f $s AR)!0.+, t%e& Vdc $s L Rule .f $s AR)!2*+, t%e& Vdc $s VL

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PPTSWorld.blogspot.com This is last step in the implementation of output of "*P!!. This gi%es compromised decision regarding the dc %oltage. -efu$$ification con%erts o%erall fu$$y output of fu$$y inference into crisp %alue that corresponds to exact %alue of dc %oltage. Se%eral defu$$ification methods are a%ailable, howe%er, due to computational simplicity higher defu$$ification is used. The crisp %alue of dc %oltage commutated by following formula. )dcAqrA5(Pk(r, h(r,;h(r,, IAnumber of rules fired Pk(r,Apeak %alue of rth clipped fu$$y set /(r,Aheight of rth clipped fu$$y set

6.

FREQUENCY LOCK IN RANGE OF FUZZY CONTROLLED PLL"

Ste3 !4 -efine inputs and outputs for the "*&P!! The range of %alues that inputs and outputs may take is called the uni%erse of discourse. We need to define the uni%erse of discourse for all of the inputs and outputs of the "*& P!!, which are all crisp %alues. Ste3 24 fu$$y the inputs4 We are using triangular membership functions to fu$$y the inputs. There are some guidelines to be kept in mind, when we determine the range of the fu$$y %ariables as related to the crisp inputs. 5. Symmetrically distribute the fu$$fied across uni%erse of discourse. 6. Use an odd fu$$y sets for each %ariable so that some set is assured to be in the middle. The optimi$ation of these assignment of often done through trail and error for achie%ing the best performance of the "*P!!.

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PPTSWorld.blogspot.com Ste3 0( setup fu$$y membership function for outputs. Ste3 -4 create a fu$$y rule base4 These rules usually take the form "&T/01 rules of the fu$$y rule base firing at once, because the inputs ha%e been fu$$ified. We ha%e to arri%e at a single crisp output number. These are actually se%eral different strategies for this. We consider one of the most height defu$$ification method. . CALCULATING THE CRISP VALUE"

With "*P!!, frequency lock in range is as follows. "u$$y output with membership ( "&T/01, rules 5. )ery low 8.8% and low <.6%. 6. low <.6% and medium low >.56% 7. #edium low >.56% and medium high 5=.5>%. 8. #edium high 5=.5>% and high 56%. "irst we must determine for each of the '1- clause in the "&T/01 rules. 1. (8.8%,(<.6%,A8.8% 2. (<.6%,(>.56%,A<.6% 3. (>.56%,(5=.5>%,A>.56% 4. (5=.5>%,(56%,A5=.5>% :y using the fu$$y rule base, we ha%e the following inputs. We must combine the recommendation to arri%e at a single crisp %alue. (8.8,(<.6,(>.56,(5=.5>,(56,. /ere we use a dis.unction or maximum operator to combine the %alues. The crisp output %alue is 6J56%. Using this %alue of )dc the output frequency and lock in range can be calculated as follows "outA5.6;(825*5, A6k/$ PPTSWorld.blogspot.com Powered by UandiStar.org

PPTSWorld.blogspot.com f!A>fout;) A5.77k/$ "or the classic P!!, frequency lock in range is 5.8k/$Fwith "*P!! frequency lock in range is 5.77k/$.hence the lock in range is reduced by 5= %. "or classic P!! the signal to noise ratio is as follows4 S12A6= ( log)s ; )n , Where )s is %oltage of signal without noise, )n is the %oltage of signal with noise. /ere )sA5.H>%, )nA=.==5%. S12A6= ( log )s ; )n, A <9.H7d: "or "*P!!, )sA5.>9%, )nA5.B8). S12ABH.76d:. /ence impro%ement of S12 of the order of 57d: has been achie%ed.

CONCLUSION" The *haracteristics of P!! ( * 9<9, were studied in frequency range 5.6k/$& 5.96k/$ for classic P!!. The said P!! showed the lesser signal to noise ratio and larger lock&in&range. With introduction of "u$$y controller at appropriate signal to noise ratio

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PPTSWorld.blogspot.com impro%ed by 57d: and lock&in&range of frequency is reduced by 5=K. Thus, "u$$y logic P!! performs better than the said analog classic P!!.

REFERENCES4 5. Technical paper on "*P!! by '.:.3U!3'21 and S.)./'!S0 from Culbarga Uni%ersity. 6. +P&'mplifiers and !inear ntegrated *ircuits by 2.'.Cayakward. 7. 0lectronics Principles by #al%ino from Tata #cCraw /ill. 8. "u$$y !ogic with 0ngineering 'pplications by Timothy 2oss. IETE 'esea'c% 3a3e' o& Fu""# co&t'olled PLL b# S4R4SA ANT a&d R4R4/UDHOL5AR f'o6 S%$7a8$ U&$7e's$lt#4

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