EXPERIMENT No.

-1
Design six basic gates (AND, OR, NAND, NOR, XOR and XNOR) for 1 bit.
library IEEE; use IEEE.STD_LOGIC_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity gates is Port ( a : in STD_LOGIC; b : in STD_LOGIC; cand : out STD_LOGIC; cor : out STD_LOGIC; cxor : out STD_LOGIC; cnand : out STD_LOGIC; cnor : out STD_LOGIC; cxnor : out STD_LOGIC); end gates; architecture Behavioral of gates is

begin

cand <= a and b; cor <= a or b; cnand <= a nand b; cnor <= a nor b; cxor <= a xor b; cxnor <= a xnor b; end Behavioral;

Simulation Model:

EXPERIMENT No.-2
Design One Bit Half Adder using basic gates.

library IEEE; use IEEE.STD_LOGIC_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity halfadder is Port ( a : in STD_LOGIC; b : in STD_LOGIC; SUM : out STD_LOGIC; CARRY : out STD_LOGIC); end halfadder; architecture Behavioral of halfadder is begin SUM<= a xor b; CARRY<=a and b; end Behavioral;

Simulation Model:

EXPERIMENT No.-3
Design a Full Adder using basic gates for 1 bit operations.
library IEEE; use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity fulladder is Port ( a : in STD_LOGIC; b : in STD_LOGIC; cin : in STD_LOGIC; SUM : out STD_LOGIC; CARRY : out STD_LOGIC); end fulladder; architecture Behavioral of fulladder is

begin SUM<= a xor b xor cin; CARRY<=(a AND b) OR (a AND cin) OR (b AND cin);

end Behavioral;

Simulation Model:

EXPERIMENT No.-4
Design a half subtractor using logic gates. library IEEE; use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity halfsubtractor is Port ( a : in STD_LOGIC; b : in STD_LOGIC; DIF : out STD_LOGIC; BOR : out STD_LOGIC); end halfsubtractor;

architecture Behavioral of halfsubtractor is

begin DIF<=a xor b; BOR<= (not a) and b; end Behavioral;

Simulation Model:

EXPERIMENT No.-5
Design a full subtractor using logic gates. library IEEE; use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all;

entity fullsubtractor is Port ( a : in STD_LOGIC; b : in STD_LOGIC; BORROWin : in STD_LOGIC; DIF : out STD_LOGIC; BORROWout : out STD_LOGIC); end fullsubtractor;

architecture Behavioral of fullsubtractor is

begin DIF <= a XOR b XOR BORROWin; BORROWout <= ((NOT a)AND b)OR ((NOT a)AND BORROWin) OR (b AND BORROWin);

end Behavioral;

Simulation Model:

EXPERIMENT No.-6
Design a 3x8 decoder library IEEE; use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all;

entity decoder is Port ( input0: in STD_LOGIC; input1: in STD_LOGIC; input2: in STD_LOGIC; output0 : out STD_LOGIC; output1 : out STD_LOGIC; output2 : out STD_LOGIC; output3 : out STD_LOGIC; output4 : out STD_LOGIC; output5 : out STD_LOGIC; output6 : out STD_LOGIC; output7 : out STD_LOGIC); end decoder;

architecture Behavioral of decoder is begin output0 <= (not input2) and (not input1) and (not input0); output1 <= (not input2) and (not input1) and input0; output2 <= (not input2) and input1 and (not input0); output3 <= (not input2) and input1 and input0; output4 <= input2 and (not input1) and (not input0); output5 <= input2 and (not input1) and input0; output6 <= input2 and input1 and (not input0); output7 <= input2 and input1 and input0; end Behavioral;

Simulation model:

EXPERIMENT No.-7
Design a 8x1 Multiplexer library IEEE; use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity multiplexer is Port ( din0 : in STD_LOGIC; din1 : in STD_LOGIC; din2 : in STD_LOGIC; din3 : in STD_LOGIC; din4: in STD_LOGIC; din5 : in STD_LOGIC; din6 : in STD_LOGIC; din7 : in STD_LOGIC;

sel0 : in STD_LOGIC; sel1 : in STD_LOGIC; sel2 : in STD_LOGIC; dout : out STD_LOGIC);

end multiplexer;

architecture Behavioral of multiplexer is

begin

dout <= din0 when sel2='0' and sel1='0' and sel0='0' else din1 when sel2='0' and sel1='0' and sel0 ='1' else din2 when sel2='0' and sel1='1' and sel0='0' else din3 when sel2='0' and sel1='1' and sel0='1' else din4 when sel2='1' and sel1='0' and sel0='0' else din5 when sel2='1' and sel1='0' and sel0='1' else din6 when sel2='1' and sel1='1' and sel0='0' else din7 when sel2='1' and sel1='1' and sel0='1' ; end Behavioral; Simulation Model:

EXPERIMENT No.-8
Design a 1x8 Demultiplexer library IEEE; use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all;

entity demux is Port ( output0 : out STD_LOGIC; output1 : out STD_LOGIC; output2 : out STD_LOGIC; output3 : out STD_LOGIC; output4 : out STD_LOGIC; output5 : out STD_LOGIC; output6 : out STD_LOGIC; output7 : out STD_LOGIC; sel0 : in STD_LOGIC; sel1 : in STD_LOGIC; sel2 :in STD_LOGIC; input : in STD_LOGIC);

end demux;

architecture Behavioral of demux is

begin output0 <=input and(not sel2)and(not sel1)and(not sel0); output1 <=input and(not sel2)and(not sel1)and sel0; output2 <=input and (not sel2)and sel1 and(not sel0); output3 <=input and(not sel2)and sel1 and sel0; output4 <=input and sel2 and(not sel1)and(not sel0); output5 <=input and sel2 and(not sel1)and sel0; output6 <=input and sel2 and sel1 and(not sel0); output7 <=input and sel2 and sel1 and sel0; end Behavioral;

EXPERIMENT No.-9
Design a JK flip flop

library IEEE; use IEEE.STD_LOGIC_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity flipflops is Port ( J : in STD_LOGIC; K : in STD_LOGIC; Q : inout STD_LOGIC; QN : inout STD_LOGIC; CLK : in STD_LOGIC); end flipflops; architecture Behavioral of flipflops is begin process(CLK,J,K) begin if (CLK='1') then if(J='0' and K='0') then Q <=Q;

QN <=QN; elsif(J='0' and K='1') then Q <= '0'; QN <= '1'; elsif(J='1' and K='0') then Q <= '1'; QN <= '0'; elsif(J='1' and K='1') then Q <= NOT Q; QN <= NOT QN; end if; end if; end process; end Behavioral;

EXPERIMENT No.-10
Design a D flip flop

library IEEE; use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity Dfliflop is Port ( D : in STD_LOGIC; Q : inout STD_LOGIC; Qn : inout STD_LOGIC; CLK : in STD_LOGIC); end Dfliflop; architecture Behavioral of Dfliflop is begin process (D,CLK) begin if (CLK= '1') then Q <= D; QN <= NOT D; end if;

end process; end Behavioral ;

Simulation model: