Counter Design Exercises

Engr. J. S. Cansino

Exercises on Designing of Counter Circuits

Mod 4 Binary Up/Down Counter Example:
Design a circuit to build a Mod 4, two bit binary up/down counter. T e counter cycles !rom 0 1 ! 0 1... w en "#0 or: ! 1 0 ! ... w en "#1 T is circuit can be represented by t e "tate Transition Diagram in !ig. #.$ below.
Construct t$e State %ransition Diagra& for Counter Circuit

T e "T%TE" & binary number' are represented using ( !lip)!lops* eac !lip)!lop represents $ binary digit. T e !lip)!lops can remember what has happened in the past, or what value has been stored in them. T ere will be one external input+ , w ic controls t e direction o! t e count: U- !or ,./+ and D012 !or ,.$. T e state of the flip-flops, representing the 2-bit binary number &t e count' will be t e only circuit output. 1e could design t is circuit using 34+ D or T !lip)!lops+ but in t is example we5ll use D !lip)!lops. 1 en we are !inis ed t e circuit will loo6 somet ing li6e t is incomplete circuit:
lig ts "
DB Clc 7B5 7B

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Counter Design Exercises

Engr. J. S. Cansino

D% Clc

7% 7%5

c'oc(

0ur tas6 is to design t e circuit+ suc t at t e !lip !lop inputs will produce t e current )ext State outputs. T e design procedure we will !ollow !or t is problem will be: Design *rocedure+ $. 0btain t e "tate Table !rom t e problem statement o! !rom t e "tate Transition Diagram. (. Deri9e t e !lip)!lop input e:uations !rom t e next state conditions in t e state table. ;. Use 4)maps to simpli!y t e !lip)!lop input e:uations. 4. Draw t e logic diagram wit !lip)!lops and combinational gates as speci!ied by t e !lip)!lop input e:uations. 1e will illustrate t e solution using bot D !lip !lops and 34 !lip !lops. "tarting wit D !lip !lop solution.
*resent State ,nput )ext State -'ip -'op ,nputs

./

.0

"

./1

.01

D/

D0

Deri9e t e next)state e:uation using t e 4)mapping met od:

./.0 0 0 " 0 1 0 1 1 1 1 0

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Counter Design Exercises

Engr. J. S. Cansino

D%. ./.0 0 0 " 0 1 DB. 0 1 1 1 1 0

Draw t e logic diagram !or t is counter circuit:

lig ts "
DB Clc 7B5 7B

D% Clc

7% 7%5

c'oc(

Complete t e solution using 34 !lip !lops is s own on t e !ollowing page. *S )S J 2 input

*resent State ,nput )ext State -'ip -'op ,nputs

0 0
20

./

.0

" 0 1 0 1 0 1 0

./1

.01

J/

2/

J0

0 1 1 0 1 1 Complete t e 34 Excitation table 9alues to determine inputs to 34 !lip !lops+ w ic will cause correct transitions.
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0 0 0 0 1 1 1

0 0 1 1 0 0 1

Counter Design Exercises

Engr. J. S. Cansino

34 <=>- <=0- ?$ corresponds to most signi!icant bit o! t e ( bit binary number+ w ile !lip !lop ?( represents t e least signi!icant bit.

Deri9ing t e next)state e:uations using 4)mapping:

JK FLIP FLOP #1

./.0 0 0 .C" 0 0 0 1 1 1 1 0 3%.

0 1

1 1

1 0

./.0 .C" 0 0 0 1 1 1 1 0 4% .

0 0

0 1

1 1

1 0

JK FLIP FLOP #2

./.0 0 0 .C" 0 0 0 1 1 1 1 0 3B.

0 1

1 1

1 0

./.0 .C" 0 0 0 1 1 1 1 0 4B .

0 0

0 1

1 1

1 0

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Counter Design Exercises

Engr. J. S. Cansino

Draw t e logic diagram !or circuit implementation:

-roblem ?(: Design a circuit t$at cyc'e t$roug$ t$e nu&bers+ 1!43 1!4.... @our counter !or t e se:uence o! numbers s ould ad9ance up or down based on a control variable input. 1 en contro' 4ariab'e C#1, ad4ance forward+ w ile a control input o! C#0 s$ou'd cause a bac(ward &o4e in t e se:uence. %ssume t e se:uence wraps around at bot$ ends. <or example+ i! you a9e selected se:uence 1!43 and t e counter started up at $+ wit control input at one &C.$'+ se9en cloc6 pulses s ould cause t e !ollowing transitions: 1!43 1!4....
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Counter Design Exercises

Engr. J. S. Cansino

1. Draw t$e State %ransition Diagra&+

(. <ill in t e State %ab'e below+ !or your se:uence+ using t e completed 34 excitation 9alues in t e small table below.
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Counter Design Exercises

Engr. J. S. Cansino

*S )S J 2 input 0 0 0 1 1 0 1 1 <or now lea9e t e rows associated wit t e unused numbers empty !or now. =ater a!ter we !ill in t e 4)maps we will come bac6 and explore w at appens i! t e circuit e9er gets into one o! t ese states.
Present State
input

Next State

-'ip -'op ,nputs

./ 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

.0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1

.C 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1

E 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

1 /

.0

1 C

J/

2/

J0

20

JC

2C

5
0

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Counter Design Exercises

Engr. J. S. Cansino

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Counter Design Exercises

Engr. J. S. Cansino

JK FLIP FLOP #1

./.0 0 0 .CE 0 0 0 1 1 1 1 0 3%.

0 1

1 1

1 0

./.0 .CE 0 0 0 1 1 1 1 0 4% .

0 0

0 1

1 1

1 0

JK FLIP FLOP #2 ./.0 0 0 .CE 0 0 0 1 1 1 1 0 J0 # 0 1 1 1 1 0 ./.0 .CE 0 0 0 1 1 1 1 0 20 # JK FLIP FLOP #3 0 0 0 1 1 1 1 0

./.0 0 0 .CE 0 0 0 1 1 1 1 0 JC #

0 1

1 1

1 0

./.0 .CE 0 0 0 1 1 1 1 0 2C #

0 0

0 1

1 1

1 0

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Counter Design Exercises

Engr. J. S. Cansino

Circuit Diagram Control Input E________________________________________________________

J/

./ 88 ./

J0

.0 88

JC

.C 88 .C

2/

20

.0

2C

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