Analysis of the Impact on Amplication Due to Bypassing in an NPN Emitter Resistor Circuit

Sandesh Mohan Adhikary and Lab Partner: Anna Nuxoll

Department of Physics, Reed College, Portland, Oregon, 97202, USA (Dated: September 16, 2013) The impact of the bypassing capacitor in an amplier circuit constructed using a 2N2222 NPN transistor driven by a 10 kHz triangular waveform was analyzed by measuring gains with and without the capacitor connected. The measured gain of the bypassed emitter-resistor circuit of -286 13 was only 4.67 % dierent from the theoretical value of -300 whereas the measured gain of the unbypassed emitter resistor circuit of 15 0.5 was 100 % dierent from the theoretical value of -7.5. The bypassing was observed to have had a signicant impact on the gain, increasing it by 94.8 %. I. INTRODUCTION

The discovery of the transistor eect by John Bardeen and Walter Brattain at Bell Telephone Laboratories in 1947 [1] ushered a revolution in technological progress. Paving the way forward from the clunky and timeconsuming vaccum tubes, transistors enabled devices of extreme complexity to be developed on the minute real estate on Integrated Chips. Bardeen and Brattain were awarded the Nobel Prize in 1956 for their discovery of the transistor eect [2].A part of almost every piece of electronics present today, the transistor manages to provide a range of versatile uses even though its arsenal comprises mainly of only two techniques - switching and amplifying [3]. The switching capabilities of transistors have allowed them to be used in developing logic devices of immense complexity. However, the experiment described in this paper focuses on the amplication of input signals with the help of transistors. Transistors acheive amplication by allowing a small voltage (or current) to control the ow of a much larger current[3]. The current owing from the collector to the emitter is equal to the base current multiplied by a factor . The functioning of the transistor greatly depends on the biasing regime it operates on. In a forward biased base-emitter regime, the requirement that needs to be met is Vc > Vb > Ve (Fig. 1 ), where the subscripts refer to collector, base and emitter. In an amplier circuit, the biasing requirement is met through the right combination of biasing resistors. The DC power supply drives current IC through RC into the collector, out the emitter and then into the ground via Re . But even though the resistor combination is essential in creating the amplier circuit, the presence of the emitter resistor, Re actually counteracts the amplication. This resistor provides a negative feedback which, by increasing the value of Ve , minimizes Vbe , the dierence between Vb and Ve . Vbe represents the voltage that the transistor acknowledges as entering it and amplies the output accordingly. Therefore, the presence of Re , although important in the functioning of the amplier, also reduces the amplication. In order to solve this problem, a by passing capacitor (Cb ) can be connected in parallel to Re . The capacitor accomplishes

this because for a DC supply (the power supply for the transistor), the capacitor is basically an open circuit with innite resistance. But for an AC signal, the capacitor eectively makes the emitter an AC ground. This eect will be analyzed in greater detail in the later sections of this experiment in order to obtain a quantitative measurement of the improvement in gain due to the presence of this bypassing capacitor.

FIG. 1: Simple amplier circuit. Schematic of a basic amplier circuit

II.

EXPERIMENTAL DESIGN

An analog bypassed emitter resistor circuit was constructed on a breadboard as shown by the schematic diagram in Fig 2. A voltage source (VCC ) of 15 V was used to run the 2n2222 transistor. Firstly, relevant potential measurements from the circuit were compared to theoretical values to check if the circuit was, in fact, operating in the required biasing regime and was acting as an amplier. Secondly, the output signals (VOut ) were compared to the input signals (VIn ) with and without the presence of Cb in order to gauge the impact of Cb on the operation of the circuit, with special interest in measuring changes in voltage gains (the amplication factor). The circuit has been designed in order to ensure forward

2 biased emitter-base diode such that the voltage applied across the emitter-base junction needs to have the base at a positive potential about 0.6 V greater than that of the emitter (i.e VBE = 0.6). Furthermore, resistors R1 and R2 are chosen to ensure I2 > IB . Lastly, the amplitude of the input signal should be maintained such the output signal does not get clipped and thus compliance is maintained.

FIG. 3: The equivalent DC circuit. This is the quiescent circuit without any capacitors, the AC source turned into a short and with the DC model of an NPN transistor used to approximate the circuit of interest.

I2 + IB = I1 (At point j) IC = IE IB (At point k)

FIG. 2: Bypassed emitter resistor circuit. This in an amplier circuit which amplies Vin into Vout according to the value of Gain as determined by the resistances. Cb acts as the bypassing capacitor.

(1a) (1b)

The following Kircho Voltage Loop (KVL) equations describe the circuit presented in Fig. 3: I2 R2 + R1 (I2 + IB ) = VCC IE RE + VBE + (I2 + IB )R1 = VCC IE IB IB = (2a) (2b) (2c)

The potentials (in relation to ground) at the base (VB ), collector (VC ) and the emitter (VE ) are of special interest while analyzing the circuit. The strategy employed in theoretically obtaining these values was to analyze the DC equivalent of the circuit of interest at zeroth order and then rst order while using Kircho Voltage Loops (KVL) and the main computational tool. In order to obtain the DC equivalent of the circuit, it was rstly noted that with DC, , the frequency of the input signal, is zero and thus, owing to the inverse relationship between capacitor impedence and input signal frequency, the bypass capacitors essentially become open circuits and can be removed. Furthermore, the AC voltage source in the original circuit is turned into a short in the DC-equivalent circuit. Lastly, a DC model of the transistor is adopted where the transistor is replaced by a junction with a doide biased towards the direction of the emitter and placed at the Base-Emitter junction. These changes are shown in the DC-equivalent circuit in Fig. 3.

With the assumption that the , IB = 0, I2 IB and IE IB , IC = IE . Now, by solving Equations 2 (a-c) it is possible to obtain the following expression for IE : IE =
CC VCC ( RV )R1 VBE 1 +R2

RE

= IC

(3)

Since R1 and R2 form a voltage divider circuit, it is possible to derive the following expression for VB from the equations at hand: VB = VCC R2 R1 + R 2 (4)

With the expression for IC in Eq. 3, the following expression for VC can be derived: VC = VCC IC RC = VCC
CC )R1 VBE VCC ( RV 1 +R2

RE

RC

A.

Zeroth Order DC Circuit Analysis

By using conservation of charge, the following equations are readily deduced:

(5) With these expressions, it is possible to obtain VB , VC and VE . The results are tabulated in Table I. With these expressions from the zeroth order DC circuit analysis, it is possible to make the higher ordered rst order analysis.

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B. First Order DC Circuit Analysis

With the assumption that is nite (say 100), a relationship between IB and IE can be established : IB (1 + ) = IE (6)

Furthermore, from Equation (2b), it can be deduced that: I2 R1 + IB R1 + IE RE = VCC VBE (7)
FIG. 4: AC equivalent circuit. This circuit was obtained by removing capacitors and turning DC sources into shorts along with applying the AC model of the transistor - the dynamic resistance re

The task of nding all the required currents now involves solving the three simultaneous equations: 2a, 6 and 7. By substituting the relevant values of R1 (82K ), R2 (10K ), RE (1.0K ), VCC (15V ) and VBE (0.6V ), the matrix equation in Equation 8 was obtained. The value of VBE was theoretically deduced to be 0.6V since that is the baising requirement placed on the transistor. I2 92 K 82 K 0 15V IB = 82 K 82 K 1 K 14.4V (8) IE 0 101 K 1 K 0 The resultant values of VB , VE and VC , which were found using the values for currents and the expressions for the respective potentials at hand, are shown in Table I.
TABLE I: Required potentials for the zeroth and rst order results for DC and AC analysis of the bypassed emitter resistor circuit Quantity Zero order [DC] First order [DC VC V 7.27 7.97 VB V 1.63 1.55 VE = VB 0.6/, V V 1.03 0.95

Now, an expression for vin can be obtained: vin = vb = vs R1 ||R2 R1 R2 + r (10)

With vin already at hand, obtaining Vout will enable the calculation of the gain, the quantity of comparison between the bypassed and the non-bypassed emitterresistor circuit. It is known that: vout = ic Rc (11)

The computation of the gain will be dierent for the bypassed and the unbypassed circuits. These two scenarios are dealt with separately below:

1.

With the emitter resistor bypassed

With the bypassing capacitor present, the following expression can be obtained for ie :
C. Zeroth Order AC Analysis

ie = vs

R1 ||R2 1 ( ) R1 R2 + r re

(12)

Now, the AC zeroth order analysis is performed to obtained a higher order approximation of the emitterresistor circuit. Maintaining the assumptions that = ib = 0 = ic = ie , = ZC = 0 and that a DC source becomes a short in an equivalent AC circuit, a more complicated gure as shown in ?? is analyzed. The AC equivalent model of a transistor consists of a dynamic resistance (re ) between the base and c (mA) the emitter where re = i25mV . The following equations hold by Ohms Law and conservation of charge respectively: ie re = +is r = vs is = ib + i12 (9a) (9b)

Now, substituting the value of ie from Eq. 12 into Eq. 11, an expression can be derived for vout , which, in turn, yields the following expression for gain: G= ic (mA) Vout = Rc / Vin 25mV (13)

2.

With the emitter resistor not bypassed

Without the presence of the capacitor Cb , the gain can be easily computed as: RC RE + re

where i12 is the current in the ground wire leading to the parallel combination of R1 and R2

G=

(14)

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III. PROCEDURE TABLE III: Measurements of quiescent voltages of the collector, emitter and base of the bypassed emitter-resistor circuit Terminal Measured Voltage Average Predicted Voltage (V )V (V ) (V ) 0.02V 0.02V Trial 1a Trial 2 Trial 3 Collector 15.40 8.03 8.04 8.04 7.97 Base 1.68 1.62 1.62 1.62 1.55 Emitter 1.00 1.00 1.00 1.00 0.95
a A loose connection was noticed in the circuit after measuring VC and VB . Since the only certain measurement in Trial 1 (VC ) is exactly the same in all trials, the readings from Trial 1 were ignored while computing the averages.

The experiment was conducted in three parts. Firstly, The resistances used in the circuit were separately measured to ensure accurate measurements of gains. Secondly, the quiescnet potentials at the three transistor terminals were measured for comparison with theoretical value to ensure proper functioning of the amplier circuit. Finally, gains were measured separately with and without the bypassing capacitor Cb . As evidenced by equations 13 and 14, the resistances R1 , R2 , RC and RE play crucial roles in determining the gain of the circuit as well ensuring that the transistor is working within the correct biasing regime. Therefore, the exact values of these resistors were measured separately using a digital multimeter and are presented in Table II. Since the circuit consists of shunt paths that force the current to ow through alternate low-resistance paths, the resistances were measured separately and not while connected to the circuit. These values for the resistances will be used to obtain theoretical values of the gain for comparison.
TABLE II: Measured and theoretical resistances for all resistors involved in the analog circuit being analyzed Resistor Measured Resistance (k) 0.1k 81.6 9.98 7.39 1.00 Theoretical Resistance (k) 82.0 10.0 7.5 1.0

TABLE IV: VIn , VOut and Gain for the non-bypassed circuit Vin (mV ) 1V 50 45 40 60 Vout (V ) 0.1V 13.9 13.5 13.2 14.2 Gain

278 5.6 300 6.7 330 8.3 237 3.9

R1 R2 RC RE

Before the circuit was driven with an external voltage source, the quiescnet voltages at the collector (VC ), emitter (VE ) and the base (VB ) of the bypassed emitterresistor circuit were measured. These values were compared to theoretical values to ensure that the circuit was operating in the correct biasing regime. Table III presents the measured voltages along with predicted voltages. As the rst order DC analysis provides a better approximation of the circuit in general than the zeroth order, the values from the former analysis, rather than the latter, are used as predicted voltages in Table III. After ensuring that the circuit was operating as expected, it was driven with a triangular wave at 10 kHz with no DC oset. The input and output signals were both displayed on a digital oscilloscope to visually inspect dierences between the two, mainly amplitude and phase dierences. At suciently high input amplitudes, the output voltage gets clipped and does not provide accurate measurements while computing the gain since the output voltage is not allowed to reach its natural amplitude (no compliance). To ensure that all observations were being made in the unclipped regime, the amplitude was slowly in-

creased until the top and bottom parts of the output signal were seen to be conspicuosly atting out. As shown in Figure 5, the output signal was completely unclipped at input amplitude (peak to peak) of 50mV (a). At 60 mV (b), slight curving of the output signal was observed but it still remained unclipped. As the voltage was increased above 60mV, the straight lines forming the traingular wave were seen to become more curved along with the extremes of the curve completely attening out. At about 100mV (c), the signal was seen to be completely clipped and resembeled a sinusoidal signal with attened extremes. In order to ensure compliance, the maximum input amplitude applied to the circuit was 60 mV (peak to peak). Corresponding values of Vout were measured according to dierent values of Vin as shown in .Table IV for the bypassed circuit. The value of predicted gain (-300) was computed using Equation 13. Finally, the bypassing capacitor Cb was removed from the circuit and then values of Vout were measured for different values of Vin as shown in Table V. The value of predicted gain (-7.5) was computed using Equation 14.

IV.

DATA ANALYSIS

The values of measurements from Table III was compared with theoretical values to ensure that the circuit was functioning predictably and was within required compliance and biasing regimes. Furthermore, the mea-

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Voltage

(a)

Voltage

Time

(b)

Voltage

Time

(c)

the x-axis. Therefore, even though the values of measured gains have been quoted as positive, they should be understood to be negative to indicate the phase dierence between the input and output signals. The average value of gain obtained from the bypassed circuit (286 13.0) has a percentage dierence of 4.7 % from the predicted value of -300. Given the errors, it seems that the predicted value lies outside the error bars of the measured values. This might be the case because the error due to the noise in the signal has not been incorporated in the error estimates. On the other hand, the gain obtained from the unbypassed circuit (15 0.5) has a 100% dierence from the predicted value of (-7.5). This excessively large error is explained by the fact that the noise to signal ratio was much higher in the case of the unbypassed output signal due to the low amplication. Furthermore, since the values being measured were peak to peak voltages, the data was especially susceptible to errors due to noise. As is evident from comparing the value of gain from the bypassed circuit to that of the unbypassed circuit, the presence of Cb increases the gain by about 94.8 %.

Time

V.

CONCLUSION

FIG. 5: Vout and Vin plots with increasing input amplitude. The top curve in each of the plots represents the output while the bottom represents the input. Parts (a), (b) and (c) refer to input amplitudes (peak to peak) of 50 mV, 60 mV and 100 mV.

TABLE V: VIn , VOut and Gain for the non-bypassed circuit Vin (mV ) 1mV 50 40 Vout (mV ) 1mV 700 640 Gain

14 0.3 16 0.40

sured gains from Table IV and Table V were compared to respective theoretical values and especially with one another to analyze the impact of Cb on the gain of provided by the amplier circuit. The measured voltages as shown in Table III were found to be consistent with the predicted values with percentage discrepencies of 10%,0.62% and 2.9% for VC , VB and VE respectively. Thus, the bypassed emitterresistor amplier circuit produced voltage measurements as expected from an NPN amplier circuit. As seen in all three plots in Figure 5, the output signal is denitely amplied in comparison to the input signal. The shape of the output signals also match the prediction that gain should be negative. As can be seen in the gure, the output signals and the input signals have a phase dierence of i.e. the signals are reected along

A simple amplier circuit was built using a 2N222 NPN transistor with the main goal of analyzing the impact of the emitter bypassing capacitor. Furthermore, the quiescent circuit without a driving AC input signal was also analyzed in order to understand the signicance of the combination of resistors employed in an amplier circuit, specically the emitter resistor. The task of the emitter bypassing component is one that is extremely well suited for a capacitor. Since capacitors do not conduct DC voltages but are able to conduct AC voltages, the emitter bypassing capacitor is able to enable the bypass the negative feedback that would arise due to the presence of the emitter resistor while not bypassing the DC current that is required for the transistor to operate. The quiescnet circuit when analyzed without any AC input signal, operated as predicted by theory with discrepencies in the values of relevant potentials ranging from 0.62 to 10 %. This relatively low percentage errors exemplies the eciency of the emitter resistor bypassing capacitor. Though the function of the capacitor is to bypass AC currents form the emitter resistor, it would have been a futile device if it interrupted the ow of DC current, which is essential for the functioning of the transistor. It was noticed that the presence of the capacitor improves gain by about 94.8 % from about -7.5 to 286. This result not only highlights the usefulness of the technique of bypassing the emitter but also points out the limitations of the transistor when operated without the bypassing. If it were not for the technique of bypassing the emitter-resistor, the transistor may not

6 have found the wide appeal as an amplier that it enjoys today. New York, 2013) [2] J. Bardeen. Walter Houser Brattain 1902-1987: A Biographical Memoir (National Academy of Sciences, Washington D.C., 1994)
VI. BIBLIOGRAPHY

[1] J. Gertner. The Idea Factory: Bell Labs and the Great Age of American Innovation (Penguin Books,

[3] R. E. Simpson. Introductory Electronics for Scientists and Engineers (Allyn and Bacon Inc., Boston, 1974)