ARM Cortex-M3 Specifics

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ARM Cortex-M3 Specifics

ARM Specifics >

ARM Cortex-M3 Specifics

In order to get the most from the mikroC PRO for ARM compiler, the user should be familiar with certain aspects of ARM Cortex-M3 MCU. This knowledge is not essential, but it can provide a better understanding of the ARM's capabilities and limitations, and their impact on the code writing as well.

Types Efficiency
First of all, the user should know that ARM's ALU, which performs arithmetic operations, is optimized for working with 32-bit types. Also, it performs hardware multiplication and division on the integer level, so the floating multiplication and division is slower and consumes more memory comparing it to the integer. The ARM supports 64-bit data types, but they are less efficient. They provide higher precision, but lack the code size and the execution.

Nested Calls Limitations

There are no Nested Calls Limitations, except by RAM size. A Nested call represents a function call within the function body, either to itself (recursive calls) or to another function. Recursive calls, as a form of cross-calling, are supported by mikroC PRO for ARM, but they should be used very carefully. Also calling functions from interrupt is allowed. Calling function from both interrupt and main thread is allowed. Be careful because this programming technique may cause unpredictable results if common resources are used in both main and interrupt.

Variable, constant and routine alignment

Simple type variables whose size is 2 bytes are set to alignment 2, those whose size is 4 bytes and larger are set to alignment 4. Aggregated types are aligned according to the maximal alignment of its member. Routines are always set to alignment 4.

Bit-Banding
This bit-banding operation greatly simplifies bit manipulations. Instead of reading a word, ANDing in the appropriate bit, and then writing the word back out, bit-banding accomplishes this with a single store instruction. But that single instruction has another benefit: it is an atomic operation, executed as a single instruction.

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Example of Bit-Banding

Bit-banding uses address space that aliases peripheral or SRAM address space, allowing a single bit within a word to be manipulated by a reference to a byte at an aliased address. For example, a write to address 0x20000000 modifies the SRAM 32-bit word at that location, but writing to 0x28000000 modifies only bit 0 at address 0x20000000. With the prior method of bit manipulations with sequential instructions doing the read-modifywrite operations, an interrupt could occur which, potentially, could change a bit at that memory location. After the interrupt returns, the store could be writing corrupt data back to that memory location. The atomic nature of bit-band operations eliminates that problem.

Non-aligned Memory Access

ARM Cortex-M3 allows non-aligned memory access but at a performance loss. Each unaligned access causes multiple bus accesses which will cause slower performance.

Copyright (c) 2002-2013 mikroElektronika. All rights reserved. Want more examples and libraries? What do you think about this topic ? Send us feedback! Find them on

ARM Cortex-M4 Specifics

ARM Specifics >

ARM Cortex-M4 Specifics

In order to get the most from the mikroC PRO for ARM compiler, the user should be familiar with certain aspects of ARM Cortex-M4 MCU. This knowledge is not essential, but it can provide a better understanding of the ARM's capabilities and limitations, and their impact on the code writing as well.

Types Efficiency

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First of all, the user should know that ARM's ALU, which performs arithmetic operations, is optimized for working with 32-bit types. Also, it performs hardware multiplication and division on the integer level, so the floating multiplication and division is slower and consumes more memory comparing it to the integer. The ARM supports 64-bit data types, but they are less efficient. They provide higher precision, but lack the code size and the execution.

Nested Calls Limitations

There are no Nested Calls Limitations, except by RAM size. A Nested call represents a function call within the function body, either to itself (recursive calls) or to another function. Recursive calls, as a form of cross-calling, are supported by mikroC PRO for ARM, but they should be used very carefully. Also calling functions from interrupt is allowed. Calling function from both interrupt and main thread is allowed. Be careful because this programming technique may cause unpredictable results if common resources are used in both main and interrupt.

Variable, constant and routine alignment

Simple type variables whose size is 2 bytes are set to alignment 2, those whose size is 4 bytes and larger are set to alignment 4. Aggregated types are aligned according to the maximal alignment of its member. Routines are always set to alignment 4.

Bit-Banding
This bit-banding operation greatly simplifies bit manipulations. Instead of reading a word, ANDing in the appropriate bit, and then writing the word back out, bit-banding accomplishes this with a single store instruction. But that single instruction has another benefit: it is an atomic operation, executed as a single instruction.

Example of Bit-Banding

Bit-banding uses address space that aliases peripheral or SRAM address space, allowing a single

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bit within a word to be manipulated by a reference to a byte at an aliased address. For example, a write to address 0x20000000 modifies the SRAM 32-bit word at that location, but writing to 0x28000000 modifies only bit 0 at address 0x20000000. With the prior method of bit manipulations with sequential instructions doing the read-modifywrite operations, an interrupt could occur which, potentially, could change a bit at that memory location. After the interrupt returns, the store could be writing corrupt data back to that memory location. The atomic nature of bit-band operations eliminates that problem.

Non-aligned Memory Access

ARM Cortex-M4 allows non-aligned memory access but at a performance loss. Each unaligned access causes multiple bus accesses which will cause slower performance.

Floating-point Unit
The Floating-Point Unit (FPU) fully supports single-precision add, subtract, multiply, divide, multiply and accumulate, and square root operations. It also provides conversions between fixedpoint and floating-point data formats, and floating-point constant instructions. The FPU provides floating-point computation functionality that is compliant with the ANSI/IEEE Std 754-2008, IEEE Standard for Binary Floating-Point Arithmetic, referred to as the IEEE 754 standard. The FPU implements the FPv4-SP floating-point extension.

DSP Extensions
The Cortex-M4 core has digital signal processing capability in the form of DSP extensions, a single cycle MAC unit and a single precision floating point unit. The DSP extensions have following features :

Single cycle 16,32-bit MAC, Single cycle dual 16-bit MAC, 8,16-bit SIMD arithmetic, Hardware Divide (2-12 Cycles).

Copyright (c) 2002-2013 mikroElektronika. All rights reserved. Want more examples and libraries? What do you think about this topic ? Send us feedback! Find them on

Stellaris Specifics
ARM Specifics >

Stellaris Family Specifics

The Stellaris family of microcontrollers are the first ARM Cortex-M3 based microcontrollers, and feature :

Up to 80 MHz operation with 32-bit ARM Cortex-M3 architecture, 8K to 256K Single-cycle Flash, 8K to 64K Single-cycle SRAM, Flexible Timer Capability, Up to 4 general purpose timer, 24-bit system (SysTick) timer,

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32-bit watchdog timer, Several serial interfaces, LDO voltage regulator.

When using Stellaris family, user should be aware of the following :

Locking pins, Start-up, and Advanced Peripheral Bus and Advanced High-Performance Bus.

Locking pins
All MCUs, except x00 family, provide a layer of protection against accidental programming of critical hardware peripherals. Protection is currently provided for the NMI pin (PB7) and the four JTAG/SWD pins (PC[3:0]). Therefore these pins need to be unlocked before their function can be changed. Refer to GPIO Library for GPIO handling routines. Caution : It is possible to create a software sequence that prevents the debugger from connecting to the Stellaris microcontroller. If the program code loaded into flash immediately changes the JTAG pins to their GPIO functionality, the debugger may not have enough time to connect and halt the controller before the JTAG pin functionality switches. As a result, the debugger may be locked out of the part. This issue can be avoided with a software routine that restores JTAG functionality based on an external or software trigger. Or, if possible, by simply adding few seconds delay at the beginning of your code.

Start-up
Upon reset, MCU will execute Start-up sequence in order to configure the oscillator block. Start-up sequence will configure Reset and Clock Control registers (RCC and RCC2) using the settings given in the Edit Project window.

Advanced Peripheral Bus and Advanced High-Performance Bus

Advanced Peripheral Bus (APB) interfaces to any peripherals that are low-bandwidth and do not require the high performance of a pipelined bus interface; the APB has unpipelined protocol. All signal transitions are only related to the rising edge of the clock to enable the integration of APB peripherals easily into any design flow. Every transfer takes at least two cycles. APB is designed for low bandwidth control accesses, for example register interfaces on system peripherals and is optimized for minimal power consumption and reduced interface complexity. APB bus has an address and data phase similar to AHB, but a much reduced low complexity signal list, for example no bursts. The Advanced High-Performance (AHB) is a new level of bus which sits above the APB and implements the features required for high-performance, including:

burst transfers, split transactions, single cycle bus master handover, single clock edge operation, non-tristate implementation, wider data bus configurations (64/128 bits).

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Copyright (c) 2002-2013 mikroElektronika. All rights reserved. Want more examples and libraries? What do you think about this topic ? Send us feedback! Find them on

STM32 Specifics
ARM Specifics >

STM32 Family Specifics

This topic discusses basic STM32 family specifics.

STM32 F4 Specifics STM32 F2 Specifics STM32 F1 Specifics Start-up Advanced Peripheral Bus and Advanced High-Performance Bus

STM32 F4 Specifics
The STM32 F4-series is the first group of STM32 microcontrollers based on the ARM Cortex-M4F core. The main features for this series are :

ARM Cortex-M4F core at a maximum clock rate of 168 MHz. The Flash memory has the following main features :

Capacity up to 1 Mbyte 128 bits wide data read Byte, half-word, word and double word write Sector and mass erase

Prefetch instruction and cache memory, Embedded SRAM feature 4 Kbytes of backup plus 192 Kbytes of system SRAM. The system SRAM can be accessed as bytes, half-words (16 bits) or full words (32 bits). Oscillators consists of internal (16 MHz, 32 kHz), optional external (4 to 26 MHz, 32.768 to 1000 kHz). Common peripherals included are :

USB 2.0 OTG HS and FS, Two CAN 2.0B, One SPI + two SPI or full-duplex I2S, Three I2C, Four USART, Two UART, SDIO for SD/MMC cards, Twelve 16-bit timers, Two 32-bit timers, Two watchdog timers, Temperature sensor, 16 or 24 channels into three ADCs, Two DACs, 51 to 140 GPIOs, Improved real-time clock (RTC), Cyclic redundancy check (CRC) engine, Random number generator (RNG) engine.

The STM32F4x7 models add ethernet MAC and camera interface.

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The STM32F41x models add a cryptographic processor for DES / TDES / AES, and a hash processor for SHA-1 and MD5.

STM32 F2 Specifics
The STM32 F4-series are the STM32 microcontrollers based on the ARM Cortex-M3 core. The main features for this series are :

ARM Cortex-M4F core at a maximum clock rate of 120 MHz. The Flash memory has the following main features :

Capacity up to 1 Mbyte 128 bits wide data read Byte, half-word, word and double word write Sector and mass erase

Prefetch instruction and cache memory, Embedded SRAM feature 4 Kbytes of backup plus 192 Kbytes of system SRAM. The system SRAM can be accessed as bytes, half-words (16 bits) or full words (32 bits). Oscillators consists of internal (16 MHz, 32 kHz), optional external (4 to 26 MHz, 32.768 to 1000 kHz). Common peripherals included are :

USB 2.0 OTG HS, Two CAN 2.0B, One SPI + two SPI or I2S, Three I2C, Four USART, Two UART, SDIO for SD/MMC cards, Twelve 16-bit timers, Two 32-bit timers, Two watchdog timers, Temperature sensor, 16 or 24 channels into three ADCs, Two DACs, 51 to 140 GPIOs, Improved real-time clock (RTC), Cyclic redundancy check (CRC) engine, Random number generator (RNG) engine.

The STM32F2x7 models add ethernet MAC and camera interface. The STM32F21x models add a cryptographic processor for DES / TDES / AES, and a hash processor for SHA-1 and MD5.

STM32 F1 Specifics
The STM32 F1-series are the group of STM32 microcontrollers based on the ARM Cortex-M3 core. The main features for this series are :

ARM Cortex-M3 core at a clock rate up to 72 MHz. The Flash memory for XL-density devices has density of up to 1 Mbyte, for other devices density of up to 512 Kbytes. The Flash memory can be programmed 16 bits (half words) at a time. Embedded SRAM feature up to 96 Kbytes of static SRAM. It can be accessed as bytes, half-words (16 bits) or full words (32 bits). Oscillators consists of internal (16 MHz, 32 kHz), optional external (4 to 26 MHz, 32.768 to 1000 kHz). Common peripherals included are :

USB 2.0 OTG HS, One CAN 2.0B,

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Up to three SPI, Up to two I2C, Up to five USART, Two UART, SDIO for SD/MMC cards, Up to fourteen 16-bit timers, Two 24-bit timers, Two watchdog timers, Up to 21 ADC channels, Two 12-bit DACs, Real-time clock (RTC).

The STM32F2x7 models add ethernet MAC and camera interface. The STM32F21x models add a cryptographic processor for DES / TDES / AES, and a hash processor for SHA-1 and MD5.

Start-up
Upon reset, MCU will execute Start-up sequence in order to configure the oscillator block. Start-up sequence will configure Reset and Clock Control registers (RCC and RCC2) using the settings given in the Edit Project window.

Advanced Peripheral Bus and Advanced High-Performance Bus

Advanced Peripheral Bus (APB) interfaces to any peripherals that are low-bandwidth and do not require the high performance of a pipelined bus interface; the APB has unpipelined protocol. All signal transitions are only related to the rising edge of the clock to enable the integration of APB peripherals easily into any design flow. Every transfer takes at least two cycles. APB is designed for low bandwidth control accesses, for example register interfaces on system peripherals and is optimized for minimal power consumption and reduced interface complexity. APB bus has an address and data phase similar to AHB, but a much reduced low complexity signal list, for example no bursts. The Advanced High-Performance (AHB) is a new level of bus which sits above the APB and implements the features required for high-performance, including:

burst transfers, split transactions, single cycle bus master handover, single clock edge operation, non-tristate implementation, wider data bus configurations (64/128 bits).

Copyright (c) 2002-2013 mikroElektronika. All rights reserved. Want more examples and libraries? What do you think about this topic ? Send us feedback! Find them on

ARM Cortex-M3 and Cortex-M4 Memory Organization

ARM Specifics >

ARM Memory Organization

The Cortex-M3 and Cortex-M4 have a predefined memory map. This allows the built-in peripherals, such as the interrupt controller and the debug components, to be accessed by simple

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memory access instructions. Thus, most system features are accessible in program code. The predefined memory map also allows the Cortex-M3 processor to be highly optimized for speed and ease of integration in system-on-a-chip (SoC) designs. Overall, the 4 GB memory space can be divided into ranges as shown in picture below. The Cortex-M3 design has an internal bus infrastructure optimized for this memory usage. A graphical representation of the ARM memory is shown in picture below :

ARM Memory Map

The ARM Cortex-M3 memory is divided into following regions :

System - . Private Peripheral Bus - External - Provides access to :

the Trace Port Interface Unit (TPIU), the Embedded Trace Macrocell (ETM), the ROM table, implementation-specific areas of the PPB memory map. the Instrumentation Trace Macrocell (ITM), the Data Watchpoint and Trace (DWT),

Private Peripheral Bus - External - Provides access to :

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the Flashpatch and Breakpoint (FPB), the System Control Space (SCS), including the MPU and the Nested Vectored Interrupt Controller (NVIC).

External Device - This region is used for external device memory. External RAM - This region is used for data. Peripheral - This region includes bit band and bit band alias areas.

Peripheral Bit-band alias - Direct accesses to this memory range behave as peripheral memory accesses, but this region is also bit addressable through bit-band alias. Peripheral bit-band region - Data accesses to this region are remapped to bit band region. A write operation is performed as read-modify-write.

SRAM - This executable region is for data storage. Code can also be stored here. This region includes bit band and bit band alias areas.

SRAM Bit-band alias - Direct accesses to this memory range behave as SRAM memory accesses, but this region is also bit addressable through bit-band alias. SRAM bit-band region - Data accesses to this region are remapped to bit band region. A write operation is performed as read-modify-write.

Code - This executable region is for program code. Data can also be stored here.

Related topics: ARM Cortex-M3 Specifics, ARM Cortex-M4 Specifics, Stellaris Specifics, Memory type specifiers

Copyright (c) 2002-2013 mikroElektronika. All rights reserved. Want more examples and libraries? What do you think about this topic ? Send us feedback! Find them on

ARM Memory Type Specifiers

ARM Specifics >

Memory Type Specifiers

The mikroC PRO for ARM supports usage of all memory areas. Each variable may be explicitly assigned to a specific memory space by including a memory type specifier in the declaration, or implicitly assigned. The following memory type specifiers can be used:

code data rx (reserved for compiler purposes only) sfr ccm

code
Description The code memory type may be used for allocating constants in program memory.

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Example

// puts txt in program memory const code char txt[] = "ENTER PARAMETER:";

data
Description Example This memory specifier is used when storing variable to the Data RAM.
// puts x in data ram data unsigned char x;

rx
Description Example This memory specifier allows variable to be stored in the working registers space (reserved for compiler purposes only).
// puts y in working register space rx char y;

sfr
Description This memory specifier allows user to access special function registers. It also instructs compiler to maintain same identifier name in source and assembly. Note : Variables can only be allocated in sfr space by the means of absolute directive or at directive to a variable already allocated in sfr space. Example
// Extern y in sfr space extern char y; sfr; // Puts y in sfr space by absolute (sfr addresses are MCU specific) char y absolute 0x40004000; sfr; // Puts y in sfr space by at char y at GPIO_PORTA;

ccm
Description This memory specifier allows user to allocate variables in the Core Coupled Memory (CCM). It is available only for the MCUs that possess this type of memory (currently, only the STM32 Cortex M4 family).
// Put variable y in CCM space : ccm char y;

Example

Note : If none of the memory specifiers are used when declaring a variable, data specifier

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will be set as default by the compiler.

Related topics: ARM Memory Organization, Accessing individual bits, SFRs, Constants, Functions

Copyright (c) 2002-2013 mikroElektronika. All rights reserved. Want more examples and libraries? What do you think about this topic ? Send us feedback! Find them on

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