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An Eighth-Order CMOS Low-Pass Filter with 30120 MHz Tuning Range and Programmable Boost
Giacomino Bollati, Stefano Marchese, Marco Demicheli, and Rinaldo Castello, Fellow, IEEE
AbstractA CMOS low-pass filter with programmable boost is type with the value presented. The architecture is a controlled through a resistor servo approach. The transfer function has been optimized in order to reduce the sensitivity to component parameter variations. The 1:4 tuning range is achieved by exploiting a dual-loop control over a degenerated differential pair. At the nominal output voltage swing of 200 mVpp differential, a THD better than 40 dB is guaranteed. The high-frequency boost is programmable between 6 and 14 dB. This filter, realized as a cascade of biquad and first-order cells, is implemented in a 0.25- m 2.5-V CMOS technology. It dissipates 120 mW with = 120 MHz and has a die area of 0.23 mm2 . Index TermsCOMS filters, HDD equalization, linear phase filters, programmable boost, tuning circuits.

Some of the most popular transconductors are discussed in Section III, while in Section IV, we present a technique used to control a well-known transconductor, the degenerated differential pair, in order to achieve a better tradeoff between programmability, offset, dynamic range, and power dissipation. Some design details of the eighth-order filter implemented in a 0.25- m CMOS technology are discussed in Section V. Experimental results are presented in Section VI, and conclusions are given in Section VII. II. FILTER ARCHITECTURE The filter presented in this paper is integrated within R/W channels whose digital portions are becoming bigger and faster requiring the filter to have high immunity from on-chip interference (switching noise). For this reason and to maximize dynamic range, the size of the integrated capacitors and the voltage swing must be kept as large as possible, with the constraint of having a limited power dissipation. Both the transfer function and the filter structure have been chosen to keep the same voltage swing at each node. In particular, boost control is implemented in such a way to minimize the in-band gain dependence on the programmed boost. The filter is realized as a cascade of first- and second-order structures with the high-frequency boost provided by two real axis zeroes. Such an architecture, compared with a ladder-type topology, has a worse amplitude response accuracy but better phase response accuracy (as required in this application). The absolute frequency value is controlled with a single precise external resistor. For a fixed value of this resistor, the cutoff frequency is programmable in a 1:3 range. It is possible to use the same filter on different families of HDD using different external resistors: the overall frequency range for a master covered is 1:4. A dc loop sets the desired transconductor while all the other transconductors used in the filter are biased as replicas of this master. Closed loop operation ensures stability over process, temperature, and supply voltage variations. A one-time trim, performed at wafer sort, is used to compensate the deviation of the cutoff frequency from the nominal value due to capacitor spread (over process) and to circuit. The accuracy the random offset in the reference s and of the frequency response shape is guaranteed by the capacitor matching. A. Transfer Function Choice Seventh-order phase equiripple continuous time filters are widely used for hard disk drive read channels [1], [3], [6], [8]. Our approach uses an higher order filter to fit the same mask

I. INTRODUCTION EAD/WRITE (R/W) channels for hard disk drives (HDD) require high-frequency continuous time filters (CTF) with a wide frequency tuning range. On the other hand, linearity and dynamic range need not be very high (typically 40 dB for both parameters). To achieve very high speed, simple circuits are more suitable, - type and for this reason, the most popular solution is the due to its open-loop structure. The filter presented in this paper implements an eighth-order transfer function as a cascade of biquad and first-order cells. The poles constellation has been optimized to satisfy the mask requirements of the standard seventh-order 0.05 equiripple linear phase filter generally used for this application while using less selective cells. The transfer function choice and the circuit architecture used to implement the boost function will be described in Section II. Programmable high-frequency filters for R/W channels can be easily implemented in BiCMOS technology taking advantage of the very wide tunability of bipolar transconductors [1][4], [11]. The design of the same filters in CMOS technology is, however, much more challenging due to the difficulprogrammable over ties of designing transconductors with a a wide range [5][10]. A multirange approach is often preferred to a continuous tuning one in the most advanced implementation of these filters [8][10]. Such a solution has also been adopted in this design.
Manuscript received November 17, 2000; revised January 22, 2001. G. Bollati and S. Marchese are with STMicroelectronics, 20010 Cornaredo, Italy. M. Demicheli was with STMicroelectronics, 20010 Cornaredo, Italy. He is now with Maxim Integrated Products, 20089 Rozzano, Italy. R. Castello is with the Department of Electronics, University of Pavia, Pavia, Italy. Publisher Item Identifier S 0018-9200(01)04514-0.

00189200/01$10.00 2001 IEEE

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(a)

Fig. 3.

Classical boost implementation.

(b) Fig. 1. Group-delay in the ideal case and with a 10% error in the of the most selective biquad. (a) Seventh-order equiripple. (b) Implemented eighth order.

Fig. 4. Derivative circuit.

value of the most selective cell. It is possible to see the reduced sensitivity of the eighth-order structure.
Fig. 2. Biquad block diagram.

B. Filter Structure A critical design aspect of filters performing the equalization function is the boost capability. Boosting is done to shape the spectrum of the received signal according to the desired class of equalization (E PR4 in the case reported here) of a PRML read channel. This feature is typically realized through two opposite real axis zeroes, in this way it is possible to modify the amplitude frequency response without changing the group-delay response. The numerator of the transfer function must therefore contain the following term:

requirements with the purpose of reducing the sensitivity of the amplitude and phase response to implementation inaccuracies (random mismatch and parasitics not accurately evaluated). Such a solution allows a greater freedom in the poles placement. The transfer function implemented (derived from an eighth-order equiripple filter) is made up of three biquad and two first-order cells. Through a numeric optimization, the and pole frequencies of the spreads of both quality factor various cells have been minimized. In particular, the highest is 1.5 (instead of 2 in the seventh-order equiripple). In fact, high-selectivity cells are undesirable for two main reasons. First, the higher the , the higher is the sensitivity of the and deviation from cell to implementation inaccuracy ( nominal value due to random mismatch). Second, for a given precision of the elementary cells making up the filter, the overall frequency response is more sensitive to the higher selective cells inaccuracy. In Fig. 1, group-delay plots of ideal version of the standard seventh-order filter [Fig. 1(a)] and of the chosen eighth-order one [Fig. 1(b)] are compared to nonideal implementations having, for instance, a 10% error in the

Several topologies have been proposed to realize these symmetric zeroes. Many of them make use of additional circuits (amplifiers, derivators, etc.) that require a large amount of power to keep the parasitic poles out of the band of interest. For instance, in the circuit shown in Fig. 3, the zeroes are realized by injecting a current proportional to the derivative of the voltage at the input of a biquad cell (shown in Fig. 2) directly into the output node of the cell. But, every circuit realizing a derivative function contains at least one parasitic pole: the implementation

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Fig. 5. Third-order cell block diagram.

Fig. 6.

Overall filter block diagram.

represented in Fig. 4, assuming an ideal transconductor, has the following transfer function: (1) To use this circuit in the scheme of Fig. 3, the extra pole must be kept at a frequency much higher then the filter cutoff frevalue with a consequently quency. This requires a very high high power consumption. One target of the present work has been to develop a structure with low sensitivity to process and environmental spreads having the constraint of a limited power budget. The solution adopted can be used for filters having at least two real axis poles (this has been a further constraint on the transfer function optimization). If the circuit of Fig. 4 is used in the scheme of Fig. 5, the resulting third-order structure has the following transfer function:

quency much higher than the filter cutoff frequency. This results in a less sensitive design and in a power saving. Further power and area saving is obtained since the boost function is realized using only the cells required for implementing the low-pass function. This is not the case with the classical methods which usually require additional circuitry to generate the boost function. The two required zeroes are obtained using two of these cells. The symmetry in the zero position with respect to the imaginary axes is obtained injecting the currents with opposite sign in the two cells. This can be easily done in a differential configuration crossing paths (the complete filter block diagram is shown in Fig. 6). C. Boost Programmability For the intended application, the boost range required is quite large (i.e., from 6 to 14 dB). Traditionally, while boosting, the dc gain is kept constant and the peak value of the frequency response is varied acting on the high-pass term [1][3], [5], [6]. This implies a big variation of the filter gain close to the cutoff frequency (where most of the read signal power is located). Fig. 7(a) shows the amplitude frequency response with boost equal to 6 dB and 14 dB in the classical implementation. Our solution performs boost control programming the value of the first transconductor (i.e., the dc gain of the cell) of the two third-order structures and of the first biquad. In this way, a small dependence of the peak filter gain on the boost value is

(2) The pole associated with the stage generating the derivative is, in this case, used as a pole of the transfer funccurrent tion: in this way such a pole does not need to be moved to a fre-

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(a) Fig. 7.

(b)

Amplitude frequency response at 6 dB and 14 dB of boost in (a) standard implementation and (b) in our filter.

obtained, as shown in Fig. 7(b) [for the same boost values of Fig. 7(a)]. As a consequence, the filter gain in the frequency of interest, where most of the signal energy is located, stays fairly constant for different boost values. This produces a similar voltage swing at all internal nodes independent of the boost value. Also, the output noise spectrum is only slightly dependent on the boost, as shown in Fig. 8. The end result is a dynamic range almost independent of the boost value much different than in classical implementations. III. BASIC DIFFERENTIAL TRANSCONDUCTORS The cutoff frequency of analog CTFs can be programmed time constants. This control can be controlling the value while keeping the capaciachieved by varying the tance values fixed, or vice versa. In the former, the dynamic range is not dependent on the cutoff frequency value. For this reason, several CMOS transconductors with a programmable value have been developed. The tuning range achievable is usually not wide enough, so multirange architectures are often used. The simplest transconductor is the differential pair shown in Fig. 9(a). It has many merits, but its tunability is quite poor in value can be approximated as low voltage technologies. The (3) (4) Equation (3) shows that it is possible to control the transconductance value through the tail current. On the other hand, and the voltage (4) shows the proportionality between determine the achievable overdrive. The allowed values of is related to the limited tuning range. The upper limit of voltage supply (shared between loads, transconductor, and

Fig. 8. Filter output noise spectrum at the extreme cutoff frequency and boost values (for the same frequency the noise is lower at higher boost).

tail current generator). The lower limit of depends on the amount of distortion allowable in the application. Process and environmental spreads heavily reduce the available tuning range. Moreover, for power efficiency reasons, it is better to . In fact, while the grows limit the highest value of , the current grows proportionally to . proportionally to An alternative solution that increases the linear range at low overdrive voltages has been preferred in this work. The transconductor proposed is an evolution of the classical degenerated differential pair shown in Fig. 9(b).

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(a)

This transconductor also has other problems. The gate overdrive of M3 (and consequently the value) is directly dependent on the accuracy of the common-mode output voltage of the previous transconductor and therefore on the gain (and bandwidth) of the common-mode feedback loop. Finally, the high-frequency behavior is altered by the phase shifts due to the internal nodes and its input impedance is not purely capacitive. The key advantages of this transconductor (i.e., large linear range and tunability) are therefore counterbalanced by many serious disadvantages that make it unsuitable for very high-frequency filters. However, many of these disadvantages become is small. smaller if Let us finally compare these two transconductors considering some important figures of merit: power efficiency (PE) (exratio) and total harmonic distortion (THD) pressed by the (considering only the dominant effect of the third harmonic). : In the nondegenerated case (7) (8) where is the input signal peak amplitude (differential), while for a degenerated differential pair working with the same input the expressions are, to the first order, the following: signal

(b) Fig. 9. pair. (a) Nondegenerated differential pair and (b) degenerated differential

(9) (10)

The differential pair formed by M1M2 is degenerated by an NMOS transistor operating in the triode region (M3). If we the triode MOS resistance and the differential pair call can be, to the first order, aptransconductance, the overall proximated as (5) where is expressed as in (3) and (4) and

, THD With degeneration, for the same voltage overdrive , but the power efficiency is reduced improves by , while, for the same distortion, the lowest by can be reduced by , allowing a tuning range extension. In the following section, we will show the improvement introduced in the tuning strategy of the degenerated differential pair in order to overcome the main limitations of this structure. IV. DUAL-LOOP DEGENERATED DIFFERENTIAL PAIR

(6) In the standard version of this circuit, the current sources are (i.e., fixed and tuning is performed by a loop controlling controlling ). To achieve a significant tunability, the value must be large compared to unity (in this case, the transcon). This ductance of the cell can be approximated as condition strongly extends the linear range with respect to a nondegenerated differential pair having the same overdrive voltage, but it is undesirable from several points of view, most notably for (i.e., power efficiency reasons. In fact, to achieve a certain ), it is necessary to have while in the nondegenis equal to . Moreover (due to contribution erated case from devices other than the input ones), the input-referred noise which, for this reason, spectral density increases at high should be kept small.

A significant improvement in the power efficiency of the degenerated differential pair can be obtained introducing only a small amount of degeneration. The basic idea is to control the degeneration resistor in order to have the smallest degeneration required to guarantee the linearity needed. In this case, to achieve a wide tuning range, the transconductance value needs to be controlled mainly through the tail currents (as in the nondegenerated case). with the One of the simplest solutions is to realize equal to the scheme of Fig. 9(b) with the tuning voltage common-mode voltage (VCM). The degeneration MOS M3 will have an overdrive voltage equal to that of the MOS used in and the resistance can be the differential pair expressed as (11)

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where

Then, in this case, the and its value is

factor is independent from

(12) value is proportional to (as in the nondegenerated The case), so the achievable tuning range increases to the first order . In fact, the highest value is the same as by can be reduced for the nondegenerated case while the lowest for the same distortion. The cost of this tuning by extension is a power efficiency reduction, which is particularly values where power consumption is troublesome at high high. A significant power efficiency improvement can be achieved increases. This if the degeneration resistance decreases as is achieved controlling the voltage overdrive of the MOS M3 with the following law: (13) where has the dimension of Volt It follows that .

Fig. 10.

control.

control is performed by two loops: of the differential pair a main loop controlling the through the tail currents; through an auxiliary loop controlling the resistance . the voltage Both loops work simultaneously, however the one controlling is much faster than the other in order to avoid stability problems. Further improvement could have been achieved with the following law: (18)

The

(14) (15) (16)

and having the dimension of Volt . with This last solution has not been implemented because it requires a more complicate implementation and also because a similar result can be achieved with the multirange approach shown in the following section. V. FILTER IMPLEMENTATION

In this case, the degeneration amount is not fixed but depends on the voltage overdrive of the input pair. The degeneration decreases when factor increases. This behavior is good for several reasons. At high values, the degeneration factor can be small because distortion being high). Reducing the is intrinsically low (as a result of degeneration factor improve power efficiency where is critical, i.e., at high power dissipation. Opposite considerations apply at where a large degeneration factor is required, because low in this region there is the highest distortion. The resulting power efficiency degradation is of low concern because here power dissipation is low. expression as a function of Moreover, looking at the (17) on is more than linear. This increases the dependence of tuning range for the same allowed range. the The transconductor presented in this paper has been designed according to the above law. The very simple circuit implementing the described idea is shown in Fig. 10 (where ). In fact, a voltage proportional to can be easily realized as the voltage across a resistor biased with the tail current of the transconductor.

In this section, we discuss the design of an eighth-order filter implementing the topology proposed in Section II and the transconductor presented in Section IV. A. Tuning Range Extension The tuning range achievable with the proposed transconductor is not wide enough to cover the required 1:4 range over all worst cases conditions. A multirange solution has been implemented to extend the tuning interval. The idea of connecting in parallel a programmable array of identical transconductors has been ruled out for matching considerations related to the small sizes of the elementary transcon(minimum size). ductors at low The solution implemented uses in every range the same differential pair, while the degeneration resistance value is modrange used. Even implementing the ified according to the the tune control presented in the previous section, at high , so, more degeneration delinearity is higher than at low vices can be put in parallel in order to reduce the resistance and increase the transconductance. Fig. 11 shows the simulated current consumption and the THD (in typical conditions) as a function of the cutoff frequency. For a fixed external resistor, the cutoff frequency can be tuned in a 1:3 range. It is possible to use the same filter for different applications changing the ex-

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Fig. 11. Simulated power consumption and THD as a function of the input frequency.

ternal resistor. In this case, the total frequency range covered is 1:4. In the low frequency ranges, the voltage drop across the degeneration resistors can be as big as 50% of the input signal amplitude introducing distortion problems related to the nonideality of the MOS resistors. A significant improvement has been achieved realizing these resistors as the series of two MOS biased in triode region. Fig. 12 shows the complete transconductor scheme. B. Complete -Control Scheme

The transconductance values are controlled through a resistor servo approach. Two loops fix the bias condition of a reference inversely proportional transconductor in order to have its to a precise external resistor. All the other transconductors are biased as replicas of this master one. Fig. 13 shows the complete -control scheme. The reference transconductor is folded for headroom and its differential output is converted to single-ended. It is driven by and its output current is forced to be a fixed dc voltage equal to the DAC current whose full-scale value is derived from is the external resistor on which a voltage proportional to forced. The main loop adjusts the tail currents of the differential pair while the auxiliary loop controls the tuning voltage of the degeneration devices. This auxiliary loop is realized using the , and a current proporoperational amplifier , the resistor tional to the tail current of the transconductor. To avoid interaction between the two loops, the auxiliary one has been designed

Fig. 12.

Complete transconductor scheme.

to be much faster than the main one. To achieve this, opamp is used to drive the degeneration transistors with a wide bandwidth. C. Boost Implementation As explained in Section II, the high-frequency boost is provalue in (2). The tuning range regrammed through the

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Fig. 13.

Complete

-control scheme.

Fig. 14.

LSB implementation of the transconductor used for boost programmability.

quired for is much bigger than the range required for the other transconductors. In fact, to achieve the 614 dB boost value must be tuned in a 1:2.8 range above the range, the 1:4 range for frequency tuning. The overall required tuning is 1:11.2. tuning is realized conThis further extension of the necting in parallel a programmable array of binary sized transconductors. The dimensions required for the two LSBs are too small to be integrated with sufficient accuracy. For this reason, they have been built with the scheme shown in Fig. 14. The differential pair of the transconductor is split in a programmable array. Each elementary cell can be connected to the output or to the reference common-mode voltage. In this way, the dc output current of the differential pair is dependent of the selected boost value, therefore, also the active loads from the voltage supply are made dependent on the same value.

Fig. 15.

Core filter layout.

D. Practical Design Consideration Capacitors are realized by nMOS transistors biased in inversion featuring a large capacitance per unit area ( fF m ). The voltage swing across them (100 mV peak to peak) is small com-

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Fig. 16.

Measured amplitude and group delay responses at f

=40 MHz and 120 MHz at the highest boost value.

Fig. 17.

Simulated THD as a function of the input frequency.

pared to the dc voltage ( V), making their distortion negligible with respect to other sources. The area of the capacitors array is 25% of the total. The core filter layout is shown in Fig. 15. The sizes of the input pairs have been chosen according to different constraints. They should be small to reduce the input capacitance but, on the other hand, they should be large to have a good matching. Moreover, the finite output impedance of the input pair devices could alter the ideal frequency response of the filter (the effect of the active loads is small since they have been cascoded). m that is The channel length used for these devices is twice the minimum length allowed by the process. This gives a

worst-case gain at the highest cutoff frequency setting equal to 35 dB sufficient to make its effect negligible. VI. IMPLEMENTATION RESULTS In this section, we present some simulation and experimental results. The frequency response (amplitude and group-delay) have been measured at the highest boost at the extreme cutoff frequency conditions (for a fixed external resistor) and presented in Fig. 16. Due to a parasitic zero in the transconductor the boost amount is not independent from the programmed cutoff

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TABLE I PERFORMANCE SUMMARY

frequency. The experimental results (predicted by simulations) show a signficant dependence at the highest boost value (the effect is negligible at the minimum boost). The boost is higher at high cutoff frequency, for this reason the filter has been designed to have a maximum boost of 16 dB (instead of 14) at the highest frequency in order to cover the 614 dB range in every case. InFig.17,thesimulatedTHDatthehighestcutofffrequency(in typical conditions) and extreme boost values is reported as a function of the input frequency, the voltage amplitude is adjusted to havethenominal200mVpeak-to-peakdifferentialoutputvoltage swingaroundthe .Experimentalmeasurementsontheavailable samples validate these simulation results. The prototypes have been stressed to reach the upper limit of the cutoff frequency. These measurements have shown a signifMHz icant group delay flatness degradation around (in the same condition the THD is still good). Simulations show that the limitation at high frequency is mainly related to the parasitic singularities within the transconductors and to the finite output impedance. Table I gives a summary of the measured performance. VII. CONCLUSION A filter intended for hard disk drive read/write channels has been designed considering several aspects. The transfer function has been optimized to improve the immunity to implementation inaccuracy, while the filter architecture adopted assures a constant dynamic range irrespective to the amount of boost required to equalize the input signal. This result has been achieved minimizing the dependence on the boost value of both the voltage swing (at each filter node) and the output noise. Finally, a key issue of this design has been the transconductor choice. The solution implemented exploits the use of a degenerated differential pair tuned with a dual-loop control. The purfactor as small as possible in every conpose is to keep the dition (compatibly with the allowed THD). In this way a good

tradeoff between linearity, power consumption, and noise efficiency has been achieved. ACKNOWLEDGMENT The authors thank D. Ottini and R. Alini for helpful discussions and suggestions. They also thank M. Malfa for his support. REFERENCES
[1] G. A. De Veirman and R. G. Yamasaki, Design of a bipolar 10-MHz programmable continuous-time 0.05 equiripple linear phase filter, IEEE J. Solid-State Circuits, vol. 27, pp. 324331, Mar. 1992. [2] C. A. Laber and P. R. Gray, A 20-MHz sixth-order BiCMOS parasiticinsensitive continuous-time filter and second-order equalizer optimized for disk-drive read channels, IEEE J. Solid-State Circuits, vol. 28, pp. 462470, Apr. 1993. [3] N. Rao, V. Balan, and R. Contreras, A 3-V 10100 MHz continuous-time seventh-order 0.05 equiripple linear phase filter, IEEE J. Solid-State Circuits, vol. 34, Nov. 1999. [4] R. Alini, A. Baschirotto, and R. Castello, Tunable BiCMOS continuous-time filter for high-frequency applications, IEEE J. Solid-State Circuits, vol. 27, Dec. 1992. -C filter [5] I. Mehr and D. R. Welland, A CMOS continuous-time for PRML read channel applications at 150 Mb/s and beyond, IEEE J. Solid-State Circuits, vol. 32, Apr. 1997. [6] W. Dehaene, M. S. J. Steyaert, and W. Sansen, A 50-MHz standard CMOS pulse equalizer for hard disk read channels, IEEE J. Solid-State Circuits, vol. 32, July 1997. [7] F. Krummenacher and N. Joehl, A 4-MHz CMOS continuous-time filter with on-chip automatic tuning, IEEE J. Solid-State Circuits, vol. 23, June 1988. [8] V. Gopinathan, M. Tarsia, and D. Choi, A 2.5-V, 30-MHz, 100-MHz, seventh-order equiripple group-delay continuous-time filter and variable-gain amplifier implemented in 0.25-m CMOS, in ISSCC Dig. Tech. Papers, Feb. 1999, pp. 394395. [9] S. Pavan, Y. Tsividis, and K. Nagaraj, Widely programmable high-frequency continuous-time filters in digital CMOS technology, IEEE J. Solid-State Circuits, vol. 35, Apr. 2000. [10] F. Behbahani, W. Tan, A. Karimi-Sanjaani, A. Roithmeier, and A. A. Abidi, A broad-band tunable CMOS channel-select filter for a low-IF wireless receiver, IEEE J. Solid-State Circuits, vol. 35, Apr. 2000. [11] G. Bollati, R. Alini, R. Castello, M. Demicheli, and S. Portaluri, An eighth-order low-pass filter with 5100-MHz tuning range and programmable boost, in ESSCIRC Dig. Tech. Papers, Sept. 1999, pp. 5053.

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Giacomino Bollati received the degree in electronic engineering from the University of Pavia, Italy, in 1995. In 1995, he joined STMicroelectronics, Cornaredo, Italy, where he has been involved in the design of analog front-ends for hard disk drive read/write channels. Since 2000, he has been the analog project leader in the R/W Channels group. His main research interests include analog filters and amplifiers.

Marco Demicheli was born in Pavia, Italy, in 1964. He received the degree in electronic engineering (magna cum laude) in 1989 from the University of Pavia, where he spent one year working on low-noise preamplifier for particle detectors. He joined STMicroelectronics in 1990 as a Designer of power integrated circuits for hard disk drive applications. In 1992, he moved to the Read/Write Channel Group designing mixed-signal ICs for hard disk drives. Since March 2000, he has been working for Maxim Integratred Products, Assago, Italy, as Design Director of the Italian design center.

Stefano Marchese was born in Pavia, Italy, in 1968. He received the degree in electronic engineering from the University of Pavia in 1993. He had a fellowship in the Italian Program for Bioelectronics Technology and he spent one year with the University of Pavia on analog design in CMOS technology (analog memory for image processing). In 1995 he joined STMicroelectronics, Cornaredo, Italy, in the Hard Disk Drive Group. He worked on amplifiers, filters, and PLLs in CMOS and BiCMOS technology.

Rinaldo Castello (S78M78SM92F99) was born in Genova, Italy, in 1953. He graduated in electronics engineering from the University of Genova in 1977. He received the M.S. and Ph.D. degrees from the University of California at Berkeley in 1981 and 1984, respectively. From 1983 to 1985, he was a Visiting Assistant Professor at the Electronics Department of the University of California at Berkeley. In 1987, he joined the Department of Electronics at the University of Pavia, Italy, as an Associate Professor. He also acts as a Consultant to STMicroelectronics, Milan, Italy. His research activities are in the field of integrated circuits for analog/digital interfaces, mainly oriented toward telecom applications. Dr. Castello has been a member of the technical committees of the European Solid State Circuit conference (ESSCIRC) since 1987, the International Solid State Circuit Conference (ISSCC) since 1992, and was Technical Chairman of ESSCIRC91. He was Guest Editor of the July 1992 special issue of the IEEE JOURNAL OF SOLID-STATE CIRCUITS.