THE IAS COMPUTER ARCHITECTURE Or

The von Neumann Machine The IAS machine was the first electronic computer built at the Institute for Advanced Study (IAS), in Princeton, New Jersey, USA. It is sometimes called the von Neumann machine, since the paper describing its design was edited by John von Neumann, a mathematics professor at both Princeton University and IAS. The computer was built from late 1945 until 1951 under his direction. The general organization is called Von Neumann architecture. This is regarded as the Prototype of all subsequent general-purpose computers. The IAS computer has the following features, Stored-Program concept Main memory stores both data and instructions Program Control unit (PCU), interprets the instructions in memory Data Processing unit (DPU) is responsible for executing binary instructions. This is also known as data-path or execution unit Input and output (I/O) equipment operated by the control unit The organization of the CPU and main memory of the IAS computer is as follows,

Organization of the CPU and main memory of the IAS computer

Memory: The basic unit of information in the IAS computer is a 40-bit word, which is the standard unit of information stored in a memory location or transferred in one step between the CPU and the main memory M. The size of the main memory is 4K 40 bit words and a secondary storage of 16K words based on electromechanical magnetic drum technology was provided for bulk storage. Each location in M can be used to store either a single 40-bit number or else a pair of 20-bit instructions. Data Format:

IAS Number Format The IASs number format is fixed-point, meaning that it contains an implicit binary point in some fixed position. Numbers are usually treated as signed binary fractions lying between -1 and +1, but they can also be interpreted as integers. Examples of IASs binary format are 0110100000 0000000000 0000000000 0000000000 = + 0.8125 1001100000 0000000000 0000000000 0000000000 = - 0.8125 Instruction Format:

IAS Instruction Format Each memory location is capable of storing two 20 bit instructions. If M(X) denotes the 40-bit memory word with address X, then M(X, 0:19) denotes the half word consisting of bits 0 through 19 of M(X) , also called as left instruction and M(X, 20:39) denotes the half word consisting of bits 20 through 39 of M(X) , also called as right instruction. An IAS instruction consists of an 8-bit opcode (operation code) followed by a 12-bit address A that identifies one of up to 212 =4K

40-bit words stored in M. The IAS computer thus has a one-address instruction format, which is represented symbolically as OP A The Program Control unit (PCU) operates the IAS by fetching instructions from memory and executing them one at a time. The Program Control unit and the Data Processing unit contain storage locations, called registers. The PCU has circuits to interpret opcodes and to issue control signals to the DPU, memory and other circuits involved in executing instructions. The PCU can modify the instruction execution sequence when required to do so by branch instructions. The PCU contains the registers IR (Instruction register), IBR (Instruction buffer register), AR (Address register) and PC (Program Counter). The DPU has the necessary component, the ALU which contains the circuits that perform addition, multiplication, etc; The DPU has the DR (Data register), AC (Accumulator) and MQ (multiplier quotient) registers. Registers: Instruction register (IR): It is one of the major components of PCU and contains the 8-bit opcode instruction being executed. Instruction buffer register (IBR): The IAS fetches two instructions at a time from memory, so it contains a second register, the instruction buffer register for holding a second instruction. Address register (AR): It holds the address of a data operand to be fetched from or sent to main memory. Program Counter (PC): contains the address of the next instruction to be fetched from memory. Data register (DR): Data register normally contains a word to be stored in memory, or issued to receive a word from memory. Accumulator (AC) and multiplier quotient (MQ): The accumulator is a special register normally used for arithmetic operations and holds the end result of the operation. The MQ is a special register used for multiplication and division operation.

Instruction Set: The IAS computer has around 30 types of instructions which can be grouped as follows: Data transfer: These instructions move data between memory and ALU registers or between two ALU registers. Data Processing: These instructions specify the operations performed by the ALU. Program control or branch instructions: These instructions determine the sequence in which instructions are executed. Instruction execution can be made dependent on a condition, thus allowing decision points. It also performs the operation of address computation in the ALU and then it is inserted into instructions stored in memory

Instruction Set of IAS

Instruction Execution: The IAS fetches and executes instructions in several steps that form an instruction cycle. The IAS fetches two instructions in an instruction cycle. Each instruction cycle consists of two sub cycles. Fetch cycle: The opcode of the next instruction is loaded into the IR and the address portion is loaded into the AR. This instruction may be taken from the IBR, or it can be obtained from memory by loading a word into the DR, and then down to the IBR, IR, and AR. Execute cycle: The control circuitry interprets the opcode and executes the instruction by sending out the appropriate control signals to cause data to be moved or an operation to be performed by the ALU.