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Learning Objectives:
At the end of this topic you will be able to; 1. .1 ! Intr"d#cti"n. Recognize high/low, 1/0, as two state logic levels; 1. .$ ! Tr#t% Tab&es. Draw symbols and construct truth tables for A D, !R, !", !R, and A D gates; #roduce a truth table for a system of up to five gates; Devise a system of gates from a truth table; Design simple systems using logic gates to solve a given problem; Use '""&ean n"tati"n as a s%"rt%and (et%"d ") e*+ressing a tr#t% tab&e, 1. .- ! Use ") data s%eets. $se data sheets to; o %elect a logic &' for given applications; o &dentify pin connections of logic gates; 1. .. ! N/N0 gate i(+&e(entati"n. S%"1 %"1 "t%er gates can be (ade #+ )r"( N/N0 gates, I(+&e(ent a given &"gic circ#it #sing N/N0 gates, Re("ve d"#b&e inversi"ns, 1. .2 ! 3#&& #+4d"1n resist"rs. Rec"gnise t%e #se ") +#&& #+4d"1n resist"rs t" +r"vide t%e c"rrect &"gic &eve&s at a gate in+#t.
&n this topic we will be concentrating on the basics of digital logic circuits which will then be e(tended in )odule *+, -e should start by ensuring that you understand the difference between a digital signal and an analogue signal, /n ana&"g#e signa& "his is a signal Voltage (V) that can have Max any value between the zero and ma(imum of the power V supply, 'hanges 0Min between values can occur slowly or rapidly depending on the system involved, / digita& signa& "his is a signal Voltage (V) that can "n&5 have t1" finite values, usually at Max zero and ma(imum of the power supply, V 'hanges between 0 Min these two values occur instantaneously,
time (s)
time (s)
LOGIC CIRCUITS and SWITCHING THEORY .or this part of the course we will concentrate on digital systems, Reca+ ") 1"r6 c"vered in S#b7s5ste(s 8t"+ic 1.$9 -hen an input or output signal is at the minimum power supply voltage /usually 001 this is referred to as a LOW signal or LOGIC : signal, -hen an input or output signal is at the ma(imum power supply voltage this is referred to as a HIGH signal or LOGIC 1 signal, Re(e(ber t%en t%at a digita& signa& is a t1" state s5ste( 1it% in+#t and "#t+#t signa&s being eit%er re)erred t" as %ig%4&"1; :41; "n4")) de+ending "n t%e a++&icati"n. -e will now loo2 at the basic building bloc2 of all digital systems, the logic gate, and their associated truth tables, N"te 3ogic gates are available with up to 4 inputs per gate which may be useful for pro5ect wor2 later on in the course, but for this introductory section and for the purposes of the e(amination 6uestions we will only consider + input logic gates,
Unit E1 : 0isc"vering E&ectr"nics 1. .$ Tr#t% Tab&es 7ere is a summary of the three logic gates you have already studied
8A"*
A
%9):!3
Q
"R$"7 "A:3*
.$ '"&!
In+#t A 0 1
O#t+#t Q 1 0
%ignal out of gate is the opposite of the signal in i,e, it inverts the input signal "he output ; is only at a logic 1 when input A /N0 input B are at a logic 1
In+#ts A B
A
O#t+#t Q 0 0 0 1
A D
0 0 1 1
0 1 0 1
A B
In+#ts A B !R 0 0 1 1 0 1 0 1
O#t+#t Q 0 1 1 1
-e will now loo2 at two additional logic gates< T%e N/N0 gate "he symbol for a + input
A B
A D gate is<
Q
B 0 1
&f you compare this truth table with that for the A D gate, you will find that the output Q is the e(act opposite of the A D,
LOGIC CIRCUITS and SWITCHING THEORY T%e NOR gate "he symbol for a + input
A B
!R gate is<
Q
&f you compare this truth table with that for the !R gate, you will find that the output Q is the e(act opposite of the !R, ow let us see what you can remember =
Unit E1 : 0isc"vering E&ectr"nics E*ercise 1 1, 3oo2 at the following logic symbols labelled A > *,
'
-hich is the correct symbol for an A D gate, -hich is the correct symbol for a -hich is the correct symbol for a -hich is the correct symbol for a !" gate, !R gate, A D gate@
+,
LOGIC CIRCUITS and SWITCHING THEORY ii, !R gate, In+#ts A 0 0 1 1 iii, A D gate, In+#ts A 0 0 1 1 iv, !R gate, In+#ts A 0 0 1 1 B 0 1 0 1 O#t+#t Q B 0 1 0 1 O#t+#t Q B 0 1 0 1 O#t+#t Q
Unit E1 : 0isc"vering E&ectr"nics 3ractica& L"gic Gates 3ogic gates are usually supplied in plastic d,i,l, /dual in line1 pac2ages containing multiple copies of one type of logic gate, "he following diagram shows a picture of this type of pac2age,
Pin 1 identification
Pin 1
"here are two common types available, ""3 or AB(( series and ')!% or B((( series, &t is li2ely that you will come across both types in your practical wor2, so whatCs the difference between them@ "he 2ey differences are outlined in the table below< 3ara(eter %upply 0oltage 3ogic 0 range 3ogic 1 range .re6uency of operation /)a(1 #ower consumption TTL 8<.** )a(i&59 D0 0,+D0 only 0 to 0,40 +,0 to D,00 D0 )7z 10m- / gate C=OS 8.*** )a(i&59 E0 to 140 :elow E0F of supply voltage Above A0F of supply voltage B )7z 0,1m- / gate
"his information will be important in practical wor2, as you will need to 2now which type of logic gate you are using, 9ou will also need to be careful how you connect each logic gate into your circuit,
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LOGIC CIRCUITS and SWITCHING THEORY "o be able to identify which leads are connected to which gate you need to loo2 at a data sheet for the actual logic gate you are using, 7ere are two data sheets from the ""3 /AB((1 family,
&t is important that you chec2 the connections every time you use a logic gate as connecting these incorrectly can result in the whole logic chip being destroyed, Y"# 1i&& n"t be re>#ired t" 6n"1 t%e di))erence bet1een TTL and C=OS devices in t%e e*a(inati"n. T%is is re>#ired )"r an5 +ractica& tests t%at 5"# carr5 "#t; and 1i&& be +artic#&ar&5 i(+"rtant )"r 5"#r +r"ject 1"r6. 9ou will however need to be able to identify the output pin of a logic gate given its symbol, .or e(ample if you are given the pinout of the ABE+ device shown above you can be as2ed to identify the pin numbers of the outputs of the logic gates, &n this case the relevant pin numbers are; E, G, 4 H 11, Alternatively you might be as2ed to identify the power supply connections, in which case the answer would be #in 1B for the positive supply and #in A for the negative of the supply,
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Unit E1 : 0isc"vering E&ectr"nics E*ercise $ "he pin out diagrams for a logic &' is shown below,
a1 b1 c1
7ow many logic gates are contained in this &'@ ?,,,,,,,,,,,,,,,,,, 7ow many inputs does each gate have@ ,,,,,,,,,,,,,,,,,,,,,,,
8ive the number of the pin connected to the output of gate 8@ ?????????
d1 e1
-hich t1" pins should be connected to the power %upply@ ,,,,,,,,,,,,,,, -hat is the name given to the type of logic gate contained in this &'@ 'hoose from the following list< /N0 OR NOT N/N0 NOR
Answer< ????????????????????????????????????
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LOGIC CIRCUITS and SWITCHING THEORY /na&5sis ") si(+&e &"gic circ#its &n the e(amination you will have to recognise truth tables for these basic gates individually for some of the easier 6uestions in the e(amination, 7owever, it is much more li2ely later on in the paper that these gates will be lin2ed together in simple combinations and you will be as2ed to complete a truth table for a larger system, -e will now consider a couple of e(amples of these systems, 1, %tudy the following logic system carefully and then complete the truth table that follows<
In+#ts A
0 0 1 1
B
0 1 0 1
O#t+#ts C Q
&n this problem, the output of the !" gate has been labelled I CC, "he first stage is to complete the output column for I CC which is the !" of IAC as shown below, In+#ts A
0 0 1 1
B
0 1 0 1
O#t+#ts C Q
1 1 0 0
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Unit E1 : 0isc"vering E&ectr"nics ow we need to complete the final column Q which is the output of the A D gate with IBC and ICC as the inputs, In+#ts A
0 0 1 1
B
0 1 0 1
O#t+#ts C Q
1 1 0 0 0 1 0 0
0" n"t fall into the trap of writing the answer to the Q column in the order you would normally do for the truth table for an A D gate, :ecause the inputs to the A D gate are B and C rather than A and B, the logic 1 in the Q column appears in the row where B and C are both 1 rather than when A and B e6uals 1,
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LOGIC CIRCUITS and SWITCHING THEORY +, %tudy the following logic system carefully and then complete the truth table that follows<
A
0 0 0 0 1 1 1 1
In+#ts B
0 0 1 1 0 0 1 1
C
0 1 0 1 0 1 0 1
O#t+#ts G
9ou can see that the truth table for a E input logic system contains 4 possible input combinations, otice the way the logic state of each input changes as you move down the table, .irst complete the output column for the !" gate /'olumn .1 > JRemember the input is B,K "hen complete the output column for the A D gate /'olumn 81 > JRemember the inputs are F and C,K .inally complete the final output from the !R gate /'olumn ;1 > JRemember the inputs are A and GK A solution to this problem will be found at the end of this chapter,
Unit E1 : 0isc"vering E&ectr"nics E*ercise 1, %tudy the following logic system carefully and then complete the truth table that follows<
In+#ts A
0 0 1 1
B
0 1 0 1
O#t+#ts K Q
+,
%tudy the following logic system carefully and then complete the truth table that follows<
A
0 0 0 0 1 1 1 1 16
In+#ts B
0 0 1 1 0 0 1 1
C
0 1 0 1 0 1 0 1
O#t+#ts G
LOGIC CIRCUITS and SWITCHING THEORY E, %tudy the following logic system carefully and then complete the truth table that follows<
A
0 0 0 0 1 1 1 1
In+#ts B
0 0 1 1 0 0 1 1
C
0 1 0 1 0 1 0 1
O#t+#ts F
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Unit E1 : 0isc"vering E&ectr"nics Trans)erring a tr#t% tab&e int" a L"gic 0iagra( &n the previous section we loo2ed at how a system of logic gates could be used to complete a truth table to illustrate the conditions needed for the output to operate, -e will now consider how we can reverse this process and construct a logic circuit diagram from a truth table, "his is best done by loo2ing at a couple of e(amples, N"te &n the following e(amples the outputs have been chosen so that they are n"t the output of one of the five logic gates considered previously, E*a(+&es: 1, "he following truth table represents a particular logic function, $se the information in the table to draw a corresponding logic gate system that will produce this function, In+#ts A 0 0 1 1 B 0 1 0 1 O#t+#t Q 0 0 1 0
-e first have to identify all the combinations of the inputs that cause the output to come on, &n this case it only occurs once, when input A is on and input B is n"t on, "he description of what is re6uired to cause the output to operate gives a very good clue as to the logic gates re6uired in this e(ample, &n this case two logic gates are re6uired, a !" gate and an A D gate, "he !" gate is used to invert the B input, as shown below,
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LOGIC CIRCUITS and SWITCHING THEORY "he output of this !" gate is then connected to the A D gate with input A to provide the full solution, as follows<
?#ic6 R#&e &n any +Linput logic system, for every row of the truth table for which the output is logic 1, this output can be written in terms of the following input conditions< /; NOT /; '; NOT ' depending whether there is a 0 or a 1 in that cell, "he + inputs are lin2ed with an A D gate, 8oing bac2 to our e(ample we identify the output row where Q is a logic 1 and note that A M 1 and B M 0, :ecause B is 0 we write it down as NOT B as shown< In+#ts A 0 1 1 1 B 0 0 0 1 O#t+#t Q 0 0 1 0
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Unit E1 : 0isc"vering E&ectr"nics +, "he following truth table represents a particular logic function, $se the information in the table to draw a corresponding logic gate system that will produce this function, In+#ts A 0 0 1 1 B 0 1 0 1 O#t+#t Q 1 0 0 1
-e first have to identify all the combinations of the inputs that cause the output to be logic 1, &n this case it occurs in + rows of the truth table, -e then label these output as e(plained above in the N;uic2 RuleO, In+#ts A 0 0 1 1 B 0 1 0 1 O#t+#t Q 1 0 0 1
!utput M A /N0 B "he output re6uired for the first line of the truth table is therefore<
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and the output re6uired for the last line of the truth table is<
%o far we have two separate logic systems providing the output ;, -e need to lin2 the two systems together so that either system can produce the output, "his is achieved by using an !R gate as shown below<
-e have some duplicated input terminals here now so the circuit diagram can be simplified by lin2ing these together as shown below,
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Unit E1 : 0isc"vering E&ectr"nics Tr#t% tab&es 1it% (#&ti+&e "#t+#ts ;uite often a logic system will have more than one output, .or e(ample a set of traffic lights might have E outputs, .or this type of system we can follow a simple set of rules, .or each output column of the truth table as2 yourself the following 6uestions in the order listed below 1, &s the output column pattern the same as one of the input column patterns@ &f the answer is yes then Q M N"he &nputO /e,g, Q M B1 +, &s the output column pattern the inverse of the input column pattern@ &f the answer is yes then Q M E, !" N"he &nputO /e,g, Q M !" C1
&s the output column pattern the same as a logic gate output@ &f the answer is yes then Q M Nlogic gate e(pressionO /e,g, Q M A !R B1
B,
&s the output column pattern the inverse of one of the other output patterns already identified@ &f the answer is yes then Q M !" N!ther !utputO /e,g, Q3 M !" Q11
D,
$se the N;uic2 ruleO by labelling rows of the outputs which are logic 1 and lin2 with an !R gate e,g, Q M P !" A A D !" BQ !R PA A D BQ
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LOGIC CIRCUITS and SWITCHING THEORY E*a(+&e "he following truth table shows the outputs re6uired for three 3*Ds 3*Ds used to represent the operation of a set of traffic lights, Determine the combination of logic gates re6uired to produce the output pattern shown, In+#ts A 0 0 1 1 B 0 1 0 1 Red 1 1 0 0 O#t+#ts Yellow Green 0 0 1 0 0 1 1 0
7ere we have three separate outputs to be produced by 5ust two inputs, to solve this we 5ust treat each individual output as a separate problem, &f you e(amine the input A column and Red output column carefully what do you notice@ "hey are reproduced below with these columns In+#ts A 0 0 1 1 highlighted, B 0 1 0 1 Red 1 1 0 0 O#t+#ts Yellow Green 0 0 1 0 0 1 1 0
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Unit E1 : 0isc"vering E&ectr"nics 'omparing the two highlighted columns we can see that the Red output is the e(act opposite of the A input column, "his means that if we simply invert the input A signal, this will produce the Red output, i,e, Red M !" A
ow for the Yellow output, again chec2 the truth table carefully, "he solution is that the Yellow output follows the B input e(actly, and therefore to produce the Yellow output no logic gates are re6uired, &t is simply a case of connecting the Yellow output to the B input, i,e, Yellow M B
.inally we have to consider the Green output, A chec2 of the truth table shows there is no simple relationship to the inputs as was the case with the Red and Yellow outputs, either does the output correspond to the output of a logic gate, -e have no choice therefore other than to use the N;uic2 ruleO to solve this part of the problem, 9ou should be able to produce the system as shown below, In+#ts A 0 0 1 1 B 0 1 0 1 Red 1 1 0 0 O#t+#ts Yellow Green 0 0 1 0 0 1 1 0
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!" B
&f we connect all three sections together the final system design will loo2 li2e this<
ote< &f we were very observant we could have noticed that the Green output can be obtained from a !R gate connected to the Red and Yellow outputs, In+#ts A 0 0 1 1 B 0 1 0 1 Red 1 1 0 0 O#t+#ts Yellow Green 0 0 1 0 0 1 1 0
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i,e,
Green M Red
!R Yellow
&t is left to you to chec2 that both solutions produce the correct output pattern, 0" n"t 1"rr5 i) 5"# cann"t #nderstand %"1 t%e sec"nd s"&#ti"n 1as "btained as 5"# 1"#&d receive )#&& (ar6s )"r t%e )irst s"&#ti"n. ow its time for you to have a go, E*ercise . 1, "he following truth table represents a particular logic function, $se the information in the table to draw a corresponding logic gate system that will produce this function, In+#ts A 0 0 1 1 B 0 1 0 1 O#t+#t Q 0 0 1 0
,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
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LOGIC CIRCUITS and SWITCHING THEORY ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +, "he following truth table represents a particular logic function, $se the information in the table to draw a corresponding logic gate system that will produce this function, In+#ts A 0 0 1 1 B 0 1 0 1 O#t+#t Q 0 1 1 0
Unit E1 : 0isc"vering E&ectr"nics ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
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LOGIC CIRCUITS and SWITCHING THEORY E, An electronic system has two input sensors A and B, and three outputs P, Q and R, "he truth table showing how the input sensors control the outputs is shown below, In+#ts A 0 0 1 1 B 0 1 0 1 P 1 1 0 0 O#t+#ts Q 0 0 0 1 R 1 0 0 0
/a1 %tudy the P output, &t is the inverse of one of the inputs, -rite down an e(pression to describe this output, P M ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, /b1 %tudy the Q output, "here is one type of logic gate that will provide this, -hat is the name of this gate@ ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, /c1 %tudy the R output, "here is one type of logic gate that will provide this, -hat is the name of this gate@ ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, /d1 9ou have a selection of A D, !R, !", A D and !R gates available, Draw a labelled diagram to show how the logic system can be made,
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Unit E1 : 0isc"vering E&ectr"nics B, "he following truth table shows the outputs re6uired for three 3*Ds used to represent the operation of a set of traffic lights, Determine the combination of logic gates re6uired to produce the outputs re6uired, In+#ts A 0 0 1 1 B 0 1 0 1 Red 0 0 1 1 O#t+#ts Yellow Green 1 0 0 1 1 0 0 0
,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, '""&ean N"tati"n 8Hig%er Leve& T"+ic9
30
"here is also a shorthand way of writing down the function of logic gates, using a special type of algebra called '""&ean /&gebra, "his is used e(tensively for advanced wor2 in digital electronics, -e shall briefly consider how to e(press the output of a truth table and logic gates in :oolean notation, -e will start by loo2ing at the five basic gates we have introduced previously, "here are E basic things to remember 1, A dot N,O between two input labels is read as NA DO +, A plus NRObetween two input labels is read as N!RO E, A bar N S O over the top of an input label is read as N !"O
Gate
NOT /N0
Q = A.B
A Q
S5(b"&
Q =A
'""&ean N"tati"n
8read as Q @ NOT A 9 8read as Q @ A /N0 B9
A B A B
OR
Q = A +B
8read as Q @ A OR B9
N/N0 NOR
Q = A.B
A B A B
Q = A +B
&n addition to the five :oolean notations shown above, each line of a truth table for which the output is a N1O can also be written in :oolean notation
31
Unit E1 : 0isc"vering E&ectr"nics 'onsider the solution to e(ample + on page 1T In+#ts A 0 0 1 1 B 0 1 0 1 O#t+#t Q 1 0 0 1
In+#ts A 0 0 1 1 !utput M
!utput M
A AND B
!utput M A AND B Remember that these e(pressions need to be lin2ed together with an OR gate to produce the output Q, so the full :oolean e(pression for Q can be written as
32
( ) Q = (A.B ) + ( A.B )
Q = A AND B OR ( A AND B )
E*ercise 2 1, "he :oolean e6uations labelled A > *, below are to be used to answer the following 6uestions, A1 :1 '1 D1 *1 i, ii,
Q = A.B
Q = A +B
Q = A +B
Q =A
Q = A.B
-hich e(pression is correct for an A D gate, -hich e(pression is correct for a !" gate, !R gate, A D gate,
iii, -hich e(pression is correct for a iv, -hich e(pression is correct for a
A 0 0 1 1
B 0 1 0 1
X 1 0 1 0
Y 0 0 0 1
Z 0 1 0 0
34
LOGIC CIRCUITS and SWITCHING THEORY L"gic S5ste( 0esign &n the previous two sections we have considered the function of a number of logic gates that are available for us to use in electronic system design, -e have derived a truth table from a logic circuit, and we have constructed a logic circuit from a truth table, &n this section we will be completing the design process by converting a design brief of a problem into a truth table, !nce this has been achieved then we can use the techni6ues used in the last section to complete the logic circuit design, 0esign 3r"b&e(s 1, A logic system has two input sensors A and B and two outputs, !utput 1 is high when sensor A is high and sensor B is high, !utput + is high either when sensor A is low and sensor B is high or when sensor A is high and sensor B is high, a1 b1 S"&#ti"n: a1 !/p 1 is high only when A M 1 and B M 1, &dentify this cell in the o/p 1 column at the truth table and place a I1C in it, #lace zeroCs in the three other cells in the o/p 1 column, !/p +, is high when A M 0 and B M 1 or when A M 1 and B M 1, &dentify these two cells in the o/p + column of the truth table, #lace a I1C in these two cells and zeroCs in the other two, In+#ts A 0 0 1 1 B 0 1 0 1 O#t+#ts O/p 1 O/p 2 'omplete the truth table to satisfy these conditions Draw the circuit diagram for the logic system,
35
Unit E1 : 0isc"vering E&ectr"nics b1 9ou should have obtained the following truth table, In+#ts A 0 0 1 1 B 0 1 0 1 O#t+#ts O/p 1 O/p 2 0 0 0 1 0 0 1 1
*(amine the o/p 1 pattern, 9ou should realise that it is the same pattern as for an A D gate, *(amine the o/p + pattern, 9ou should realise that it is the same as input B, "he circuit diagram can then be drawn,
36
LOGIC CIRCUITS and SWITCHING THEORY +, A system is re6uired that will monitor a carCs cooling system, -hen the water level in the radiator is below a certain level a 3*D will light up, -hen the engine temperature is above a preLdetermined value and the water level is too low a buzzer should sound in addition to the 3*D lighting up, "he positioning and signals out of the sensors used are shown below,
"adiator A Moisture Sensor
Sens"r / 8("ist#re9 $%&%e lo'() le*el -et 0 Dry 1 Sens"r ' 8te(+erat#re9 state &"gic &eve& 'ool 0 7ot 1
B Te !erature Sensor
a1
'omplete the following truth table for the system, In+#ts A 0 0 1 1 B 0 1 0 1 O#t+#ts ED !"##er 0 0 1
b1
%tudy the 3*D output and compare it with the inputs, -hat do you notice@
37
Unit E1 : 0isc"vering E&ectr"nics ?????????????????????????????????????????????? ?????????????????????????????????????????????? c1 %tudy the buzzer output, "here is one type of gate that will provide this output pattern, -hat type of logic gate is re6uired@ ????????????? 'omplete the following diagram showing how the system can be made up,
d1
E,
:efore ta2e off, the pilot and coLpilot of an aircraft carry out preflight safety chec2s, -hen all chec2s have been completed they each move a switch from the up to the down position,
-hen both switches are up, a red indicator on the instrument panel is on, "his changes to yellow when at least one of them operate their switch, -hen both have operated their switches, a green indicator comes on, "he engines can only be started when the green indicator is on,
Assume that the switches provide logic level 0 in the up position and logic level 1 in their down position, "he 3*D indicators operate on logic level 1, a1
38
'omplete the following truth table for the system, "he IyellowC , Y column has been completed for you,
In+#ts A 0 0 1 1 b, B 0 1 0 1 R
O#t+#ts Y 0 1 1 1
G 0
%tudy the Y output, "here is one type of gate which will provide the re6uired output, -hat type of gate is it@ ?????????????
c,
%tudy the G output, "here is one type of gate which will provide the re6uired output, -hat type of gate is it@ ?????????????
d,
%tudy the R output, -rite down an e(pression to describe it, ?????????????????????????????????????????????? i, "he first solution is to recognise the output pattern as that, of a !R gate, i,e, R M A !R B
ii,
"he second solution is to recognise the output pattern as the inverse of !utput Y i,e, R M !" Y
39
B,
"wo sensors A and B are used to monitor a chemical process, !utput Q1 is a heater, output Q2 is a motor and output Q3 is a bell, "he heater is on either when sensor A is low and sensor B is high or when both sensors are low, "he motor is on when either A is low and B is high or when both sensors are high, "he bell comes on when both sensors are high, a1 'omplete the following truth table for the system, In+#ts A 0 0 1 1 b1 B 0 1 0 1 O#t+#ts Q1 Q2 +,e&%er- +.o%or0 1 1 1
Q3 +!ell0
-rite down an e(pression to describe Q1 and Q2 by comparing them with the inputs,
40
Q1 M ?????????????????????????????????????????? ?????????????????????????????????????????????? Q2 M ?????????????????????????????????????????? ?????????????????????????????????????????????? c1 -hich type of gate will provide the Q3 output@ ?????????????
41
ow itCs time for you to have a go, E*ercise A 1, A logic system has two input sensors A and B and three outputs,
!utput 1 is high when sensor A is low, !utput + is high when sensor A is low and sensor B is low !utput E is high when sensor A is high and sensor B is low,
a1
'omplete the truth table to satisfy these conditions "ruth "able O#t+#ts O/p 1 O/p 2
In+#ts A 0 0 1 1 B 0 1 0 1
O/p 3
42
LOGIC CIRCUITS and SWITCHING THEORY b1 i1 *(amine the !/p 1 pattern, "his can be generated from one of the input signals, -rite down the logic function re6uired to generate this output, ???????????????????????????? ii1 *(amine the !/p + pattern, "his can be generated from one of the standard logic gates, -rite down the logic function re6uired to generate this output, ???????????????????????????? iii1 *(amine the !/p E pattern, "his cannot be generated from the inputs using one of the standard logic gates, -rite down the logic function re6uired to generate this output, ???????????????????????????? c1 Draw the circuit diagram for the logic system,
43
Unit E1 : 0isc"vering E&ectr"nics +, A system is re6uired that will monitor a carCs cooling system, -hen the water level in the radiator is below a certain level a 3*D will light up, -hen the engine temperature is above a preLdetermined value and the water level is too low a buzzer should sound in addition to the 3*D lighting up, "he positioning and signals out of the sensors used are shown below,
"adiator A Moisture Sensor
Sens"r / 8("ist#re9 $%&%e lo'() le*el -et 1 Dry 0 Sens"r ' 8te(+erat#re9 state &"gic &eve& 'ool 1 7ot 0
B Te !erature Sensor
a1
'omplete the following truth table for the system, In+#ts A 0 0 1 1 B 0 1 0 1 O#t+#ts ED !"##er
b1
%tudy the 3*D output and compare it with the inputs, -hat do you notice@
44
?????????????????????????????????????????????? ?????????????????????????????????????????????? c1 %tudy the buzzer output, "here is one type of gate that will provide this output pattern, -hat type of logic gate is re6uired@ ????????????? 'omplete the following diagram showing how the system can be made up,
d1
E,
:efore leaving port, the loading bay controller and captain of a 'ar .erry carry out preLdeparture safety chec2s, -hen all chec2s have been completed they each move a switch from the down to the up position,
-hen both switches are down, a red indicator on the instrument panel is on, -hen any one of the switches, is in the up position, the indicator light changes to yellow, -hen both switches are in the up position, a green indicator comes on, "he engines of the 'ar .erry can only be started when the green indicator is on,
Assume that the switches provide logic level 0 in the up position and logic level 1 in their down position, "he 3*D indicators operate on logic level 1,
45
a1
'omplete the following truth table for the system, In+#ts A 0 0 1 1 B 0 1 0 1 R O#t+#ts Y
b,
%tudy the R output, "here is one type of gate which will provide the re6uired output, -hat type of gate is it@ ?????????????
c,
d,
%tudy the G output, "here is one type of gate which will provide the re6uired output, -hat type of gate is it@ ?????????????
e,
'omplete the following diagram showing how the system can be made up,
46
47
Unit E1 : 0isc"vering E&ectr"nics B, "wo sensors A and B are used to control the paint mi(ing process at a local D&9 store, "hree output valves control the flow of cyan, magenta, and yellow pigment, 0alve /1 is the cyan, 0alve /2 is the magenta, and 0alve /3 is the yellow, )i(ing occurs according to the following se6uence, A logic 1 operates the valve,
0alve 1 operates when input A is high and input B is high, 0alve + operates when input A is low and input B is low or when input A is high and input B is low, 0alve E operates when input A is low and input B is high or when input A is low and input B is low,
a1
'omplete the following truth table for the system, In+#ts A 0 0 1 1 B 0 1 0 1 /1 +)0&nO#t+#ts /2 /3 +.&'en%&- +0ellow-
b1 c1
-hich type of gate will provide the /1 output@ ????????????? -rite down an e(pression to describe /2 and /3 by comparing them with the inputs, /2 M ?????????????????????????????????????????? ?????????????????????????????????????????????? /3 M ?????????????????????????????????????????? ??????????????????????????????????????????????
48
LOGIC CIRCUITS and SWITCHING THEORY d1 Draw the circuit for the system
49
Unit E1 : 0isc"vering E&ectr"nics 1. .- Use ") data s%eets -hen you complete your pro5ect, you will need to e(amine data sheets for different logic gates, because as you have seen there are a lot of different logic gates available, and the connections for these vary between different types so you always have to chec2 carefully that you 2now where the power supply, inputs and outputs are connected to, 7ere are some of the more common AB(( %eries ""3 logic gates you might end up using in your pro5ect,
50
LOGIC CIRCUITS and SWITCHING THEORY "he following pin outs are from an alternative family of logic gates called the ')!% B((( series,
9ou could be as2ed to use these diagrams to answer a series of 6uestions about the logic gates in each particular pac2age, 7ere are some typical 6uestions based on the symbols on page BD/BG,
51
Unit E1 : 0isc"vering E&ectr"nics E*ercise < 1, +, E, B, D, G, A, 4, 7ow many logic gates are contained in the AB04 pac2age@ -hat type of logic gate is in the AB0+ i,c, pac2age@ -hat type of logic gate is contained in the B011 pac2age@ ???????? ???????? ????????
7ow many inputs do the logic gates in the B0A+ pac2age have @ ?????? -hat are the output pins of the AB04 pac2age@ -hich pac2age contains !" gates@ ??????????? ???????????
7ow many logic gates are there in the B00+ pac2age@ ??????????? -hich + pac2ages have some pins that are not connected to anything @ ???????????????????????????????????????????
T, 10,
-hat pin number is the positive supply for a B041 pac2age @ ????? -hat pin number/s1 are the inputs of the logic gate, whose output is connected to pin 1E of the B0A+ pac2age@ ????????????????????????????????????????????????
11, 1+,
???????
-hich AB(( family pac2age has an output pin connected to pin 1@ ????
52
LOGIC CIRCUITS and SWITCHING THEORY 1. .. N/N0 gate i(+&e(entati"n 8Hig%er Leve& T"+ic9
&n section 1,T,+ we found out how to construct logic systems from a truth table, "his often resulted in logic systems that re6uired a number of different types of logic gate /e,g, !", A D and !R1 in order to fulfil the function re6uired, &n some of the designs we have loo2ed at we ended up with 5ust one of three different types of logic gate needed in the final design, As we have seen from the last section only one type of logic gate is built inside each pac2age, and there could be as many as si( of these logic gates in the pac2age of which we are only going to use one, "his is very wasteful not only in terms of unused devices but also in the space needed on circuit boards to accommodate three different logic gate pac2ages, "he inverted gates, A D and !R are special because the function of all other gates can be made from various combinations of A D or !R gates, &n this syllabus only A D gate alternatives of the other logic functions will be discussed, Y"# (a5 )ind s"(e re)erence t" NOR gate &"gic in s"(e te*t b""6s b#t t%ese 1i&& n"t be as6ed )"r in t%e e*a(inati"n. :y using 5ust one type of logic gate we may be able to reduce the number of types of logic gate re6uired to ma2e any particular design, "his has a number of advantages< i, "here will be less confusion about which type of gate goes where in the circuit as they are all the same, ii, "here will be no need to 2eep stoc2s of all the different types of logic gate, therefore saving money, iii, 3arger 6uantities of a single type of gate can be purchased, which ma2es cost lower,
53
Unit E1 : 0isc"vering E&ectr"nics -e will now loo2 at an e(ample to show you how ma2ing this change can improve the situation, 'onsider the two logic circuits below, which perform the sa(e logic function, %ystem 1 < )i(ture of gates,
A B C
%ystem + <
A
A D gates only
Q B
-hen system + is compared to system 1, you may thin2 that we have made the circuit more complicated as we have more logic gates in system +, however, in system 1 t%ree different types of gates are re6uired !", !R and A D, "o construct system 1 using these gates would re6uire E different logic i,cCs, and many of the logic gates on these i,cCs would not be used, $sing system +, however, whilst there are four logic gates re6uired these are all of the same type, and only "ne logic i,c, would be re6uired where all gates in the i,c, are used,
54
LOGIC CIRCUITS and SWITCHING THEORY "his would provide a considerable cost saving compared to the design in system 1, &n industry if such systems are to be mass produced such savings can be considerable, and it is up to the engineers ma2ing the systems to use this techni6ue as much as possible to enable more profit to be made, ow that we 2now why A D gate logic is used letCs find out how to carry out this procedure, -e need to understand the combination of A D gates re6uired to replace each of our IstandardC gates, N/N0 gate e>#iva&ent circ#its )"r t%e )"#r "t%er gates
1.
T%e NOT gate "his is the simplest of the standard gates to form from A D gates,
is the same as
N"te "he A D e6uivalent of a !" gate is sometimes referred to as a N/N0 Inverter, 9ou will need to remember this for later on,
55
Unit E1 : 0isc"vering E&ectr"nics $. T%e /N0 gate "his is the inverse of a A D gate, and is simply a by an inverter / !" 8ate1,
A B Q A B X
A D gate followed
'omplete the truth table below for the In+#ts A 0 0 1 1 -. T%e OR gate B 0 1 0 1 X
"he !R gate is a little more complicated, and re6uires three gates as shown below,
A A B Q is the same as B Y A X A
A D
A D e6uivalent circuit,
&ntermediate !utputs
O#t+#t Q
"he !R gate is the inverse of the !R gate, so 5ust one more gate is needed as shown below,
X Z Q
A A B Q is the same as B
&ntermediate !utputs
57
Unit E1 : 0isc"vering E&ectr"nics C"nverting L"gic 0iagra(s t" N/N0 gates "he process for converting logic system diagrams into A D gate format is 6uite straight forward if you wor2 logic ally through the circuit, *ach gate is replaced in turn by its A D e6uivalent, and connected up in the same way, -e will loo2 at an e(ample to show how this is done, *(ample 1< 'onvert the following logic system into A D gates only,
A B C
%tage 1< Redraw the A D e6uivalent circuits of the gates shown above, where possible retain the position of these gates so that you can identify the connections afterwards,
A Q B C
Drawing a bo( around each gate and itCs corresponding A D e6uivalent will allow you to chec2 that you have replaced every gate in the circuit,
58
LOGIC CIRCUITS and SWITCHING THEORY %tage +< &t is then 5ust a matter of connecting the e6uivalent circuits together,
A Q B C
"his circuit is now the e6uivalent circuit to that using in !", !R and A D gate given earlier, however there is one further simplification we can ma2e, %tage E < 'onsider the circuit again as shown below,
A 1 2 A Q
B C
&f you loo2 carefully at the two A D gates labelled 1 H +, we can see that these are both configured to be inverters or !" gates, &f we consider what happens to signal A as it passes through these two gates we have the following< A logic 1 at A, becomes a 0 after gate 1 and then a 1 again after gate + A logic 0 at A, becomes a 1 after gate 1 and then a 0 again after gate + "herefore gates 1 and +, serve no useful purpose in this circuit, and are 2nown as redundant gates and can be removed, -e call this d"#b&e inversi"n and it occurs commonly when creating A D gate circuits from other logic systems, Remember a double inversion "n&5 occurs when + A D &nverters are direct&5 connected to one another,
59
Unit E1 : 0isc"vering E&ectr"nics &n an e(amination you are usually as2ed to cross out any redundant gates, so if this was an e(amination you would end up with the following circuit,
A Q B C
!ccasionally, you will be as2ed to redraw the circuit, with redundant gates removed in which case the final circuit would be as follows<
A Q B C
As has been the case with other e(amples we have ta2en our time with this one to illustrate each stage of the simplification process, )ost of these steps can be carried out in 5ust a couple of steps but there are a couple of things that will help to ensure that you donCt ma2e mista2es that in an e(amination could cost you a lot of mar2s, i, ii, iii, iv, identify each of the gates from the original circuit and their A D e6uivalent, connect each e6uivalent A D gate circuit as per the original diagram, identify and cross out and redundant gates caused by double inversions, d" n"t tr5 t" re("ve d"#b&e inversi"ns in 5"#r %ead; as 5"# can easi&5 )"rget 1%ic% "nes 5"# %ave d"ne and &eave s"(e "#t.
60
LOGIC CIRCUITS and SWITCHING THEORY *(ample + < 'onvert the following logic diagram into
A
A D gates only,
A B
B C
.irst of all we will replace all of these gates with their A D e6uivalent and connect them together, .inally we chec2 for any redundant gates, and identify these,
A
ote the way in which different pairs of redundant gates are mar2ed,
61
Unit E1 : 0isc"vering E&ectr"nics ow here are a couple for you to try, E*ercise B 1, /a1 Redraw the following logic circuit using + input
A B Q C
A D gates only,
/b1
62
LOGIC CIRCUITS and SWITCHING THEORY +, /a1 Redraw the following logic circuit using + input
A Q B
A D gates only,
/b1
63
Unit E1 : 0isc"vering E&ectr"nics 1. .2 3#&& U+ 4 3#&& 0"1n Resist"rs 8Hig%er Leve& T"+ic9
$p until now we have shown the input connections to a logic gate either as a wire with a label, or connected to a logic input<
A B Q
"hese diagrams are called schematic circuit diagram which help us to concentrate on what is happening to the logic signals 1it%in the logic circuit without worrying to much how the inputs are wired up, &f we want to build a logic circuit we have to provide the logic gate with a suitable input subLsystem to provide the correct logic levels, "he input to a logic gate can come from a number of different sources but for the purposes of this unit we are going to concentrate on mechanical switches, -hichever type of switch we use, they have to be used along with a series resistor as part of a voltage divider circuit, -e have to be careful which way around the resistor and switch are connected in the voltage divider circuit to produce either a 3ogic 0 signal or a 3ogic 1 signal when the switch is pressed,
64
LOGIC CIRCUITS and SWITCHING THEORY "wo input subLsystem circuits using a push to ma2e switch are shown below,
'ircuit A
'ircuit :
"he resistor used in 'ircuit A is called a +#&& #+ resistor and the resistor used in 'ircuit : is called a +#&& d"1n resistor, "his is because of their behavior in the circuit, either Ipulling upC the voltage at the input to 3ogic 1 or Ipulling downC the voltage to 3ogic 0 when the switch is not pressed, &n 'ircuit A, before the switch is pressed, there is no connection to the 00 line, and the input to the logic gate is IpulledLupC to D0, giving a 3ogic 1 input to the logic system, -hen the switch is operated, the input to the logic system is connected to the 00 line through the switch and the logic level falls to 3ogic 0, &n 'ircuit :, before the switch is pressed, there is no connection to the D0 line, and the input to the logic gate is IpulledLdownC to 00, giving a 3ogic 0 input to the logic system, -hen the switch is operated, current flows through the resistor, causing the voltage across it to rise to D0, changing the 3ogic level into the logic system to 3ogic 1, ow try these
65
Unit E1 : 0isc"vering E&ectr"nics E*ercise 1, %tudy the circuits below and complete the statements that follow<
a1 b1 c1 d1
&n circuit ' with the switch "+en the input to the logic system is at logic ?? &n circuit ' with the switch c&"sed the input to the logic system is at logic ?? &n circuit D with the switch "+en the input to the logic system is at logic ??? &n circuit D with the switch c&"sed the input to the logic system is at logic ??
+,
%tudy the circuit below and complete the statements that follow<
a1 b1 c1
66
Resistor R1 is a pull ??? resistor and R+ is a pull ??? resistor, -hen switch %-+ is pressed input : is at logic ,,,,,,, -hen both switches are pressed output ; is at logic ,,,,,,,
LOGIC CIRCUITS and SWITCHING THEORY N"n e*a(inab&e in)"r(ati"n ab"#t in+#ts t" &"gic gates 9ou might have as2ed yourself why canCt we simply connect input switches to a logic system as follows
"his is because with the switches open the inputs A and : are not connected to either 00 /logic 01 or D0 /logic 11, "his will cause the logic system to behave in an unpredictable way, Different families of logic circuits react to these incorrectly connected inputs in different ways, ""3 or AB(( series devices have a property whereby any unconnected input will assume a 3ogic 1, ')!% or B((( devices on the other hand behave very differently and any unconnected input will drift rapidly between logic 0 and logic 1, ma2ing it impossible for you to tell what logic level the input is actually at, :y using pull up and pull down resistors on all inputs, removes this possibility and should ensure that the logic circuit will behave as designed,
67
"he correct symbol for an A D gate is 0, "he correct symbol for a "he correct symbol for a "he correct symbol for a !" gate is /, !R gate is E, A D gate is ',
"he correct symbol for an !R gate is C, i, A D gate, In+#ts A 0 0 1 1 ii, !R gate, In+#ts A 0 0 1 1 B 0 1 0 1 O#t+#t Q 1 0 0 0 B 0 1 0 1 O#t+#t Q 0 0 0 1
+,
68
LOGIC CIRCUITS and SWITCHING THEORY iii, A D gate, In+#ts A 0 0 1 1 iv, !R gate, In+#ts A 0 0 1 1 E*ercise $ B 0 1 0 1 O#t+#t Q 0 1 1 1 B 0 1 0 1 O#t+#t Q 1 1 1 0
a1 b1 c1 d1 e1
69
Unit E1 : 0isc"vering E&ectr"nics S"&#ti"n t" 3r"b&e( "n 3age 1.: In+#ts B
0 0 1 1 0 0 1 1
A
0 0 0 0 1 1 1 1
C
0 1 0 1 0 1 0 1
F
1 1 0 0 1 1 0 0
O#t+#ts G
0 1 0 0 0 1 0 0
Q
1 0 1 1 0 0 0 0
E*ercise 1, In+#ts A
0 0 1 1
B
0 1 0 1
O#t+#ts K Q
1 0 0 0 0 1 1 1
+, A
0 0 0 0 1 1 1 1
In+#ts B
0 0 1 1 0 0 1 1
C
0 1 0 1 0 1 0 1
F
1 0 1 0 1 0 1 0
O#t+#ts G
1 0 1 1 1 0 1 1
Q
1 1 1 1 0 1 0 0
70
In+#ts B
0 0 1 1 0 0 1 1
C
0 1 0 1 0 1 0 1
D
1 1 1 1 0 0 0 0
E
1 0 1 0 1 0 1 0
O#t+#ts F
0 0 1 1 0 0 0 0
G
1 1 0 1 1 1 0 1
Q
1 1 1 1 1 1 0 1
71
Unit E1 : 0isc"vering E&ectr"nics E*ercise . 1, !utput ; is on when input A is high and input : is low, /i,e, ; M A A D !" :1 "he logic circuit re6uired is as follows<
+,
!utput ; is on when input A is low and input : is high or when input A is high and input : is low, /i,e, ; M P !" A A D :Q !R PA A D !" :Q1 "he logic circuit re6uired is as follows<
72
LOGIC CIRCUITS and SWITCHING THEORY E, /a1 /b1 /c1 /d1 # M &nverse of input A /or # M "he name of this gate is A D, RMA !R B, !" A1
B,
73
/ is correct for an A D gate, 0 is correct for a !" gate, ' is correct for a !R gate, E is correct for a A D gate, C is correct for an !R gate,
+,
9 M A.B VM
A.B
74
O/p 3 0 0 1 0
!/p + M A
!R B, or
A +B
!/p E M A A D
!" B, or
A.B
75
Unit E1 : 0isc"vering E&ectr"nics +, a1 'omplete the following truth table for the system, In+#ts A 0 0 1 1 b1 c1 d1 B 0 1 0 1 O#t+#ts ED !"##er 1 1 1 0 0 0 0 0
"he led output is the inverse of input A, :uzzer M A !R :, so a !R logic gate is re6uired,
E,
a1 In+#ts A 0 0 1 1 b1 c1 B 0 1 0 1 R 0 0 0 1 O#t+#ts Y 1 1 1 0
G 1 0 0 0
76
d1 e1
!r
77
78
LOGIC CIRCUITS and SWITCHING THEORY E*ercise < 1, +, E, B, D, G, A, 4, T, 10, 11, 1+, B, !R gates, A D gates, B, E, G, 4 and 11, AB0B, +, B00+ H B0A+ 1B, T, 10, 11 H 1+, A D gates, AB0+,
79
$.
A
E*ercise
a1 b1 c1 d1 &n circuit ' with the switch "+en the input to the logic system is at logic ?1? &n circuit ' with the switch c&"sed the input to the logic system is at logic ?0 &n circuit D with the switch "+en the input to the logic system is at logic ?0? &n circuit D with the switch c&"sed the input to the logic system is at logic ?1
+,
a1 b1 c1
Resistor R1 is a pull 0OWN resistor and R+ is a pull U3 resistor, -hen switch %-+ is pressed input : is at logic : -hen both switches are pressed output ; is at logic :
80
+o% +o%
an, -o$ic $ates are in t#is '(. an, in!uts does eac# $ate #a0e.
........................................... ...........................................
Pin 1 is -a/e--ed. )i* )ii* 1#at is t#e !in nu /er for t#e 02 !in. 1#at is t#e !in nu /er for t#e out!ut of $ate A. ........................................... ........................................... 344
2.
)a*
Logic Gate Name A56 $ate 5A56 $ate 57" $ate 57T $ate 7" $ate
334 81
)i*
)ii*
5a e t#e sin$-e -o$ic $ate %#ic# !roduces t#e sa e effect as t#is -o$ic s,ste . ........................................ 314
3. 82
An e-ectronic s,ste
#as t%o in!ut sensors A and B: and t#ree out!uts P: ; and ".
1#ic# of t#e fo--o%in$ e<!ressions correct-, descri/es t#e % out!ut. A Ans%er NO" A B NO" B 314
....................................
)/*
1#ic# of t#e fo--o%in$ e<!ressions correct-, descri/es t#e Q out!ut. A Ans%er NO" A B NO" B
.................................... 314 to s#o% #o% t#e & out!ut can /e o/tained usin$ a sin$-e
)c*
314
83
)a*
(o !-ete t#e fo--o%in$ trut# ta/-e for t#is s,ste . Input A Input B ! ! ! ! to s#o% #o% a 5A56 $ate can /e 324 ade to /e#a0e as a 57T $ Q
)/*
)i*
314 )ii* 6ra% a dia$ra to s#o% t#e 5A56 $ate e=ui0a-ent of an A56 $ate.
314 )iii* +ere is a -o$ic s,ste /ui-t usin$ on-, 5A56 $ates.
+o% +o%
an, -o$ic $ates are in t#is '(. an, in!uts does eac# $ate #a0e.
........................................... ...........................................
Pin 1 is -a/e--ed. )i* )ii* 1#at is t#e !in nu /er for t#e 02 !in. 1#at is t#e !in nu /er for t#e out!ut of $ate >. ........................................... ...........................................
)d*
(#oose t#e t,!e of -o$ic $ate found on t#is '( fro A56 7" 57T
5A56
Ans%er 8 ............................................... 6.
(o !-ete t#e state ents8 )a* )/* T#e si$na- at P %i-- /e -o$ic 0 on-, %#en in!ut A is -o$ic ....................... 314 7ut!ut ; %i-- /e -o$ic 1 on-, %#en t#e si$na- at P is -o$ic ......................: and in!ut B is -o$ic ...................... 314 85
)a* )/*
........................... 314
1#ic# s, /o-: ', (, $, ), or *: is t#e s, /o- for t#e -o$ic $ate %#ic# #as t#e fo--o%in$ trut# ta/-e. Input A Input B ! ! ! ! Q ! ! !
Ans%er 8 .................................... 314 )c* 1#ic# one of t#e fo--o%in$ -o$ic $ate s,ste s: &, S, ", or +: #as t#e sa e out!ut as an A56 $ate.
86
)a*
T#e s%itc# unit is used to ar )s%itc# on* t#e s,ste . 't out!uts -o$ic 1 %#en s%itc#ed on. T#e /u??er sounds %#en so eone stands on t#e !ressure !ad: /ut on-, of t#e s,ste is ar ed. T#e !ressure !ad out!uts -o$ic 1 %#en so eone stands on it. T#e transistor s%itc# needs a -o$ic 1 in!ut to a9e t#e /u??er sound. 1#ic# of t#e fo--o%in$ trut# ta/-es: (: 6: @: or A: $i0es t#e re=uired out!ut for -o$ic $ate >.
Ans%er 8 ................................ 314 )/* 1#at t,!e of -o$ic $ate is re=uired in /-oc9 >. (#oose ,our ans%er fro t#e fo--o%in$ -ist8 A56 $ate 5A56 $ate 57T $ate 7" Bate 314
Ans%er 8 ................................
87
88
B !
! ! ! 334 )/* "edra% t#e s,ste arran$e ent. re!-acin$ eac# of t#e t#ree $ates %it# its e=ui0a-ent 5A56 $ate
334
89
+o% +o%
an, -o$ic $ates are in t#is '(. an, in!uts does eac# $ate #a0e.
........................................... ...........................................
Pin 1 is -a/e--ed. )i* )ii* 1#at is t#e !in nu /er connected to 0V . 1#at is t#e nu /er of t#e !in -a/e--ed >. ........................................... ........................................... t#e fo--o%in$ -ist8 57" 354
)d*
(#oose t#e t,!e of -o$ic $ate found on t#is '( fro A56 7" 57T
5A56
Ans%er 8 ...............................................
90
)i*
)ii*
Ans%er 8 ............................................. 314 )/* T#e fo--o%in$ -o$ic s,ste $i0es t#e sa e out!ut as one of t#e -o$ic $ates in !art )a*.
)i*
(o !-ete t#e fo--o%in$ trut# ta/-e for t#is -o$ic s,ste . A B ! ! ! ! 324 $ Q
)ii*
1#ic# sin$-e -o$ic $ate $i0es t#e sa e out!ut as t#is s,ste . Ans%er 8 ........................................... 314
91
)a*
)i*
a/o0e.
324 )ii* 1#ic# sin$-e -o$ic $ate $i0es t#e sa e out!ut as t#is s,ste . Ans%er 8 .................................... 314 )iii* "edra% t#e s,ste s#o%in$ t#e 5A56 e=ui0a-ent of eac# $ate.
)i* )ii*
Si !-if, it /, crossin$ out an, redundant $ates. 324 Bi0e one reason %#, it is c#ea!er to con0ert a -o$ic s,ste e=ui0a-ent. into its 5A56 $ate
)a* )/*
1#ic# s, /o-: ', (, $, ) or *: is t#e s, /o- for a 57T $ate. (o !-ete t#e trut# ta/-e for t#e -o$ic $ate (. Input A Input B ! ! ! ! Q
........................... 314
314 )c* 1#ic# one of t#e fo--o%in$ -o$ic $ate s,ste s: %, Q, &, or S: #as t#e sa e out!ut as -o$ic $ate (.
93
+o% +o%
an, -o$ic $ates are in t#is '(. an, in!uts does eac# $ate #a0e.
........................................... ...........................................
Ca/e- Pin 1 of t#e '(. 1#at is t#e nu /er of t#e !in connected to t#e out!ut of $ate A. ...........................................
)e*
(#oose t#e t,!e of -o$ic $ate found on t#is '( fro A56 7" 57T
5A56
Ans%er 8 ...............................................
94
1#ic# of t#e $ates #as t#e fo--o%in$ s, /o-. Ans%er 8 .................................... 314
)ii*
Ans%er 8 ................................... 314 )ii* 1#ic# of t#e $ates #as t#e o!!osite effect to )in0erts* an 7" $ate. Ans%er 8 .................................... )/* (o !-ete t#e trut# ta/-e for t#e fo--o%in$ -o$ic s,ste 8
B !
! ! ! 324
95
B !
! ! ! 334 )/* )i* "edra% t#e s,ste arran$e ent. re!-acin$ eac# of t#e t#ree $ates %it# its e=ui0a-ent 5A56 $ate
96
1#ic# s, /o-: A, B, C, D or E: is t#e s, /o- for8 )i* )ii* )iii* )/* a 57T $ateD an 7" $ateD a 5A56 $ate. ........................................... ........................................... ........................................... 334 +ere are fi0e trut# ta/-es8
1#ic# ta/-e: A, B, C, D or E: is t#e trut# ta/-e for8 )i* )ii* )iii* a 57T $ateD an 7" $ateD a 5A56 $ate. ........................................... ........................................... ........................................... 334
97
B !
! ! )ii* !
5a e t#e sin$-e -o$ic $ate %#ic# !roduces t#e sa e effect as t#is -o$ic s,ste . ..................................................... 314
98
)ii*
A56
344 )/* (o !-ete t#e trut# ta/-e for t#e fo--o%in$ s,ste of -o$ic $ates.
B !
! ! ! 334
99
100
334 )/* T#e t#ree $ates are arran$ed in t#e fo--o%in$ -o$ic s,ste . (o !-ete t#e trut# ta/-e.
B !
&
! ! ! 334
101
314 )/* T#e 5A56 $ate is used a-on$ %it# a 57T $ate and an 7" $ate as !art of a -o$ic s,ste s#o%n /e-o%.
B !
Q,
! ! !
334
102
7ut!ut ; can /e o/tained /, in0ertin$ one in!ut. 1rite do%n t#e Boo-ean e<!ression for ; o/tained in t#is %a,. ; E ...................................................................... 314
)ii*
Fsin$ t#e trut# ta/-e %rite do%n t#e Boo-ean e<!ressions for out!uts P: and ". P E ...................................................................... " E ..................................................................... 324
)/*
324
103
334
104
+o% +o%
an, -o$ic $ates are in t#is '(. an, in!uts does eac# $ate #a0e.
1#ic# !in: A: B: C or D is Pin 1 of t#is '(. (#oose t#e t,!e of -o$ic $ate found on t#is '( fro A56 7" 57T
5A56
Ans%er 8 ...............................................
105
Learning Objectives
1. .1 ! Intr"d#cti"n. Recognise high/low, 1/0, as two state logic levels; 1. .$ ! Tr#t% Tab&es. Draw symbols and construct truth tables for A D, !R, !", !R, and A D gates; #roduce a truth table for a system of up to five gates; Devise a system of gates from a truth table; Design simple systems using logic gates to solve a given problem; Use '""&ean n"tati"n as a s%"rt%and (et%"d ") e*+ressing a tr#t% tab&e, 1. .- ! Use ") data s%eets. $se data sheets to; %elect a logic &' for given applications; &dentify pin connections of logic gates; 1. .. ! N/N0 gate i(+&e(entati"n. S%"1 %"1 "t%er gates can be (ade #+ )r"( N/N0 gates, I(+&e(ent a given &"gic circ#it #sing N/N0 gates, Re("ve d"#b&e inversi"ns, 1. .2 ! 3#&& #+4d"1n resist"rs. Rec"gnise t%e #se ") +#&& #+4d"1n resist"rs t" +r"vide t%e c"rrect &"gic &eve&s at a gate in+#t.
"argets<
1,
?????????????????????????????????????????? ??????????????????????????????????????????
+,
?????????????????????????????????????????? ??????????????????????????????????????????
106