Chapter 3

Combinational Logic Design

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3.1 Design Concepts and In Lab

Automation
n Logic Circuit for digital systems may be combinational circuit or sequential.

n A combinational circuit consists of logic gates whose outputs at any time are
determined by logic operations on the input values.

n Sequential circuits employ elements that store bit values.

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 In Lab
Design Hierarchy

n A circuit may be specified by a symbol showing its inputs and outputs and a
description defining exactly how it operates.

n A complex digital system may contain millions of interconnected gates (several

tens of millions in the case of VLSI).

n With such complexity, the interconnected gates appear to be like a maze.

n In order to deal with such complexity, the circuit is broken up into pieces that we
call blocks.

n The blocks are interconnected to form the circuit.

n This approach is a “divide an conquer” approach.

n This design approach is referred to as hierarchal design.

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In Lab
Hierarchical Design
n To control the complexity of the function mapping inputs to outputs:
n Decompose the function into smaller pieces called blocks
n Decompose each block’s function into smaller blocks,
repeating as necessary until all blocks are small enough
n Any block not decomposed is called a primitive block
n The collection of all blocks including the decomposed
ones is a hierarchy

n Example: 9-input parity tree (see next slide)

n Top Level: 9 inputs, one output
n 2nd Level: Four 3-bit odd parity trees in two levels
n 3rd Level: Two 2-bit exclusive-OR functions
n Primitives: Four 2- input NAND gates
n Design requires 4 X 2 X 4 = 32 2-input NAND gates

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Example of Design Hierarchy and In Lab

Reusable Blocks

Schematic
or
Logic Diagram

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Diagrams Representing the In Lab

Hierarchy

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 In Lab
Design Hierarchy

n A hierarchy reduces the complexity of required to

represent the schematic diagram of the circuit.

n A hierarchy ends at a set of leaves called primitive

blocks.

n With hierarchal design, reusability is one of the most

important properties.

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In Lab
Top-Down versus Bottom-Up
n A top-down design proceeds from an abstract, high-level
specification to a more and more detailed design by
decomposition and successive refinement

n A bottom-up design starts with detailed primitive blocks and

combines them into larger and more complex functional blocks

n Designs usually proceed from both directions simultaneously

n Top-down design answers: What are we building?
n Bottom-up design answers: How do we build it?

n Top-down controls complexity while bottom-up focuses on the

details

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 In Lab
Top-Down Design

n Ideally, the design process is performed top-down. This means

that the logic function is specified typically by text or a hardware
description language (HDL).

n At high levels of the design, the circuit is then repeatedly divided

into blocks as necessary until the blocks are small enough to
perform logic design.

n In order to obtain reusability and to make maximum use of

predefined modules, it is often necessary to perform portions of
the design bottom up.

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In Lab
Reusable Functions and CAD
n Whenever possible, we try to decompose a complex design into
common, reusable function blocks
n These blocks are
verified and well-documented
n
placed in libraries for future use
n
n Representative Computer-Aided Design Tools:
n Schematic Capture
n Logic Simulators
n Timing Verifiers
n Hardware Description Languages
n Verilog and VHDL
n Logic Synthesizers
n Integrated Circuit Layout

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 In Lab
Hardware Description Languages

n Hardware description languages resemble programming languages, but are

specifically oriented to describing hardware structures and behavior.

n They differ from typical programming languages in that they represent extensive
parallel operation whereas most programming languages represent serial
operation.

n HDLs provide an alternative to schematics.

n When a language is used in this fashion, it is referred to as a structural description

in which the language describes an interconnection of components.

n Such a structural description, referred to as a netlist, can be used as an input to

logic simulation just as a schematic is used.

n A major reason for the growth of the use of HDLs is logic synthesis.

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In Lab
Logic Synthesis

n Logic synthesis transforms an RTL description of a

circuit in an HDL into an optimized netlist representing
storage elements and combinational logic.

n This netlist may be transformed by using physical

design tools into an actual integrated circuit layout.
This layout serves as the basis for integrated circuit
manufacture.

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 High-Level Flow for Synthesis In Lab

Tool

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3.2 The Design Space In Lab

Gate Properties
n Digital circuits are constructed with integrated circuits (ICs).

n An IC is a semiconductor crystal, informally called a chip,

containing the electronic components for the digital gates and
storage elements.

n The various components are interconnected on the chip.

n The ship is mounted in a ceramic or plastic container, and

connections are welded from the chip to the external pins to
form the IC.

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 In Lab
Integrated Circuits
n Integrated circuit (informally, a “chip”) is a semiconductor
crystal (most often silicon) containing the electronic
components for the digital gates and storage elements
which are interconnected on the chip.

n Terminology - Levels of chip integration

n SSI (small-scale integrated) - fewer than 10 gates

n MSI (medium-scale integrated) - 10 to 100 gates

n LSI (large-scale integrated) - 100 to thousands of gates
n VLSI (very large-scale integrated) - thousands to 100s of
millions of gates
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In Lab
Circuit Technologies

n ICs are classified not only by their function, but also by their specific
implementation technology.

n Each technology has its own basic electronic device and circuit
structure.

n Currently, silicon-based Complementary Metal Oxide Semiconductor

(CMOS) technology dominates due to:
n its high circuit density,
n high performance,
n and low power consumption.

n Alternative technologies based on Gallium Arsenide (GaAs ) and Silicon

Germanium (SiGe) are used selectively for very high speed circuits.

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 In Lab
Technology Parameters
n Specific gate implementation technologies are characterized by the following
parameters:
n Fan-in specifies the number of inputs available on a gate.

n Fan-out specifies the number of standard loads driven by a gate output.

n Noise margin is the maximum external noise voltage superimposed on a normal

input value that will not cause an undesirable change in the circuit output.

n Cost for a gate specifies a measure of its contribution to the cost of the
integrated circuit containing it.

n Propagation delay is the time required for a change in value of a signal to

propagate from input to output. (Reading Assignment P98 – 101).

n Power dissipation is the power drawn from the power supply and consumed by
the gate. The power consumed is dissipated as heat, so the power dissipation
must be considered in relation to the operating temperature and cooling
requirements of the chip.

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Propagation Delay
n Propagation delay is the time for a change on an input of a gate to
propagate to the output.
n Delay is usually measured at the 50% point with respect to the H and L
output voltage levels.
n High-to-low (tPHL) and low-to-high (tPLH ) output signal changes may
have different propagation delays.
IN

tPH tPL
OUT
L H

tpd = max (t PHL, tPLH )

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 Delay Models
n Transport delay - a change in the output in response
to a change on the inputs occurs after a fixed
specified delay

n Inertial delay - similar to transport delay, except that if

the input changes such that the output is to change
twice in a time interval less than the rejection time,
the output changes do not occur. Models typical
electronic circuit behavior, namely, rejects narrow
“pulses” on the outputs

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Delay Model Example

A

B
A B:
No Delay
(ND) a b c d e
Transport
Delay (TD)

Inertial
Delay (ID)

0 2 4 6 8 10 12 14 16 Time (ns)
Propagation Delay = 2.0 ns Rejection Time = 1 .0 ns
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Cost
n In an integrated circuit:
n The cost of a gate is proportional to the chip area
occupied by the gate
n The gate area is roughly proportional to the number
and size of the transistors and the amount of wiring
connecting them
n Ignoring the wiring area, the gate area is roughly
proportional to the gate input count
n So gate input count is a rough measure of gate cost

n If the actual chip layout area occupied by the gate is

known, it is a far more accurate measure

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Positive and Negative Logic

Signal Logic Signal Logic
value value value value

H 1 H 0

L 0 L 1

Positive logic Negative logic

X Y Z
1 1 1
1 0 1
0 1 1
0 0 0
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 3.3 Design Procedure
n The design of a combinational circuit starts from the specification of the
problem and ends in a logic diagram or netlist that describes a logic
diagram. The procedure involves the following steps:
n Specification.
n Formulation.
n Optimization.
n Technology Mapping.
n Verification.
n The specification can take a variety of forms such as text or an HDL
description and should include the respective symbols or names for the
inputs and outputs.
n Formulation converts the specification into forms that can be optimized.
n Optimization can be performed by any of a number of available methods:
n Algebraic manipulation.
n K- maps.
n Computer-based simplification programs.

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Case-study I:
Seven-Segment Display

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 Truth Table for BCD–to–Seven-
Segment Decoder

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Case-study II:
BCD-to-Excess-3 Code Converter

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Maps for BCD-to-Excess-3 Code
Converter

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Logic Diagram of BCD-to-Excess-

3 Code Converter

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3.4 Technology Mapping
n Chip design styles
n Cells and cell libraries
n Mapping Techniques
n NAND gates
n NOR gates
n Multiple gate types
n Programmable logic devices
n The subject of Chapter 3 - Part 2

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Chip Design Styles

n Full custom - the entire design of the chip down to the smallest
detail of the layout is performed
Expensive
n
n Justifiable only for dense, fast chips with high sales volume
n Standard cell - blocks have been design ahead of time or as
part of previous designs
n Intermediate cost
n Less density and speed compared to full custom
n Gate array - regular patterns of gate transistors that can be used
in many designs built into chip - only the interconnections
between gates are specific to a design
n Lowest cost
n Less density compared to full custom and standard cell
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 Cell Libraries
n Cell - a pre-designed primitive block

n Cell library - a collection of cells available for design

using a particular implementation technology

n Cell characterization - a detailed specification of a

cell for use by a designer - often based on actual cell
design and fabrication and measured values

n Cells are used for gate array, standard cell, and in

some cases, full custom chip design
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Typical Cell Characterization Components

n Schematic or logic diagram

n Area of cell
n Often normalized to the area of a common, small cell such as an
inverter
n Input loading (in standard loads) presented to outputs driving each of
the inputs
n Delays from each input to each output
n One or more cell templates for technology mapping
n One or more hardware description language models
n If automatic layout is to be used:
n Physical layout of the cell circuit
n A floorplan layout providing the location of inputs, outputs, power
and ground connections on the cell
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Example Cell Library
Typical
Typical Input-to- Basic
Cell Cell Normalized Input Output Function
Name Schematic Area Load Delay Templates

0.04
Inverter 1.00 1.00
1 0.0123 SL

0.05
2NAND 1.25 1.00
1 0.0143 SL

0.06
2NOR 1.25 1.00
1 0.0183 SL

2-2 AOI 2.25 0.95 0.07

1 0.0193 SL

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Mapping to NAND gates

n Assumptions:
n Gate loading and delay are ignored
n Cell library contains an inverter and n-input NAND
gates, n = 2, 3, …
n An AND, OR, inverter schematic for the circuit is
available
n The mapping is accomplished by:
n Replacing AND and OR symbols,
n Pushing inverters through circuit fan-out points, and
n Canceling inverter pairs

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 NAND Mapping Algorithm
1. Replace ANDs and ORs: .
.
.
.
. .

. .
. .
. .

2. Repeat the following pair of actions until there is at

most one inverter between:
a. A circuit input or driving NAND gate output, and
b. The attached NAND gate inputs.

. .
. .
. .

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NAND Mapping Example

A A X
5
B B
6
Y OI
7 2
F 1
C C F
4
3
D D 8
9
E E
(a) (b)

A
B

X
5
C F
6
Y
5 7 D

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(c) (d)

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 3.5 Verification
n The goal of verification of circuit function (that is determination of
whether or not a given circuit implements its specified function).

n If the circuit doesn’t meet its specification, then it is incorrect.

n As a consequence, verification plays a vital role in preventing

incorrect circuit designs from being manufactured and used.

n In order to verify a combinational circuit, it is essential that the

specification be an ambiguous and correct.

n Simple specifications are:

n truth tables
n Boolean equations
n HDL code
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Basic Verification Methods

n Manual Logic Analysis
Find the truth table or Boolean equations for the final circuit
n
n Compare the final circuit truth table with the specified truth
table, or
n Show that the Boolean equations for the final circuit are
equal to the specified Boolean equations
n Simulation
n Simulate the final circuit (or its netlist, possibly written as an
HDL) and the specified truth table, equations, or HDL
description using test input values that fully validate
correctness.
n The obvious test for a combinational circuit is application of
all possible “care” input combinations from the specification

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Schematic for Simulation of a
Binary Adder

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Waveforms for the Binary Adder

Schematic

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 Verification Example: Simulation

n Enter BCD-to-Excess-3 Code Converter Circuit Schematic

A
INV W
NAND2
NAND2

INV
NOR2

B
INV
NAND2 X
NAND2
C
INV
NAND3

D
INV AND2
Y
NOR2
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AND2 AOI

Verification Example: Simulation

n Enter waveform that applies all possible input combinations:

INPUTS
A
B
C
D

0 50 ns 100 ns

n Are all BCD input combinations present? (Low is a 0 and high is a

one)

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 3.6 Why Programmable Logic?
n Facts:
n It is most economical to produce an IC in large volumes
n Many designs required only small volumes of ICs

n Need an IC that can be:

n Produced in large volumes
n Handle many designs required in small volumes

n A programmable logic part can be:

n made in large volumes
n programmed to implement large numbers of different
low-volume designs
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Programmable Logic - Additional

Advantages
n Many programmable logic devices are field- programmable, i. e.,
can be programmed outside of the manufacturing environment

n Most programmable logic devices are erasable and

reprogrammable.
n Allows “updating” a device or correction of errors
n Allows reuse the device for a different design - the ultimate
in re-usability!
n Ideal for course laboratories

n Programmable logic devices can be used to prototype design that

will be implemented for sale in regular ICs.
n Complete Intel Pentium designs were actually prototype
with specialized systems based on large numbers of VLSI
programmable devices!
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Programming Technologies
n Programming technologies are used to:
n Control connections
n Build lookup tables
n Control transistor switching

n The technologies
n Control connections
n Mask programming
n Fuse
n Antifuse
n Single-bit storage element
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Programming Technologies
n The technologies (continued)
n Build lookup tables
n Storage elements (as in a memory)
n Transistor Switching Control
n Stored charge on a floating transistor gate
§ Erasable
§ Electrically erasable
§ Flash (as in Flash Memory)
n Storage elements (as in a memory)

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 Technology Characteristics
n Permanent - Cannot be erased and reprogrammed
n Mask programming
n Fuse
n Antifuse

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Technology Characteristics
n Reprogrammable
n Volatile - Programming lost if chip power lost
n Single-bit storage element
n Non-Volatile
n Erasable
n Electrically erasable
n Flash (as in Flash Memory)
n Build lookup tables
n Storage elements (as in a memory)
n Transistor Switching Control
n Stored charge on a floating transistor gate
§ Erasable
§ Electrically erasable
§ Flash (as in Flash Memory)
n Storage elements (as in a memory)

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 Programmable Configurations
n Read Only Memory (ROM) - a fixed array of AND gates and a
programmable array of OR gates

n Programmable Array Logic (PAL) - a programmable array of AND

gates feeding a fixed array of OR gates.

n Programmable Logic Array (PLA) - a programmable array of AND

gates feeding a programmable array of OR gates.

n Complex Programmable Logic Device (CPLD) /Field-

Programmable Gate Array (FPGA) - complex enough to be called
“architectures” - See VLSI Programmable Logic Devices reading
supplement

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PAL is a registered trademark of Lattice Semiconductor Corp.

Read-Only Memory

n A read-only memory (ROM) is essentially a device in which ‘’permanent’’ binary

information is stored.

n The information must be specified by the designer and is then embedded in to the
ROM to form the required interconnection or electronic device pattern.

n One the pattern is established, it stays within the ROM even when power is turned
off and on again; ROM is nonvolatile.

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 Read-Only Memory

n Four technologies are used for ROM programming.

n If mask programming is used, then the ROM is called simply a

ROM.

n If fuses are used, the ROM can be programmed by the user, in this
case the ROM is referred to as a programmable ROM or PROM.

n If the ROM uses the erasable floating-gate technology, then the

ROM is referred to as erasable, programmable ROM or EPROM.

n If the electrically erasable technology is used, the ROM is referred

to as electrically erasable programmable ROM, or EEPROM.

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Programmable Logic Array

n The programmable logic array (PLA) is similar in concept to the

PROM, except the PLA does not provide full decoding of the
variables and does not generate all the minterms.

n The decoder is replaced by an array of AND gates that can be

programmed to generate product terms of the input variables.

n The product terms are then electively connected to OR gates to

provide the sum of the products for the required Boolean
functions.

F1 = AB + AC + ABC
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Programmable Logic Array

F1 = AB + AC + ABC
F2 = AC + BC
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Programmable Logic Array

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 Programmable Array Logic Devices

n Programmable array logic (PAL) is a PLD with a fixed OR

array and a programmable AND array. Because only the
AND gates are programmable, the PAL device is easier
to program than, but is not as flexible as, the PLA.

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F1 = AB + AC + ABC
F2 = AC + BC = AB + C

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ROM, PAL and PLA Configurations

Fixed Programmable
Inputs Programmable Outputs
AND array
(decoder)
Connections OR array

(a) Programmable read-only memory (PROM)

Programmable Programmable Fixed

Inputs Outputs
Connections AND array OR array

(b) Programmable array logic (PAL) device

Programmable Programmable Programmable Programmable

Inputs Outputs
Connections AND array Connections OR array

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(c) Programmable logic array (PLA) device

Problems
n 3.1, 3.9, 3.10, 3.11, 3.12, 3.15, 3.17, 3.19,
3.22, 3.23, 3.26.

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