2456 [31 E. J. Boleky, %ubnanosecond SOS silicon-gate technology, [41 switching delays using CMOS/ in 1971 Int.

Solid-State Circuit Conj., Dig. Tech. Papers, p. 225, E. J. Boleliy and J. E. Meyer, High-performance low-power CMOS memories using silicon-on-sapphire technology, IEEE J. Solid-State Circuits (Special Issue on Micropower Electronics), vol. SC-7, pp. 135-145, Apr. 1972. R. W. Bower, H. G. Dill, K. G. Aubuchon, and S. A. Thompson, [MOS field effect transistors by gate masked ion implantation, IEEE !trams. Electron Devices, vol. ED-15, pp. 757-761, Oct. 1968. J. Tihanyi, Complementary ESFI MOS devices with gate self adjustment by ion implantation, in Proc. 5,th Iwt. Conj. Microelectronics in Munich, Nov. 2729, 1972. MunchenWien, Germany: R. Oldenbourg Verlag, pp. 437447. E. J. Boleky, The performance of complementary MOS transistors on insulating substrates, RCA Rev., vol. 80, pp.
372-395, 1970.

IEEE JOURN.4L OF SOLID-ST.iTE CIRCUITS, VOL.

SC-9,

NO.

5>

OCTOBER 1974

[51

[61

Kapazitat auf Source und Drain im Ersatzschaltbild eines und Ent wicldwrgsMOS-Transistors, Siemenx Forxchungsberichte 1, no. 3$ pp. X4-286, 1972. [121 J. R. Burns, Switching response of complementary+symmetry MOS transistors logic circuits, RCA Rev., vol. 25, pp. 627481, 1964. [131 R. w. Ahrons and P. D. Gardner, [Introduction of technology and performance in complementary symmetry circuits, IEEE J. Solid-State Circuits (Special Issue on Technology jor Integrated-Circuit Design), vol. SC-5, pp. 2429, Feb. 1970. [141 F. F. Fang and H. Rupprecht, High performance MOS integrated circuits using ion implantation technique, presented at the 1973 ESSDERC, Munich, Germany,

[71

formation in an insulated gate field [81 K. Goser, [Channel effect transistor ( IGFET) and its emrivalent circuit . Sienzen.s Forschungsund Entwiclclungsbekhte, no. 1, pp. 3-9, 1971. Accurate metallization [91 A. E. Ruehli and P, A. Brennan, capacitances for integrated circuits and packages, IEEE J. Solid-State Circwits (Corresp.), vol. SC-8, pp. 289-290, Aug. 1973. (Siemens Netzwerk Analyse Programm Paket), [101 SINAP Siemens AG, Munich, Germany. [Aufteilung der Gate-Kanal[111 K, Goser and K. Steinhubl,

Michael Pomper, 238 of this issue.

for a photograph

and biography,

please see p.

Jeno Tlhanyi, for 238 of this issue.

a photograph

and

biogra~hy,

please

see p.

Design

of Ion-Implanted Small Physical

H. BASSOUS,

MOSFETS Dimensions
HWA-NIEN YU,

with

Very
ROBERT H. DENNARD, RIDEOUT,

LIEMBER, IEEE, FRITZ

GAENSSLEN, AND ANDRE

MEMBER, IEEE, V. LEO MEMBER, IEEE

MEMBER) IEEE, ERNEST

R. LEBLANC,

AbsfracfThis paper considers the design, fabrication, and characterization of very small MOSI?ET switching devices suitable for digital integrated circuits using dimensions of the order of 1 p. Scaling relationships are presented which show how a conventional MOSFET can be reduced in size. An improved small device structure is presented that uses ion implantation to provide shallow source and drain regions and a nonuniform substrate doping profile. One-dimensional models are used to predict the substrate doping profile and the corresponding threshold voltage versus source voltage characteristic. A two-dimensional current transport model is used to predict the relative degree of short-channel effects for different device parameter combinations. Polysilicon-gate MOSFETS with channel lengths as short as 0.5 ~ were fabricated, and the device characteristics measured and compared with predicted values. The performance improvement expected from using these very small devices in highly miniaturized integrated circuits is projected.

LIST

OF SYMBOLS

Inverse

semilogarithmic

slope of subprogate and

D AW,

threshold characteristic. Width of idealized step function fde for chaDnel implant. Work function difference for between silicon and substrate. Dielectric constants silicon dioxide. Drain current. Boltzmanns Unitless MOSFET Effective Intrinsic constant. constant. scaling

channel length. surface mobility. carrier concentration.

Manuscript received May 20, 1974; revised July 3, 1974. The aubhors are with the IBM T. J. Watson Research Center, Yorktown Heights, N.Y. 10598.

Substrate acceptor concentration. Band bending in silicon at the onset of strong voltage. inversion for zero substrate

DENN.4m

et al. : ION-IMPLANTED

MOSFETS

257

*,
(1

Built-in Charge Effective Absolute

junction

potential.

GATE ~

tox=loooh +
=. _-

GATE
:N+ ___,

&*200A
~N+o .___,

on the electron. oxide charge. temperature. volt-

Q.,,
t ox

Gate oxide thickness.

T Vd, v,, v.,

+ --0 Ll a

1, /l /L\
5P

-OILhp

VaubDrain,
Source Source

source, gate and substrate relative relative voltage. drain depletion width. to source.

N~=25x106/cm

Vd. V,-.b v, w.,Wd w

ages. Drain voltage voltage and Gate threshold widths. MOSFET

NA=5 x 105/cm3

to substrate. layer

(a)

(b)

Fig. 1. Illustration of device scaling principles with K = 5. (a) Conventional commercially available device structure. (b) Scaled-down device structure.

channel

relatively
INTRODUCTION EW N over monly new widely while ing Full tion new can the HIGH resolution semiconductor a decrease contact the in lithographic integrated linewidth of approach industry pattern device [5] exhibited the benefits and optical techniques circuit five to which today. writing fabrication projection has patterns ten times is comOf the been for

lightly reduces

doped

starting

substrate,

this

channel voltage bias. which of very favormaingives a thicker threshreduced or draina

implant This

the sensitivity

of the threshold (backdate) can then thickness

to changes in the source-to-substrate reduced substrate sensitivity off for a thicker Second, shallow able taining of these switching with ion gate insulator

forming offer optical in

be traded

of 350-A reproducibly the which

masking

tends to be easier to fabricate implantation source and drain respect features an acceptable in device which

and reliably. are more while

used techniques, used X-ray [6] have

semiconductor beam

allows regions

formation effects, The

electron for experimental

[1] [4] print-

to short-channel an

lithography also of

sheet resistance. all-implanted can be fabricated

combination

high-resolution of requires these the and new

capability. high-resoluof which

design with

realization lithographic device be

techniques designs, for concerns of very

development structures

gate insulator interelectrode

if desired, which has well-controlled and which has significantly capacitances capacitances). begins by describing to a conventional structure verification device the scaling MOSFET of the (e.g., drain-to-gate

technologies, very the small integrated is known the small design, MOSFET

old characteristics, to-substrate This which a very paper small

optimized paper

dimensions. fabrication, switching using reducing length) device when and drain and chardevices dimensions the of sourcean FET

This acterization suitable of the

principles to obtain perapscaling

for order

digital of

circuits that

are applied

1 p. It (i.e.,

capable

of improved

to-drain leads These regions large the to

spacing undesirable changes surrounding portion of

channel in the

formance.

Experimental

changes become the the region For

characteristics. the extend substrate the in on, been by depletion over under most the a

significant source in

proach is then presented. Next, the fabrication process for an improved scaled-down device structure using ion implantation is described. Design considerations for this all-implanted a simple strate structure are based on two analytical model that predicts that devices, tools: the suband a predicts of chanare to two-dione-dimensional

the

silicon

gate

electrode.

switching effect at which drain effects the

applications, is a reduction turns has

undesirable gate is that down ess, threshold

short-channel voltage by high

sensitivity

for long channel-length current-transport characteristics results experimental the model from

device It

which shown scaling thickn-

two-dimensional the device turn-on nel length, compared mensional ;vith

aggravated these the

voltages. can (e.g., along

as a function both Using of data. the the

short-channel vertical

be avoided gate with insulator the

The predicted simulation,

analyses design

dimensions depth, etc. ) also

junction

horizontal the

sensitivity

dimensions, applied

while

proportionately

decreasing

voltages

and increasing

the substrate

doping

con-

Yarious parameters is shown. Then, detailed attention is design, intendedfor zero substrate givcll to all alternate
bins, which offers some advantages with respect to thresh-

[7], [8]. Applying this scaling approach to a centration properly designed conventional-size MOSFET shows that

old control. sion of the

Finally,

the paper that

concludes

with to

a discusFETs.

a 200-A

gate insulator

is required

if the channel

length

performance circuits

improvements

be expected small

is to be reduced to 1 ~. A major consideration the use of ion implantation for very small centration scaled-down atoms of ion implantation of doping of this paper is to show how leads to an improved design MOSFETS. allows First, the ability a low condoping

from integrated

use these very

SCALING scaling design [7], trends the [8] to

DEVICE The concise in principles manner the switching n-channel of the device general and devices. lllOSFET

show be

in

to accurately

introduce

followed of

the substrate

dccreming

size

increasing Fig. [9]

performance a state-ofscaled-down

profile in the channel creased in a controlled

region under the gate to be inmanner. When combined with a

lIOSFET the-art

1 compares with a

258 clevice be 1 (a) vices niques. substrate clesignecl following The typical by using the larger device scaling principles shown in to Fig. detechwith a

IEEE

JOURFJ.iL

OF SOLIC)-STATE

CIRCUITS,

OCTOBER

1974

described

later.

structure

p-type substrates) the work function difference A~Vf is of opposite sign, ancl approximately cancels out *,J. ~. is the band bencling tial) bias. It would and (2) prevent mately increased constant, in the silicon that (i.e., the surface appearing potenin (1) approxi). at the onset of strong appear exact scaling actually inversion the * terms increasing = for zero substrate

is reasonably fahricatecl It uses doping

of commercially conventional insulator

a~ailable diffusion thickness

a 1OOO-A gate

ancl substrate voltage

bias

chosen doping

to

give

since they rcxnain slightly (2kT/q)

gate threshold

I:r of approximately A substrate

2 V relative of 5 X 105 value of subis an imporemploying difficult a factor design if of pa-

due to the h] (.V./n,

to the source potential. cm-3 is low enough strate tant source sensitivity. criterion followers in

eloping since ~0 @ *,

to give an acceptable sensitivity digital switching the design

The substrate because

However, the fixed substrate bias supply normally used with n-channel devices can be adjusted so that (~,, + V,,,,; ) = plied (~,, + substrate V,,,,,) /K. Thus, by scaling clown the apbias more than the other applied voltages, across the source region that under or drain junctions, the gate, can be reclevice by

circuits becomes

thethreshold For the

voltage

increases

by more than 1 (a), the

the potential CIUCeC{ by

K.

drop

two o~er the full range of variation clevice limit illustrated the channel in Fig. length from rameters restriction depletion normally mum tration In
values three all

of the source voltage.

or across the depletion All of the equations characteristics example, the MOSFET

L to about, 5 p. This
the penetration of the

clescribe the MOSFET equation

vd/~

arises primarily

may be scaled as demonstrated current

~7t K

above. For given

region surrounding the clrain into the area controlled by the gate electrode. For a maxiof approximately the surface potential voltage. suitable
and by a

[9]

ch-ain voltage will order

of

12-15 V this peneand significantly for

doping. unitless

~ ,_
d

P,,,e.. tOx/K-

modify

()(
w/K V,

L/ii

)
of
K,

(Vet/K)

Id/K

(3) set

lower the threshold

is seen to be reduced smaller

in First, scaling

by a, factor assuming is reduced in the heavier patterns and

for any given in

to clesigl~ a new device

L, the device is
dimension, are &K, clirnensions t,ox =

of

applied

voltages, the mobility scattering

no

change

mobility.

scaled

by

a transformation

Actually, impurity clude electric

slightly

clue to increased approach clensity. in the to inThe scaled-

variables: linear

voltage, reduced

doped substrate. current

It is possible electric field

to generalize field distribution

the scaling

faCtOr

K, e.g.,

where

the primed device, This

parameters reduction thickdi-

refer

to

the

new

scaled-down

il~cludes vertical ness, junction mensions ages applied

dimensions depth, length Third, agnin The

such as gate insulator as the horizontal and width. the substrate using

is maintained

etc., as well

of channel

Second, the voltby the same factor doping concenfactor 1 (b) was

clown device except for a change in scale for the spatial coordinates. Furthermore, the electric field strength at any corresponding Thus, effects point is un?hanged velocity and, hence, in both any fixed because

to the device are reduced

V/c

=
ve-

V/x.
locity

the carrier will From

at any point devices,

is also unneglecting lattice width IV is reduced the same

(e.g., V~S = Vd,,/K). tration is increased, (i.e., Na obtained reduction = ~Na).

K =

the same scaling in Fig.

changed

due to scaling cliff erences channel

saturation crystal

clesign shown

be similar

using

5 which

corresponds were developed

to the desired by observing

microscopic dimensions, by
K, the

due to the per unit

in channel

length to 1 p,.

(3), since the clevice current current of channel with This is consistent

The scaling

relationships

that the depletion layer widths in the scaled-down device arc reducecl in proportion to the device climensions due to the reducecl potentials ancl the increased doping. For example,
w, = {[2cs,(V~ +

is unchanged

by scaling,

sheet density of carriers (i.e., electrons per unit gate area) moving at the same velocity. In the vicinity of the clrain, the carriers extent Thus, will move away of mobile from carriers the surface per unit around to a lesser cliffusions. volume the will drain, in the new device, the clensity due to the shallower region

V,-,,,JK)l/CIKN. at turn-on [9]

}2 m w,/Ic.

(1)

The

threshold

voltage

is also decreased

bc higher

in the space-charge

in clirect pro~ortion that the clcvicc will reducecl voltage

V, =

to the reduced device voltages so function properly in a circuit with This is shown by the threshold device.
+ Vs-s,,,/K)]}

complementing the higher density clue to the heavier doped substrate, tionships in Table on circuit

of immobile charge Other scaling rela-

voltage equation

levels.

for the scaled-down

+ + [~~,,~K~a(+s

for power density, delay time, etc., are given I ancl will be discussed in a subsequent section performance. the scaling relationships, two sets of

(tO=/KCOf) { Q,.,,

In order to verify experimental

(~)

(AJVf

~.)

V,/K.

In

(2)

the reduction insulator and doping

in Tt is primarily
tOx/K,

due to the dethe changes in

devices were fabricated with gate insulators o of 1000 ancl 200 A (i. e., K = 5). The measured drain voltage characteristics of these devices, normalized to W/L = 1,
are quite of the shown similar smaller the in Fig. when ~ 9. The tin-o with sets voltage by of characteristics and current of 2, five, the are scales which exact plotted

creased

thickness,

while

the voltage opposite

terms tend to cancel out, In most gates of doping or aluminum type gates on

cases of interest to that

(i.e., polysilicon of the substrate

clevice scaling

reduced predictions.

a factor In Fig.

confirms

DENNARD et at. : ION-IMPbiNTED

MOSFETS

259
1,5~ GATEVOLTAGE [V] 20

tox =100ox
10L *w=5p v~ub=-?v 0.5+= sO.65V

Q 0

5 5 10 15 20

DRAINVOLTAGE[V]

(a)
0.3 GATE VOLTAGE[v]

0.2

3 .

0 IF

+ ~

o 0

DRAIN VOLTAGE[v] (b) Fig.

Expcrimentzd drain voltage characteristics ventional, and (b) scaled-down structures shown malized to W/L = 1.
2.

for (a) conin Fig. 1 nor-

3.5

drain
tox ds

voltage

is large exhibit

enough the

to cause pinchoff linear

and the

charact cristics
3.0 2.5 fid
2,o

expected

relationship,

=10001! =5V

When linear

proj ccted to intcrccpt the gate voltage axis this relationship defines a threshold voltage useful for design purposes.

VSu~=-7V 1#, =0,65V

most logic circuit

[#A] 2,,5

Onc area in which the dcvicc characteristics fail to scale is in the subthrcshold pr weak inversion region of the turn-on characteristic. on V, with B@ow threshold, an inverse 1,, is exponentially slopc, by device is given dependent scmilogarithrnic

1.0 0.5

a, [10], [11] which ,

( 4 .8 1,2 1.6 GATE VOLTAGE[V]

for the scaled-down flv,

volts

a ()dccadc

= d log,, 1,,

Fig. 3. Experimental turn-on characteristics for conventional and scaled-down devices shown in Fig. 1 normalized to W/L

= 1.

which

is the same as for the original

larger

clcvice.

The

match since tude istics with shows for

on there of the (see larger an

the

current

scale

is

thought uncertainty to normalize

to

be

fortuitous magni-

lJaramctcr ~ is important to dynamic memory circuits because it determines the gate voltage excursion rcq~lired to go froln tile low Current off state to the high current (on state ( 11]. In an attempt in (4)
increase thereby (3). In

is some channel Appendix). width approximate with voltage

experimental length used L1orc and Icngth reduction the also heavier scales 3, which

in the the from the

to also extend
~/K), effective

the linear
cause

characterdcviccs same chip

scaling

relationships

to ~ one could (i.e., T =

in the invalidate

reduce the operating

accurate dimensions of ten doped correctly SIIOJVS

data on pcrccnt substrate. by tllc for the cases

temperature
<% significant, [ 12] and of

but this
surface

lT70uld

mobility rclationat fact

in mobility That a factor the of

the design

current devices one does must not

scaling for

dcviccs

shi~) room that This istic

order and

to

operation the,

threshold five ~~ and is

temperature the subthreshold

above, behavior of the to

accept scale

verified versus

in ~T.

Fig. turn-on

cxpcrirncntal the original the

as desired. character-

characteristics devices. For

nonscaling is of particular

property concern

subthreshold Ininiaturc

the

scaled-down

Shon-nj

dynamic

menl-

260

IEEE

JOURNAL

OF SOLID-STATE

CIRCUITS,

OCTOBER

1974

t~*

under drain

the gate electrode are then inhibited

at the edges of the source by the heavier doped

and

surface

layer, roughly pictured in Fig. turned-off device. The depletion and

(a)
would would

4(b), for the case of a regions under the source into the lighter
material in the

drain
tend cause

extend With
to merge

much
in

further
the lighter

doped regions
which extreme,

substrate.

deeper junctions
of threshold high give drain a more effects chosen

these depletion
doped or, control

a loss at

punchthrough lower junctions which

voltages. favorable when (i.e.,

However, electric the substrate

the field

shalpatdoping

tern

avoids

these

V,,,=

-Iv

concentration

is properly

when it is not too with the ion-imlayer selfthe also

light), The planted width [cf.

(b)

device

capacitances

are reduced increased

structure separating 4(a) the reduced

due to the

depletion

the source and drain

from the substrate process which gate the over

Figs.

and 4(b) ], and due to the natural by the ion implantation of the polysilicon but regions. gate The thicker

alignment

afforded

)
Fig.

p-Si 7.5x lo15cnl-3

.
-... -.. .-. . . . . . . . . . . . . . . .1( .. . . . . . .

reduces gives benefit threshold voltage Fig. 4(b),

overlap

source and drain

gate insulator

capacitance,

performance gate field, drain in device

in this respect is offset by the decreased for the thicker increase, a design objective

To compensate

gate oxide and the expected for maximum design

1
4. Detailed ture, and (b)

,y~~=-lv

was set at 4 V for the ion-implanted compared

cross sections for (a) scaled-down device struccorresponding ion-implanted device structure.

to 3 V for the sc-sled-down

of Fig. 4(a).
FABRICATION OF ION-IMPLANTED MOS~ETs

ory

circuits

which

require

low

source-to-drain

leakage

currents. ION-IMPLANTED The 4 (a). utilizing shown initial scaling In considerations with the The DEVICE DESIGN just presented length lead to the shown in Fig. design is uses an a factor

The FETs mask devices Though

fabrication used in this process with was

process study used on

for the will to

ion-implanted

MOSA fourcontains pattern

now be described. fabricate chip ranging which

polysilicon-gate, from 0.5 to 10 p.

n-channel

MOSFETs channel the eventual

a test

device structure the in Fig. substrate

a l-,P channel corresponding afforded that

lengths

contrast, 4 (b).

improved device by about

aim is to use electron-beam

capability doping

by ion implantation

ion-implanted is lower

exposure, it was more convenient to use contact masking with high quality master masks for process development. which starting oxide For are this purpose in high the resolution uses lines subsequent was is required as small processing. (i.e., only The about for the gate pattern reduced substrate isolation which resistivity The method between suitable as 1.5 p

of four, and an implanted boron surface layer having a coneentration somewhat greater than the concentration used throughout the unimplanted structure of Fig. 4(a). The concentration and the depth of the implanted surface layer will are chosen so that within is turned the this heavier doped region layer be completely surface depletion

2 CI. cm

7.5 x 1015cm-).

of fabrication FETs presented gate oxide,

for the thick is not described here, and beFollowenergy low

adj scent techniques of the

as it is not essential cause several ing dry (40 keV), implanted the silicon thermal

to the work

when the device

on with

the source grounded.

are available.

Thus, when the source is biased above ground potential, the depletion layer will extend deeper into the lighter doped substrate, and the additional exposed bulk charge will be reasonably small and will cause only a modest increase in the gate-to-source voltage required to turn on the device. With this improvement thickness maintain in substrate gate sensitivity the gate insulator and still can be increased a reasonable

growth

B ions were low dose (6.7 x 101 atoms/cmz) into the wafers, raising the boron doping near surface. All implantations in order were performed diffusion thick of to restrict a 3500-A drain

after gate oxide growth the implanted regions. After silicon the channel Next,

implantation, and

poly 2000-A

to as much as 350A

layer was deposited,

doped n, and the gate regions regions (100 keV), high dose the the

threshold voltage as will be shown later. Another aspect of the design philosophy low implanted n+ regions surface of depth layer. The implanted p-type

delineated. is to use shalto the regions (4

x

n source As

deep were formed same 350-A oxide

by a high energy layer. During

comparable depletion

105 atoms/cm)

implantation this

through

step, however,

DENNARD

ei!

al.:

ION-IMPLANTED

MOSS13Ts

261
V,(fo, vw~=-l) [v] z:~

6-

,,-., _ :\

ORIGINAL IMPLANT

t5 mE ~ ~

l!i !

\, i

Ns ; ~
: ; \\ 1 ;, ; 0 ., ~ \l ... +IOEALIZED STEP FUNCTION AFTER ANNEALING

e -i ~
X3 -/ Z* / 2+ # 4 I-

_ tdb

Fig. 5. Predicted substrate doping profile for basic ion-implanted device design for 40 keV BI1 ions implanted through the 350-A gate insulator.

Fig. 6. Calculated and experimental substrate sensitivity characteristics for non-implanted devices with 200- and 350-A gate insulators, and for corresponding ion-implanted device with 350-A gate insulator.

polysilicon plant, etching sloping

gate masks

the channel

region

from

the imThe in a

ing, the boron

is redistributed

as shown profiles

by the heavier using

absorbing process sidewall

all of the As used to delineate which allows

dose incident

there.

dashed line. These predicted

were obtained

the gates results penetration

a slight

of ASP5

a computer program developed by F. F. Morehead of our laboratories. The program assumes that boron atoms diffusing face and modeling in the silicon thereby purposes reflect from the silicon-oxide the surface concentration. to use a simple, of the doping profile profiles rather shown interFor idealprofile, apand 5 well raise

ions underneath (or source) implantations 1000C, implanted for polysilicon sulating contact fined, Electrical which implantation the source oxide

the edges of the gates, The gate-to-drain is estimated 20 min without to be of the order of 0.2 steps that and follow 11 min the at at 900C, adequate greatly processing

overlap

p, The high temperature include damage

it is convenient representation

ized, step-function proximates offers simple the

is more than

to anneal spreading

out the out the for the

as shown by the solid line in Fig. 5. The step profile final predicted that The three the advantage parameters. it can be described

doses. Typical and drain layer areas. Following

sheet resistances regions, thick

were 50 O/D a final Then, inthe

by a few in Fig. threshsolutions condionly in

and 40 fI/D was deposited deposition. regions shallow

the AS5 implant,

all have the same active dose. Using the step profile, old voltage of Poissons tions the vertical short-channel Fig. 6 which equation dimension plots a model for determining from piecewise boundary considers has been developed with one-dimensional and cannot

2000-A

using

low-temperature

chemical-vapor

holes to the n+ and polysilicon and the metalization contact directly regions the final to avoid was applied to the

were deimplanted due to metalizain forming

appropriate model

and delineated. by a suitably

[11 ], The

account voltage

for horizontal are shown versus source-

source and drain chosen metallurgy alloying tion during an annealing

was accomplished junction annealing

effects. Results

of the model

penetration step. After

the threshold

step of 400 C for 20 min to decrease the fast-state

(LONG profile CHANNEL) for incident the active

to-substrate bias for the ion-implanted step profile shown in Fig. 5. For comparison, Fig. 6 also shows the substrate sensitivity with doping, and characteristics gate insulator for like for the nonimplanted having and device a 350-A a constructure. a 200-A and a constant device structure background

gas was performed

ONE-DIMENSIONAL The substrate

density.
ANALYSIS 6.7 350-A X 101 gate 3 persilicon time GausiV~.

a hypothetical the implanted doping

doping

the 40 keV, on oxide dose the

gate insulator stant background

atoms/cm~ oxide, cent is 6.5 of the sian For of x

channel

implant

like the nonimplanted

is shown the

in Fig.

5. Since the The by

absorbs in the at the dashed

incident

dose,

The nonirnplanted 200-A case exhibits a low substrate sensitivity, but the magnitude of the threshold voltage is also low. On the other hand, the nonimplanted 350-A case shows a higher threshold, but with an undesirably high substrate sensitivity. The ion-implanted case offers both a sufficiently high threshold voltage and a reason-

10~1 atoms/cm2. added B ions, taken to the the

concentration the lightly range 500 doping

implantation function

is given

background projected A and

level,

40 keV

and

standard process-

deviation [ 131. After

were

as 1300 treatments

i%, respectively

the heat

of the subsequent

> ably low substrate sensitivity, particularly for V~.S,,I~ 1 V. For Vs..,,,,, < 1 V, a steep slope occurs because the

262

IEEE

JOURNAL

OF SOLID-STATE

CIRCUITS,

OCTOBER

1974

surface
not

inversion
~, the

layer
step

in the channel silicon

of the width >

is obtained the
heavier doped

while
im~

,~-5 CALCULATED, L= 0,8/L 10-6 1,2+ lop

the depletion
exceed planted region.

region For

in the
V,.,u,b

under

gate does the deplesubstrate slowly bias of is

,~-lo If 0.0 0,2

1 V, at inversion
the lighter a fixed doped

-m
~U K K ~ g a K n

H
10-7

Vd K4V v,u~=-IV
T-

,+/ //
+// /rf +//

,+ //
+/

,+f //

tion with

region V..,,,,,

now extends voltage Thus, [11],

into with

and thethreshold

then increases

relatively substrate

10-s I ~ ,8(3 ~vfie~Qd~ 10-9 y{~,~l

+1 /

i ;1

1 V, the substrate of the source voltage reasonably implanted allows 200-A

sensitivity similar

over the operating potential

range

(e.g., ground However, for the

to 4 V)

low and very design. higher

to the slope of the nonthe threshold design worst reduce still under which will voltage which case. the implanted so that, effects

/-EXPERIMENTAL, L=9,75p h86p J.17Y I

0.4 0.6 0.8 I ,0

1.2

.1.4

GATE VOLTAGE , Vg (V)

is significantly adequate conditions threshold conduction plications. Experimental measurements 10 ,p) which agree this 35 keV, 6 result, of 40 kel
x

design margin

Fig. 7. Calucu!at.ed
acteristic for basic lengths with V,u, z

(e.g., short-channel considerably), level

the threshold for also

be high ap-

and experimental subthreshold turn-on charion-implanted design for various channel 1 V, V. z 4 V.

enough so that the device can be turned as required results have are

off to a negligible memory Fig.

r
1 i i , 1 I 1 1

dynamic given in

6 from (i.e., L = data A

made on relatively no short-channel well than

x

long devices effects. calculated higher the

These

reasonably rather and 6,7

with

curve. design

101 atoms/cm2

implant

was used to achieve value

the slightly

1011 atoms/cm2.
(SHORT CHANNEL) ANALYSIS

TWO-DIMENSIONAL

For devices with one-dimensional threshold drain by the which uniform field voltage into the for gate. account doping While

sufficiently lowering channel this

short-channel due to

lengths,

the

model

is inadequate region

to account penetration normally have [14], been the

for the of the

I_J???5
12345678 SOURCE-DRAIN SPACING, L (MICRONS) 910

controlled developed problem is field

some models behavior which

Fig. 8. Experimental and calculated dependence voltage on channel length for basic ion-implanted V,.b = 1 v, v. = 4 v.

of threshold design with

complicated

for the ion-implanted profile

structure leads to

by the nonidentified jected acteristics from threshold were Fig. 3 as the V*. in the actual When manner current the of at

an electric

the

prochargave

pattern that is difficult to approximate. For implanted case, the two-dimensional numerical transport utilized. Chang strate The calculate model The doping of Kennedy and Mock was [15], modified the computer profiles program considered behavior

the ioncurrent [16] by was W. sub-

voltage, plotted

computed Fig. 3 they

4 X 10-8 A at threshold for all device lengths. The band bending, +,, at this threshold condition is approximately

and P. IIwang numerical current

[171 to handle transport. computation

abrupt

0.75 V. Some of the other heavier threshold,

in all cases

device

designs considered gave a higher

of in 10-7 A was

with at
used

for these devices. model was used to decurof the ion-implanted of the device

substrate

concentrations

current

so, for simplicity,

with a resultant

the value
small error

the turn-on

vice by a point-by-point

Vt,
were measmodel. the chanin the Apin Fig. 7 curves, in

rent Ior increasing values of gate voltage. Calculated results are shown in Fig. 7 for two values of channel longlength in the range of 1 p., as well as for a relatively
channel device with L =

MOSFETS The technique nel length pendix. and especially Another

Fig.

with

various

channel

lengths

lu-ed to test the predictions for very good form short

of the two-dimensional determining is described are plotted the calculated data different is plotted voltage devices results with

for experimentally experimental agreement

10 ,fl. All

cases were normalized and a drain channel voltage length is

to a width-to-length rcdllccd shifts threshold to the to a lower voltage. order

ratio

of unity,

Ike

of 4 V was used in all

cases. As the

show

of 1 p, the turn-on voltage

characteristic of the a transi(a linear

Id m also Vqz be

considering

the somewhat voltage

values of L. is shown as a funcis essen-

gate voltage The threshold

due to a lowering make

of presentation the threshold length. for

L >

of this threshold from

occurs at about

8 where constant amount

10-7 A where

the turn-on

characteristics

tion tially small

of channel

The

tion from the exponential subthreshold behavior response on this semilogarithmic plot) to the
square-law behavior. This current level can

2 p, and falls with further

by a reasonably 2 to 1 p, and then in L, For

as L is decreased

dccrca.ses more rapidly

reductions

DENNARD et

al.:

ION-IMPLANTED MoSF@i3
9 y_?-.~ BASIC DESIGN (a) ] 7.5E15 L=o.8p N+ laop lo2p 10p vd=+4v CALCULATED THRESHOLD VOLTAGE [ VOLTS ) FOR Ids = 10-7 AMPERES

263

J v,~ ~ Vm
?
DEEPER SOURCE/ORAIN JUNCTIONS ~+ ---N+

Fig.

9.

Experimental design tracer voltage with (U

drain

voltage load

characteristics

for

basic voltage

ion12.2 ~, 4

(b)
P

implanted Curve V, gate

Vs.~ =

1 V, L = resistance each

1.1 p, and

W =

xj=o.4p

parameters;

.30 Q, drain

V in 8 steps

0.5 V apart.

circuit

applications greater

the nominal than

value

of L could over voltage

be set

somewhat

1 ,P so that,

an expected is reason0.3 pwould to this shortfor many of different characterchansource is the No exdrain imin Figs.
Fig. 10. Threshold voltage calculated using two-dimensional rent transport model for various parameter conditions. band voltage of 1.1 V is assumed, curA flat-

range of deviation ably well controlled. give V~ = l. O& channel circuit devices ofL istics effect

of L, the threshold Forexample, This would indeed MOSFET O.l Vfromchip

L = 1.3 * tochipdue be tolerable this

alone.

applications on a given can be achieved.

because of the tracking chip,if The experimental in Fig. drain with

degree of control a I.I-,P

for an ion-implanted are shown The general short-channel taken energy from

nel length condition. traneous voltages 6-9 were plantation atoms/cm2,

9 for the grounded larger devices. for data

shape of the characteristics for much effects devices were using observed a B

same as those observed

:TRATE @vm
Su

as large as 4 V. The experimental and dose of 35 keV simulations 10 which

channel

and 6.0 X 101

respectively. were also used to test parameters. values representalength The of for the tabulates of the design to various in Fig. Fig. as a function considering is about more pared calculated that. the boron effects dose implanted would With occur. in the silicon that the comhave However, thresholds bias and still a grounded

The two-dimensional the sensitivity results threshold indicated are given voltage voltages.

20 percent values

less in this case, it was expected show almost identical

of channel

short-channel

10(a) is an idealized

tion for the basic design that The first perturbation in junction preciable device (from reduction would

has been discussed thus far. to give an apfor the shorter by 20 percent comparable of the from to the shallower

to the basic design. sensitivity depleted

the shallower

implanta-

to the basic design was an increase in threshold Viewed voltage

tion it is possible good substrate is completely with show about design. a heavier

to use zero substrate at turn-on with

depth to 0.4 ,P. This was found another

since the heavier considers

doped region source.

devices in Fig. 10(b). length

way, the minimum

The last design perturbation concentration [Fig. nel threshold threshold

such a cascj again for this case In L = fact, the 0.8 p. is due

to give the same long-chaneffect. with

have to be increased a threshold the value puts

10 (e) 1. The calculations less short-channel case for a device

1.0 to 1.2 p) to obtain design. This in perspective. lighter for by

appreciably for this This with layer

the basic junctions strate higher

Another a factor

perturbation of 2, with layer device to [Fig.

the same as for an L = 1.0 ,p. device important depletion improvement layer widths around

of the basic the source the is

where

basic design which doping concentration

was considered in the

was the use of a suba slightly give the 1O(C) ]. to the

is apparently

to the reduced and drain tions.

much onlY

surface

the lower voltage these bias depth in the

particularly

drop across those j uncconditions, the

source

same threshold The results

a long-channel devices proved

Also,
less

with

and doping silicon

near

for smaller

to be similar

depletion

under
the

gate

case of deeper j unc~ions. The next possible departure from the basic design is the use of a shallower boron implantation in the channel region, to only give half the as deep, wiih long-channel profile, and a heavier threshold concentration [Fig. same

at threshold,

the band bending, which from may the drain

+$, appears into this

across this where

depletion of field the device

region, lines turn-on

help prevent

the penetration region

10(d) ]. With

the shallower

is controlled.

264

IEEEJouRNALoF soLm-STATE CIRCUITS,

OCTOBER 1974

1.2 ~ Lo -1 0 ~ 0.8

i
k

1
**

,<p:*-- * 2

% a i ~ 0,6.+ f o 1 >
2 0.4 g g 0,2 I 11 0.0 01234
Fig. 11.

20 KeV,6Ellcm2 + Vd = 0,05 VOLTS (EXI?)

G Vd =4 VOLTS (EXH A Vd =4 VOLTS (THEORY) I I I I I 678910 L?(p)

Experimental on channel

and length

calculated for

dependence zero

of

threshold bias

voltage design.

ion-implanted

substrate

CHARACTERISTICS OF THE ZERO SUBSTRATE BIAS DESIGN Since the last be better worthwhile mental 20 keV, obtain and tested behaved devices with 6.0 x design shown in Fig. 10(e) appears effects, fully. In this were to it is built case a

rl

in terms

of short-channel more to this Bll design

to review

its properties channel

Experi-

corresponding various 10 [11]. atoms/cm2 implanted Data very

lengths. implant of layer

was used to approximately for these in Fig. values. channel voltage

a shallower

~,o, o

1OOO-A depth devices with Data length,

on threshold to the drain well to the

voltage is presented calculated with

Vsource -substrate (VOLTS )

4 V applied drain

11 and corresponds for a small much showing

Fig. 12. Substrate sensitivity characteristics for ion-implanted zero substrate bias design with channel length as parameter.

voltage

is also given in this figure, of threshold design version, old offers improved threshold For control such for strong inthe 13 is its agis of threshold voltage

less variation

as expected.

The dependence

this advantage with

is offset by the flatter characteristic is turned elevated Thus, =

subthreshof Fig.

on source-to-substrate ent values a constant show that

bias is shown in Fig. 12 for differwas held at

turn-on suitable

characteristic. the turn-on Furthermore, [18]. V@ with if the device

applications off by bringing temperature earlier

of L, The drain-to-source

noise margin barely gravates the basic preferred,

low value for this measurement. The results the substrate sensitivity is indeed about the

gate to ground. design

same for this design with zero substrate bias as for the original design with V.u~ = 1 V. Note that the smaller devices values design, show a somewhat with relatively (and drain) characteristics experimental different values flatter lower voltage. for the zero substrate and calculated, of L. The relatively bias in small are shown substrate thresholds sensitivity at high characteristic The turn-on both I?ig. 13 for

the situation

for dynamic

memo~,

1 V presented

of source

CIRCUIT PERFORMANCE WITH SCALED-DOWN DEVICES The very performance small improvement in expected from of using com-

MOSFETS

integrated

circuits

shift in threshold for the short-channel devices is evident; however, the turn-on rate is considerably slower for this case than for the V,ub = 1 V case shown in Fig. 7. This is due to the fact that the depletion region in the silicon under the gate is very shallow for this zero substrate bias case so that a large portion of a given gate voltage change is dropped across the gate insulator capacitance rather than across the silicon depletion layer capacitance. This is discussed in some detail for these devices in another apbias paper [11 ]. The consequence for dynamic memory plications is that, even though the zero substrate

parably small dimensions is discussed in this section. First, the performance changes due to size reduction alone are obtained from the scaling considerations given earlier. The influence on the circuit performance due to the structural changes of the ion-implanted design is then discussed. Table I lists the changes in integrated circuit performance which follow from scaling the circuit dimensions, voltages, and substrate doping in the same manner as the device changes described with respect to Fig. 1. These changes are indicated in terms of the dimensionless scal-

DENNASD et at.: 10N-1MH,.4NTED iWOSFETS

,.-5 , , cm-z
/ . W%~~ENTAL ,0-8 /. +

265
TABLE SCALING RESULTS II LINES Factor
K K

20 KeV,6EII
]o-6 . V,=4V
v$,~=o ,0-7

FOR INTERCONNECTION Scaling

Parameter Line Line Line resistance, R~ = pL/Wt IR~/V

Normalized L=l.lp . ~ & 10-9

,0-10 ~.li)o(

voltage

drop

L=lOp

response time R~C current density I/A

1
K

.
*) A .

and reduced

depletion are driven giving

layer by the

widths. transition

These times

reduced device with

caa re-

;
o

,[
0.2 0.4

CTvj
0.6 .0.8 vg [v]

pacitances ances V/I

unchanged

resist-

decreased

sultant reduction factor of K. The so the power-delay area of a given the power more density circuits

in the delay time of each circuit by a power dissipation of each circuit is reand current by
K8.

1.0

1.2

1.4

duced by K due to the reduced voltage product device remains problem in Table
K2

levels, by K2, circuit arise

K.

is improved constant, on a given is essentially

Since the

Fig.

13. Calculated acteristics for

and experimental subthreshold turn-on charion-implanted zero substrate bias design.

or circuit

is also reduced Thus, integrated unchanged. of problems

even if many

are placed

chip, the cooling

TABLE SCALING RESULTS Device Device Doping Voltage Current or Circuit dlmensiontO., concentration V 1 I PERFORMANCE Scaling 1/.
K

As indicated from is decreased by

II,

a number

FOR CIRCUIT

the fact that

the cross-sectional while the length along resolution for the thicknesses with

area of conductors of the conductors widths because (e.g.j down on to for solid limit with the is K voltto remain becomes

Parameter L, W Na

Factor

is decreased only by the

It is assumed here that are necessarily of the more etching, constant very small comparable degenerately volubility ing factor would It K. Justifying
so

reduced stringent

1/. 1/.
l/K

requirements is considered metal films

etc. ). The which

conductivity (until

Capacitance EA It Delay time/circuit Power Power

is reasonable

VC/Z VI

dissipation/circnit density VI/A

1/. 1 /K2
1

dimensions doped and

the mean free path lines these

to the thickness), impurity of a given

K.

and is also reasonable where considerations directly

semiconducting scattering Under

these results only a. simplified voltages

here in great treatment are reduced voltage

detail in the supply levels levels divider An are be at

any

increase factor (with greater

in conductivity. The IR the drop

assumptions

be tedious, that

is given.

the resistance scaling constant times line

line increases current

is argued

all nodal

in such a line is therefore levels) ~ but operating time

miniaturized voltages. in digital consisting ance either lower

circuits MC)SFET

in proportion circuits level

to the reduced the supply a voltage by

decreased

This follows

because the quiescent are either given by

in comparison

to the lower limited by its

ages. The response time is characteristically

of an unterminated

transmission constant

or some intermediate

of two or more devices, and because the resistof each device is unchanged by scaling, threshold scaling. elements which will properly voltage is made that parasitic or unchanged because subsequently. resistance operate

V/I

R~C, which is unchanged by scaling; however, this makes it difficult to take advantage of the higher switching speeds inherent in the scaled-down devices when signaI propagation over long lines is involved, Also, the current density which MOSFET latively widths of in a scaled-down causes minor, micron a reliability but in high buses and they circuits, conductor concern, become The is increased In problems significant problems circuits by
K,

assumption examined

negligible voltages

The circuits the device

Vt

conventional are refor may linebe

scales as shown in (2), and furthermore because the reduced tolerance spreads on Vt should be proportionately as well if each parameter percentage accuracy. the same time ages are reduced internally in (2) is controlled margins signal generated to the same but at voltNoise are reduced, noise coupling voltage swings,

these conductivity dimensions. performance by avoiding

circumvented the power

by widening

the use of n+ doped considered

improvement

by the lower

lines for signal propagation. Use of the

paper will give

Due to the reduction in dimensions, all circuit elements (i.e., interconnection lines as well as devices) will have their capacitances reduced by a factor of K. This occurs because of the reduction ponents, which is partially by
K

ion-implanted
similar

devices

performance

in this to that

by K in the area of these comcancelled by the decrease insulating in due to thinner films

of the scaled-down device with K = 5 given in Table I. For the implanted dcviccs with the higher operating voltages (4 V instead (0.9 V instead of 3 V) and higher threshold level will voltages be reduced of 0.4 V), the current

the electrode

spacing

266

IEEEJOURNAL OFSOLID-STATE CIRCUrrS, OCTOBER 1974 to (Vg Tt) /tox to about 80 percent of the
12 II 109 8~ 47 /! + +/ / L= Lma~k-AL 20 KeV,6EII Cniz Vg=Vt+ 0.5 VOLTS V,j =0.05 VOLTS v~ub=f) +/ +/: I
I 1 J

in proportion current per circuit capacitances planted

in the scaled-down ate about

device. The power dissipation a factor of two less in the lines will substrate lines overall would imshow dopelebe less

is thus about the same in both cases. All device devices, and n+ interconnection due to the lighter depth. interconnection so that circuit the would junction

the same improvement ing ancl dec~:ased ments such essentially improvement than a factor is proportional micron as metal unchanged in a typical

Some capacitance

capacitance

be somewhat

of two. The delay time per circuit which to VC/I thus appears to be about the and for the directly scaled-down

z x6 z z & 54-

same for the implanted

devices shown in Fig. 4, 3/

NJMMARY

1 / / /1 ,f/,!,!I AL=0.86P

2fabrication, switching to by and de00 highly high-reFig. 14. Illustration

This vices. solution pattern

paper These

has considered of very integrated considerations

the design, MOSFET are

I-

characterization miniaturized writing.

small circuits

applicable fabricated such

2
Lmosk (})

lithographic that

techniques

as electron-beam relationships device can approach requirements

A consistent

set of scaling this direct technological

of experimental channel length,

technique L.

used

to determine

were presented be reduced leads to some

show how a conventional scaling

in size; however, challenging structure

such as very thin an all ion-implanted these difficulties formance. modified particularly A for

gate insulators. without

It was then shown how can bc used to overcome device area. or permodel proved degree of current transport structures the relative

on the observation

that

WR.w

LP.m

(Al)

sacrificing ion-implanted

two-dimensional use with valuable

where li,(.~~~ 1s the channel resistance, and pCl,~~the sheet resistance of the channel. For a fixed value of V~ Vt >

in predicting

0, and with
region, pendent intercept sion the

the device channel

turned

on in the below-pinchoff is relatively inde-

short-channel effects rameter combinations. was to design with lower a l-P circuits channel

arising from different The general objective polysilicon-gate for high-density length

device paof the study MOSFET source-folmemories. turnwas

sheet

resistance

an n-channel

versus L~,,k will of L. Then, a plot of w&han t,he Lm.,ll axis at AL because AL = L~.~~ L, reduction etching. in the mask dimenAn example of this and values as follows.

where AL is the processing due to exposure is illustrated technique

such as those used in dynamic combination control, and substrate lMOSFET B channel As an applied bias that

The most satisfactory on range, threshold

of subthreshold sensitivity

in Fig. 14. of W and l?,,,. First, used in Fig. the sheet resistance

The experimental 14 were obtained

achieved by an experimental keV, 6,0 x 10 atoms/cm keV, 350-A tended from from the using 4 x 105 atoms/cm and presented of view ~gate insulator, for

that used a 35 implant, a 100 implant, bias attractive but suffers Finally from of design a of in-

source/drain

of the icm-implanted n+ region was determined using a relatively large four-point probe structure. Knowing the n+ sheet resistance drain resistance resistance allows us to compute the source and the resist-

substrate is more control

1 V. Also

was an ion-implanted of threshold improvement in

R. and R., and to deduce W from

n+ line. The channel from

zero substrate

of a long, slender,

the point sizable very

ance can be calculated

an increased small small

subthreshold MOSFET)S dimensions

turn-on

range. expected

R,,hnn= VC,,J1,

= (V, I,(R,

+ R. + 2Rc + R1omi))/Id,
(A2)

performance

integrated

circuits

comparably

was projected.

where Rc is the contact

resistance

of the source or drain,

APPENDIX EXPERIMENTAL DETERMINATION OF GHANNEL LENGTH

and Rla,,l is the load resistance of the measurement circuit. Id was determined at VO = Vt + 0.5 V with a small applied drain voltage of 50 or 100 mV. The procedure is more simple and accurate if one uses a set of MOSFETS having different values of L~.,~ but all with the same value
L.,..],

technique length

for

determining small

the

effective

electrical from exis based

channel. perimental

L for very

MOSFETS

of W,nnsl,.Then

one needs only to AL.

plot

Rchan

versus

data is described

here. The technique

in cwder to determine

DENNARD et U1. : ION-IMPL.4NTED MOSFETS ACKNOWLEDGMENT We wish to acknowledge the valuable contributions of the Also J. J. pre. at the
advanced datz Robert Terrell, H. Dennard (M65) was Tex., in 1932. He received

267 born in the B.S.

B. L. Crowder and F. F. ?vIorehead who provided ion implantations and related design information. important Chang Walker paration to were the contributions two-dimensional and testing Research device assisted The and V. DiLonardo of l?. Hwang computations. with the mask facility devices

and M .S. degrees in electrical engineering from ,Southern Methodist University, Dallas, Tex., in 1954 and 1956, respectively, and the Ph.D. degree from Carnegie Institute of Technology, Pittsburgh, Pa., in 1958. In 1958 he joined the IBM Research Division where his experience included study of new devices and circuits for logic and memory communication applications, techniques. and devclo~ment of Since 1963 he has been

and W.

activities. center.

were fabri-

cated by the staff of the silicon T. J. Watson

technology

RE~EREN-CES [11
F. Fung, M. Hatzakis, and C, H. Tingj Electron-beam cation of ion implanted high-performance FET J. Vat. Sci. Technol., vol. 10, p. 1082, 1973. J. M. Pankrantz, gain, low-noise lithography, in Dec. [31 fabricircuits, highbeam

at the IBM T. J. Watson Research Center, Yorktown Heights, N. Y., where he worked with a group exploring large-scale integration (LSI), while making contributions in cost and yield models, MOSFET device and integrated circuit design, and FET memory cells and organizations. Since 1971 he has been manager of a group which is exploring high density digital integrated circuits using advanced technology concepts such as electron beam ~attcrn exposure.

[2]

H. T. Yuan, and L. T. Creagh, A transistor fabricated with electron Dig. Int. Electron Devices

Tech. 1973, pp. 44-46.

Meeting,

H, N. Yu, R. H. Dennard, T. H. P. Chang, .kn experimental high-density memory with electron beam, in IAWCC Dig. inn . . !wwl R. C. Henderson, R. F. W. Pease, Tech. A. M,

and M. Hatzakis, array fabricated Papers, Feb, 1973,

.i

[41

Voshchenkow, p-channel electron Meeting,

P. ranlithoDec.

Fritz

H,

Gaensslen

was born

in Tuebingen,

Mallcry, and R. L. Wadsack, [A high speed dom access 1024-bit memory made with graphy, in Tech. Dig. Int. Electron Devices 1973, pp. 138-140. [51

Germany, on October 4, 1931, He received the Dipl. Ing and Dr. Ing. degrees in electrical engineering from the Technical University of Munich, Munich, 1959 and 1966, respectively. Prior to 1966 he served fessor in the Department gineering, Munich,
u.~

Germany,

in Pro. En-

D. L. ~pears and H. I. Smith, X-Ray lithographya new high resolution replication process, Solid State Tech.nol., vol. ~:~ 15, p. 21, 1972. Projection effects, masking, IBM thin photoresist vol. layers 14, p. N. Yu, at the D. C., inn~fereuce J. Res. Develop.,

as Assistant of Electrical

[61 S. Middlehoek,

Technical Germany.

University of Munich, During this period he

[71

R. H. D&nard, F, H, Gaensslen, Design of micron MOS switching IEEE Int, Dec. 1972. Electron Devices

L. Kuhn, devices,

and H. presented

Meeting,

Washington,

[81

A. N. Broers and R. H. Dennard, Impact technology on silicon device fabrication, (Electrochem. Sot. Publication), gess, eds., pp. 830-841, 1973. D. L. Critchlow, R. H, Dennard, characteristics sisters, IBM H. and

of electron beam Semicond, Silicon and R. R. BurDesign tran. compleIEEE J. 1972. {Device MOS-

was working on the synthesis of linear and the IBM T. J. Watson Re. ~i~ital networks. In 1966 he joined search Center, Yorktown Heights, N,Y., where he is currently a member of a semiconductor device and process design group. His current technical interests involve various aspects of advanced integrated circuits like miniaturization, device simulation, and ion implantation, assignment at the Dr. Gaensslcn Sclmft. From IBM Scptcmbcr Laboratory, of the 1973 he was on a. one Boeblingen, Germany, Nachrichtentechnische year

R. Huff

is a member

Gesell-

[91

S. E. Schuster,

of n-channel insulated-gate field-effect J. Res. Develop., vol. 17, p. 430, 1973.

[101

R. M. Swanson and J. D. Meindl, Ion-implanted mentary MOS transistors in low-voltage circuits, Solid-State Circuits, V. L. Rideout, F, design FETs, H. vol. SC-7, pp. 146-153, April Gaensslen, and A. LeBlanc, for ion Develop., implanted n-channel to be published. Ph~s. Rev.
vol.

[111

considerations IBM J. Res.

[121

F. F. Fang and trons in inverted 1968,

A. B. Fowler, Transport
Si surfaces,

properties of

elec169, p. 619,

Hwa-Nien

Yu

(M6,5)

was born

in Shanghai,

[131 [141

W. S. Johnson, IBM System Products Division, E. Fishkill, N. Y., private communication. H, S. Lee, An analysis of the threshold voltage for short channel IGFETs, Soiid-State Electron., 1973. D. P. Kennedy and P. C. Murley, Steady cal theory for the insulated gate field IBi14 J. Res. Develop,, vol. 17, p. 1, 1973. vol. state effect 16, p. 1407,

China, on January 17, 1929. He received the B. S., M.S,, and Ph,D, degrees in electrical engineering from the University of Illinois, Urbana, in 1953, 1954, and 1958, respectively. While at the University, he was a Research Assistant in the Digital Computer Laboratory and worked on the design of the Illiac-11 computer, Since joining the IBM Research Laboratory in 1957, he has been engaged in various exploratory solid-state device research activities. After working with the Advanced Systems Development Division from 1959 to 1962, he rejoined the Research Division in 1962 to work on the ultra-high speed germenium dcvicc technology. Since 1967, he has been engaged in advanced silicon LSI device technology research. He is currently the Manager of Semiconductor Technology at the IBM T. J. Watson Research Center, Yorktown Heights, N.Y. Dr. Yu is a member of Sigma Xi.

[151

mathematitransistor,

[161

[171 [181

M. S. Mock, A two-dimensional mathematical model of the insulated-gate field-effect transistor, Solid-State Electron., vol. 16, p, 601, 1973. Division, W. Chang and P. Hwang, IBM System Products Essex Junction, Vt,, private communication. R. R. Troutman, Subthreshold design considerations for insulated gate field-effect transistors, IEEE J. Solid-State Circuits, vol. SC-9, p. 55, April 1974.

268 V. N.J. gree Leo Rideout (S61M65) received the in 1963 from was born in

IEEE

JOURNAL OF SOLID-STATE CIRCUITS, OCTOBER 1974

1959 where he worked for 1 year on infra

in 1941. He with honors

B.S.E.E. dethe Univer-

sity of Wisconsin, Madison, the M.S.E.E. degree in 1964 from Stanford University, Stanford, Calif., and the Ph.D. degree in materials science in 1970 from the University of Southern California (U.S.C.), Los Angeles. His thesis work at U.S.C. under Prof. C. R. Crowell concerned thermally assisted cide Schottky barriers, of current transport in platinum silion semiconductors. ently the the Mr. engaged fabrication Bassous American in of

red detectors at the Centre National dEtudes des Telecommunications, Issy-lesMoulineaux, Seine. From 1960 to 1964 he worked at the Thomas Laboratory in West A. Edison Research Orange, N.J., where

his activities included studies in arc discharge phenomena, ultra violet absorption spectroscopy, and organic semiconductors, In 1964 he joined the IBM Research Laboratory, Yorktown Heights, N.Y., to work As a member of the Research staff he is presthe study of of for materials the and processes used in and silicon integrated the circuits. Electrochemical Advancement of Society Science.

From 1963 to 1965 he was a member of the technical staff Bell Telephone Laboratories where he worked on high-frequency germanium transistors on potassium tantalate. and metal-semiconductor Schottky barriers In 1966 he spent a year as a Research

is a member Association

Assistant in the department of Materials Science at the Technological University of Eindhoven, Eindhoven, The Netherlands, studying acoustoelectric effects in cadmium sulphide. In 1970 he joined IBM Research in the device research group of Dr. L. Esaki where he worked on fabrication and contact technology for multiheterojunction superlattice structures using gallium-arsenidephosphide and gallium-aluminum-arsenide. Since 1972 he has been a member of the semiconductor device and circuit design group of Dr. R. Dennard at the IBM T. J. Watson Research Center, Yorktown Heights, N.Y, His present research interests concern high density silicon FET technology. He is the author or co-author Tau of 20 technical Dr. Rideout Beta Pi, Eta papers and 3 U.S. Patents.

Andre

R. LeBlanc

(M74)

received

the

B.S.

degree in electrical engineering, and the M.S. degree in physics from the University of Vermont, Burlington, in 1956 and 1959, respectively, and trical engineering New Prior Mexico, to joining the D. SC. degree in from the University in 1962. Junction, IBM, Essex elecof

Albuquerque,

is a member of the Electrochemical Society, Kappa Nu, Phi Kappa Phi, and Sigma Xi.

Vt., in 1957, he was an electrical engineer

affiliated with G.E. as and also with Sandia

Ernest Bassous was born in Alexandria, 1931. He received the B. SC. degree in versity of London, degree in physical Brooklyn, Brooklyn, From British 1954 Boys to School, Londonj chemistry N.Y. in he England from the 1965. Egypt.

Egypt, chemistry

on

September 1, from the Uniand the Institute MS. of the in

in 1953, Polytechnic and He went

Cor~oration in conjunction with the University of New Mexico. in 1959 he took an educational leave of absence to complete his doctorate. He is presently a member of the Exploratory Memory Group at the IBM Laborato~, Essex Junction, where his current technical interest includes a study of short-channel MOSFET devices. He has authored five publics. tions ports. Dr. and twelve papers, is a member as well as several Xi and IBM Tau Technical Beta Pi. Re-

1959

taught

Chemistry

Physics to

at

Alexandria,

France

LeBlanc

of Sigma