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Miosaw Chodacki
Faculty of Computer Science and Materials Science University of Silesia Katowice, Poland miloslaw.chodacki@us.edu.pl
AbstractThe paper shows an influence of a choice of autonomous testing structure on fault coverage in synchronous digital sequential circuit testing. In order to increase testability of sequential circuit during testing, its memory module usually undergoes a disconnection. At the time the testing structure gains access to no-primary output of the testing circuit. The circuit undergoes transformation into combinational circuit. A possibility of disconnection of a memory module results from including of multifunctional registers which execute a circuit memory function. It turns out that high fault coverage may often be gained without disconnection of the module. Thus, it is not necessary to apply such registers. Therefore the complexity of circuit is limited as far as a circuit area overhead for its application and additional mode control during its work are concerned. Nevertheless, it is not always possible. Even partial disconnection of memory modules during testing phase enables to increase fault coverage due to increasing circuit testability. Simulation studies carried out on a considerate amount of ISCAS'89 testing circuits set show rightness of introduced conception of sequential circuits testing without interference with its memory function. An important factor enabling suggested approach is an adequate choice of autonomous testing structure. Keywords biult-in self-test, self-test path, pseudorandom test, digital circuit testing
Dariusz Badura
Institute of Information Technology Katowice, Poland dariusz.badura@wsti.edu.pl
I.
INTRODUCTION
The testing of digital circuits is a very important component in designing electronic devices. The Built-In Self Test (BIST) structures are most often designed as Test Pattern Generator (TPG) and Test Response Compactor (TRC) systems, based on Linear Feedback Shift Registers (LFSR) and Multi-Input Signature Registers (MISR) [1]. There are also alternative Autonomous Test Structures (ATS) completed basically with Self-Test Path (STP) and Circular Self-Test Path (CSTP). In general, however, it is impossible to cover all failures, thus it is justified to search for more effective ATSs. The design of minimal ATSs of appropriate high diagnostic efficiency is a difficult task. The functioning of STP or CSTP is highly dependent on the function of the circuit under test, thus posing the problem of proper ATS selection, in general. The commonly used mechanism enhancing testability of a
sequential system understood most generally as an ability to control and observe internal system nodes with its primary outputs is disconnection of its Memory Modules (MM) at the test stage. Then, a difficult to test synchronous sequential circuit by nature is converted into a more easily testable combinational circuit; such transformation requires, however, appropriate MM components and area overhead to be chosen to perform additional functional control, e.g. multi-functional BILBO registers. The problem is to design a ATS which can be used without transformation of a synchronous sequential circuit during testing, thus also without intervention in the sequential circuit specification, while expecting similar testing effectiveness measured at least with the value of Fault Coverage (FC). It has been found that this cab be achieved even by using a test of the length comparable to that of pseudodeterministic test and significantly shorter than that of pseudorandom test prevailing in BIST applications. The effective ATS that requires no intervention in MM block of a synchronous sequential system at the testing stage provides significantly easier hierarchical testing of digital circuits, packages and systems. However, sometimes this is impossible, and the implementation of a MM subset of a sequential circuit into ATS significantly enhances the testing efficiency, as described in this article. In this paper the results of simulations of various ATS configurations enabling enhancement of diagnostic effectiveness, and even in some cases the reduction of area overhead to its hardware implementation are presented. II. AUTONOMOUS TEST STRUCTURE
ATS basic structure is understood as a shift register, of which a feedback is the testing circuit. As an ATS structure role a self-test path (STP) or circular self-test path (CSTP) may be used [2]. Fig. 1 shows an ATS structure which covers matrixes of input and output connections, additional shift feedback and set of switches controlling type of ATS work, apart from above mentioned. Influence of choice of feedback and connection matrixes on the increase of testing effectiveness will be shown later on. The ATS structure shown on Fig. 1 has a simulate model character, of which operation is described by register with Non-linear Feedback Shift Register (NLFSR) in a simplified method [3].
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TOP-BOTTOM LFSR (id 6000-7500), additional external and internal linear feedback are possible.
To configure STP/CSTP register connections with the circuit CUT, the following connection diagram types were distinguished: INPUT MATRIX 1 (id 1-300), complex connections available to the part of the STP/CSTP register that controls inputs of the tested circuit. INPUT MATRIX 1 LONG (id 300-600), complex connections, while allowing connections with any component of the STP/CSTP register. INPUT MATRIX E (id 600-900), simple connections. INPUT MATRIX FREE (id 900-1200), connections through XOR matrices, but only with those STP/CSTP register cells that control input of tested circuit. INPUT MATRIX FREE LONG (id 1200-1500), connection through XOR matrices with any STP/CSTP register cells. OUTPUT MATRIX 1 (id 1-100), complex connections, available for those cells of STP/CSTP register that are responsible circuit response. OUTPUT MATRIX connections. E (id 100-200), simple
Figure 1. Autonomous Test Structure.
where: V(t+1) is a vector of register outputs in a consecutive, discreet moment of time t. V(t) is a vector of register outputs in current moment t, T is a square matrix of connections describing structure of a register, F(V(t)) is a vector of nonlinear functions introduced to the register as a feedback. The size of vectors V(t+1), V(t) and F(V(t)) as well as T matrix are connected with a length of p register (number of D type flipflops). NLFSR register operation may be described as follows (1):
V (t + 1) = T V (t ) F (V (t ))
(1)
OUTPUT MATRIX FREE (id 200-300), connections through XOR matrices, but only with those STP/CSTP register cells that control output of tested circuit.
Influence of output connection matrix on NLFSR register function may be shown as a square matrix form, OM (2):
V (t + 1) = T V (t ) OM F (V (t ))
(2)
OM matrix function is a modification of output signals of testing circuit by a change of connections of circuit primary outputs with an ATS register. Depending on a structure type of the matrix, there are various functionalities that can be singled out. Similarly, an operation of IM matrix of input connections may be shown. Under are ATS structure configuration modes taking into consideration additional non-linear feedback and connection matrixes. The following linear feedback types can be chosen when configuring ATS model: AIJ TOP-BOTTOM LFSR (id 1-1500), additional external and internal linear feedbacks are possible. BOTTOM LFSR (id 1500-3000), additional internal linear feedbacks is possible. SHIFT LFSR (id 3000-4500), no additional linear feedback. TOP LFSR (id 4500-6000), additional external feedback is possible.
In brackets above there are identifiers being useful in analysis of simulation graphs presented in Fig. 3, 4, 5 and 6. For example, the ATS identifier equals 5100 indicates an ATS with additional linear feedback of TOP LFSR type and the input connection matrix INPUT MATRIX 1 LONG enabling connection of the tested circuit input with any STP or CSTP register component, and the output connection matrix OUTPUT MATRIX FREE, allowing an additional XOR matrix structure containing logic functors of the exclusive sum ExOR to be generated. The effectiveness of STP/CSTP depends mainly on: Length of STP/CSTP register. Length of test sequence. First state of STP/CSTP register and initial state of MM for synchronous sequential circuits. Schema of connection STP/CSTP to circuit.
The function of Output Matrix E, that is an identity matrix, is described as follows (1)
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1 0 0 0 0 0
0 1 0
0 0 0 0 1 0 0 0 0 0
0 0 0