1

7. THE SUBMICRON MOSFET

We now consider what happens when a MOSFET is scaled (i.e., reduced in size) to the point
where the long-channel equations fail to predict some important effects. We look first at the
general issue of scaling, and continue with some effects observed in small devices.

We should keep in mind that accurate modeling requires 2D simulation. We can extract some
important physics using intuition and 1D modeling, however, and we will do that where we can.
We will also look at reducing the 2D Poisson Equation to 1D by making some approximations.
7.1. SCALING RULES
There have been proposed several sets of rules for scaling, for the purpose of discovering as
much as possible the electrical consequences of MOSFET size reduction. Principle among these
are rules by Dennard in 1974 (1 m channel length) and Baccarani in 1984 (0.25 m).

By scaling, we hope to

- Increase packing density and chip functionality.
- Increase device current and speed.
- Lower cost (increase cost effectiveness).

but the trade-offs are

- Mobility degradation due to increased vertical fields.
- Velocity saturation due to increased lateral fields.
- Charge sharing by drain (short channel effects; DIBL)
- Increased drain/source resistance due to reduced area for current flow.
- Hot carrier effects.
7.1.1. Full Scaling
Reference Robert H. Dennard, Fritz H. Gaensslen, Hwa-Nien Yu, V. Leo Rideout, Ernest
Bassours, and Andre R. LeBlanc, Design of Ion-Implanted MOSFETs with Very Small Physical
Dimensions, IEEE J. Solid State Circuits, SC-9 (5), 256 (1974)

Dennard et al. considered full scaling by a factor k > 1. Device size is reduced as follows.

linear dimensions x d x x
ox j
' , ' , ' / k
voltage | | k ' /
doping
N N
B B
'
k
2

MOSFET parameters are changed as follows.

- current
( )
k k k k
c

D D
D T G
ox
ox
eff D
I V
V V V
d L
W
I =

=
2
1
/
'


- power
P I V
P
' ' ' = =
k
2

- power-delay product
P t
Pt
' '
k
3

7.1.2. Generalized Scaling
Reference Giorgio Baccarani, Matthew R. Wordeman, and Robert H. Dennard, Generalized
Scaling Theory and Its Application to a 0.25 m MOSFET Design, IEEE Transactions on
Electron Devices, ED-31 (4), 452 (1984)

Baccarani recognized that full scaling is not sufficiently flexible for sub-m devices because

- Variation in kT/q at elevated T gives unacceptable AV
T
, and V
T
is too low.
- Junction built-in potentials cannot be scaled.

Solution Allow for different length and voltage scales. Also arrange for constant electric field.

voltage | | k ' /
linear dimension
x
x
'

Doping and carrier concentrations
n p N N
B
' , ' ,
'

k
2


This leaves Poissons equation invariant, i.e., electric fields are preserved (for 1-D)


c | k
c c

k
c |
c c

2
2
2 2
2
/
( / )
'
'
'
x
q
x
q
Si Si
= =

3
I n practice, voltages are scaled less aggressively than linear dimensions because of the limitation
on variations in kT/q and for circuit considerations including adequate noise margins. This means
that electric fields tend to increase rather than remain constant.
7.1.3. Empirical Relation for Long Channel Behavior
Because of limitations mentioned above, it should be noted that neither the scaling rules
presented by Dennard nor those by Baccarani have been implemented. J. R. Brews notes a purely
empirical relation describing the minimum channel length for long-channel behavior.

Reference J. R. Brews et al., Generalized Guide to MOSFET Miniaturization, IEEE Electron
Device Letters, EDL-1, 2 (1980)

In this scaling scheme, the goal is to have the scaled device behave like a long channel device.
Criteria are as follows.

- Dependence of drain current on channel length is 1/L within 10%.
- Subthreshold current does not depend on V
DS
(see DIBL below, where V
DS
influences
subthreshold current in short channel devices);

With these constraints, Brews et al. show that the minimum channel length for long-channel
behavior is related to other parameters as

( ) | |
3 / 1
2
min D S ox j
w w t r A L + =

As long as the channel length exceeds L
min
, any combination of the other parameters is
acceptable. In this equation, the junction depth r
j
and the S/D depletion widths w are in microns,
and the oxide thickness t
ox
is in . The parameter A is a fitting parameter, and A = 0.41
1/3
.
Note that this equation is empirical.
Wolf, Fig. 5-44
7.1.4. Off-Current Scaling
A more complex method of controlling off-state current involves specifying a channel doping
profile which gives an acceptably small off-state current and threshold voltage in a device with as
small a channel length as possible.

Reference J. R. Brews, K. K. Ng, and R. K. Watts, The Submicron Silicon MOSFET, Ch. 1, 23-
27, Submicron Integrated Circuits, Ed. R. K. Watts, Wiley Interscience, 1989

4
In this approach, the off-state current is related to the carrier density in the MOSFET channel.
Knowing carrier densities allows selection of an appropriate V
T
and channel threshold adjust
profile.
7.2. SMALL MOSFET MODELING
7.2.5. Charge Sharing Models
It is observed that the threshold voltage of small devices (L < 1 m) is different than is predicted
by the long-channel theories, and that V
T
is a function of channel length. Several factors
contribute to the change in V
T
, some causing it to increase, others to decrease. The observed
threshold voltage will therefore depend on which of these factors dominates the device behavior.
Some simple ideas to explain these phenomena are discussed next. These models are known as
Charge Sharing Models, to indicate that depletion region charge is not controlled entirely by the
gate, but that the source and drain regions also control some of this charge.
7.2.5.1. Short Channel Effect
In small MOSFETs the presence of p-n junction depletion regions in the vicinity of the channel
modify the I
D
- V
GS
relationship, causing V
T
to decrease with decreasing channel length.

Model Intrusion of S/D depletion regions into the channel causes the gate to have control over
less bulk charge than in long channel devices. Thus V
T
is lowered.

Analysis for V
D
=V
S
=0
Uyemura, Figure 2.4
To account for reduced charge control we modify the bulk charge term in V
T
by the factor

f
C
Q
L
L L
C
Q
C
Q
ox
B
ox
B
ox
B
=
A
=

where AL L L =
1
2
1
( ) = average channel length, and the form factor f
L
L
= 1
A
. The form
factor can be treated as a fitting parameter or approximated as follows.

Assume

- S/D diffusions are circular w/ radius x
j
.
- S/D depletion regions are same depth as channel depletion region w. Call this distance x
dm
.

5
x
qN
dm
Si
B
F
~
2
2
c
|

Since V
bi F
~ 2| , this is reasonable. Now (see Uyemura Fig 2.4)

( ) ( ) x x x x L
j dm
dm
j
+ = + +
2 2 2
A

This gives
dm j j j
x x x x L 2
2
+ + = A

Thus the form factor is
f
x
L
x
x
j
dm
j
= +

(
(
1 1
2
1

and the threshold voltage becomes

(
(

|
|
.
|

\
|
+ + + + = 1
2
1 1 ) 2 ( 2
1
2
j
dm
j
F B Si
ox ox
I
F FB
SCE
T
x
x
L
x
qN
C C
qD
V V | c |


We define AV
T
from
T T T
V long V short V A + = ) ( ) ( , which gives

|
|
.
|

\
|
+ = A 1
2
1 ) 2 ( 2
1
j
dm J
F B Si
ox
T
x
x
L
x
N q
C
V | c

This term is negative, i.e., the threshold voltage is reduced. This is a problem since too small a
threshold voltage will give a larger subthreshold current for any V
G
.
Uyemura Figure 2.5
Processing I ssues

- To reduce short channel effects, we can increase N
B
. As N
B
increases, f approaches 1, (x
dm

approaches 0) and AV
T
/V
T
decreases.
- Decreasing oxide thickness, which causes C
ox
to increase, improves things.
- Decreasing junction depth x
j
(shallow junctions) reduces AV
T
.

Analysis for V
D
>V
S

Uyemura Figure 2.6
6
We now have
f
L
L L
S D
= + 1
1
2
( ) A A

We take as an approximation AL
qN
V
S
Si
B
o
~
2c
, which gives
AL
qN
V V
D
Si
B
o DS
~ +
2c
( )

Then we can show

(
(

|
|
.
|

\
|

A
+ +
|
|
.
|

\
|

A
+ = A 1
2
1 1
2
1
2
1
2 2
1
j
D
j
S
j
F B Si
ox
SCE
T
x
L
x
L
L
x
N q
C
V | c

7.2.5.2. Narrow Channel Effect
Model Additional bulk charge in z-direction (along gate width) means that gate controls more
charge than otherwise predicted. This increases V
T
.
Uyemura Figure 2.7, 2.8
Analysis

Bulk charge term is modified to read

) 2 ( A W x L qN LW x qN LW Q
dm B dm B B
+ =

where A is the cross section defining the extra bulk charge. So

Wg
C
x qN
C
Q
ox
dm B
ox
B
=
where
g
A
x W
dm
= + 1
2


We can approximate A in a variety of ways, e.g., assuming circular cross section. Then

A
x
dm
=
t
2
4


7
g
x
Wx
x
W
dm
dm
dm
= + = + 1
2
1
2
2
t t

Generalizing:
g
x
W
dm
= + 1
_

Now

( )
W
x
N q
C
V
dm
F B Si
ox
NWE
T
_
| c 2 2
1
= A

Uyemura Figure 2.10
A note on these plots (Figures 2.5 and 2.10): We are assuming here that everything stays
constant except L; this of course is never the case. What the equations tell us is that V
T
will in
fact be smaller than we planned (assuming narrow channel effect is greater than narrow width
effect). However, to know what is going to happen as L decreases, we have to know the scaling
rules. For example, if we use the Baccarani scaling rules, AV
T
will scale as 1/k (because it is a
potential) and in fact AV
T
/V
T
will be constant.
7.2.6. Quasi-Two-Dimensional Modeling And DI BL
A better way to think about short channel effects is this: when the drain gets close to the source,
the drain voltage is being felt at the source (i.e., it is forward biasing the source/body contact)
and is inducing additional current flow at a given gate bias. Thus the gate bias necessary for a
given current is reduced. This is known as Drain-I nduced Barrier Lowering or DI BL (the
barrier here is the source-body pn junction energy barrier to the flow of electrons into the
channel). This form of DIBL is a surface effect (Surface DI BL) as opposed to Subsurface DI BL
discussed in Section 7.2.4.

To model DIBL correctly requires solving Poissons Equation in 2D

Si
y x
dy
y x d
dx
y x d
c
| | ) , ( ) , ( ) , (
2
2
2
2
= +

with boundary conditions, e.g., 0 ) , ( =
S S
y x | and
D D D
V y x = ) , ( | .

Attempts have been made at analytical solutions of the Poisson Equation by reducing it, via
appropriate approximation, to a 1D problem. We examine two applications of this approach; the
first is an effort by Liu et al. to model DIBL, which we present here. The second application is to
calculation of the electric field in the saturation region, which we do in Section 7.2.7.

8
Reference Z.-H. Liu et al., Threshold Voltage Model for Deep Submicrometer MOSFETs, IEEE
Trans. Electron Devices ED-40, 86 (1993)

We begin by writing Poissons Equation as

c
c
c
c

c
E
E
y
x
Si
x y
y
x y
x
x y
( , )
( , ) ( , )
+ =

The problem is that the x- and y-components of the field (E
x
and E
y
) are both functions of x and
of y; this coupling makes the differential equation difficult to solve. But we can de-couple E
x

and E
y
by approximating the gradient of E
x
(x,y). We do this by assuming that
c
c
E
x
x y
x
( , )
can be
approximated at each point y by an average value equal to the field at the surface divided by an
appropriate depletion region width. See the figure below for the geometry.

d
max
p-Si substrate
n
+
y = L
y = 0
x
B
V
DB
> V
SB
n
+
V
SB
V
GB


We also note that the field in the substrate at the surface can be related to the oxide field by
c c
Si Si ox ox
E E = . Thus

Si ox
surf FB T
Si
ox
y
y x
d t
y V V
y
y x
c

|
c
c
c
c
) , (
) ( ) , (
max
=
|
|
.
|

\
|
+
E


Here, the second term on the left includes the oxide field at the surface, which is given by the
gate voltage (assumed to be at threshold) less the flatband voltage and surface potential, and
divided by the oxide thickness. Also, the relevant depletion region width is here labeled d
max
.
We apply this equation to the DIBL problem by recognizing d
max
as the width of the depletion
region under the channel (i.e., the parameter x
dm
of Section 7.2.1). With the depletion region
charge set to = qN
sub
, Poissons Equation becomes

9
c
q
|
c
|
Si
surf
ox
T FB surf
ox
sub
d
d y
dy
V V y
t
qN d
max
max
( ) ( )
2
2
+

|
\

|
.
| =

This is Equation (5-4b) in Wolf, The Submicron MOSFET, and the notation previously used in
these notes for several parameters has been changed to be consistent with the book. The
parameter q is a fitting parameter as per the analysis by Liu et al.

Solution for |
surf
(y): Boundary conditions are |
surf
(0) = V
bi
(source/channel built-in potential)
and |
surf
(L) = V
bi
+ V
DS
.

( )
( )
( )
( )
( ) ( )
( )
|
surf SL bi DS SL bi SL
y V V V V
y l
L l
V V
L y l
L l
( )
sinh /
sinh /
sinh /
sinh /
= + + +



Here, V
SL
= V
GS
- V
T
+ 2|
F
, where V
T
is the long channel threshold voltage given by

ox
T B
F FB T
C
w qN
V V + + = | 2 ,
l is a characteristic length given by

l
t d
Si ox
ox
=
c
c q
max


and V
bi
is the built-in potential at the source- and drain-substrate junctions.
Wolf, Fig. 5-5
We note that the minimum surface potential, which determines the extent of forward bias of the
source, is greater as channel length is reduced, indicating that more electron flow is to be
expected. In Fig. 5-5, the dashed lines are V
DS
= 0.05 V, and the solid lines are V
DS
= 1.5 V.

We can relate this result to the short-channel threshold voltage V
th
(with V
T
the long channel
threshold voltage). We do this by making the approximation that if the drain voltage is small, i.e.,
V
DS
<< V
bi
- V
SL
, the minimum potential occurs at a point y = L/2 in the channel (this is an
observation from Fig. 5-5). We then have, with y = L/2 in the solution for |
surf
,

( )
| |
( )
( )
|
surf SL bi SL DS
V V V V
L l
L l
,min
sinh /
sinh /
= + + 2
2


We then assume that at threshold, the minimum potential is equal to twice the Fermi potential
(our standard definition for the surface potential at threshold), i.e.,

10
| |
surf F
B
i
kT
q
N
n
,min
ln = =
|
\

|
.
| 2 2

when V
GS
= V
th
. Substituting these conditions into the expression for |
surf,min
above gives

( )
| |
( )
V V
V V
L l
th T
bi F DS
=
+

2 2
2 2 2
|
cosh /

i.e.,

V V V
th T th
= A

If V
DS
is not small, this expression becomes more complicated but the difference from this
approximation is not appreciable. See the reference by Liu for details. Finally we note that if L
is large compared with l, and in particular if L > 5 l, we can approximate AV
th
as

( )
| |
AV V V e
th bi F DS
L l
= +

2 2
2
|
/


and for the case that V
DS
is not small, we have

( )
| |
( )( ) AV V V e V V V e
th bi F DS
L l
bi F bi F DS
L l
= + + +

3 2 2 2 2
2
| | |
/ /


i.e., the threshold voltage shift increases exponentially as the channel length decreases.
Wolf Fig. 5-7
In Figure 5-7, Eqn. 11 is the expression in the paper by Liu for V
th
but relaxing the
approximation that V
DS
is small, i.e., the last expression above for AV
th
.

We note that the analysis presented here is good for LDD MOSFETs as well as non-LDD
MOSFETs, but in the former case we need to interpret V
bi
as the junction potential formed by the
lightly doped region and the substrate.
7.2.7. Reverse Short-Channel Effects
In addition to the reduction in V
T
caused by the short-channel effect (Section 7.2.1.1), it has
been observed that there is an increase in V
T
as channel length is decreased to about 1 m,
followed by a reduction which is more dramatic than is predicted by the charge sharing models.
Several models have been proposed to explain this reverse short-channel effect. They generally
involve re-distribution of channel dopants toward the surface or the S/D regions, such that the
threshold voltage appears as it would in a more heavily doped device, i.e., a bit larger.
11
Wolf, Fig. 5-16
Lateral Dopant Non-Uniformity This model suggests that in nMOS devices having a
punchthrough implant (discussed in Section 7.2.4.2), boron redistributes from the deep implant
toward the surface, and near the S/D regions. This happens because the re-oxidation step
(following S/D implants) injects interstitials into the substrate, thus enhancing boron diffusion.
Reference M. Orlowski, C. Mazure, and F. Lau, Submicron Short Channel Effects Due to Gate
Re-oxidation Induced Lateral Diffusion, IEDM Tech. Dig., 632 (1987)
Wolf, Fig. 5-17
Boron Segregation to I mplant Damage Regions In devices without a punchthrough implant,
boron may still re-distribute toward the S/D regions from the channel, due to implant damage in
these regions (Reference H. Hanafi et al., A Model for Anomalous Short Channel Behavior in
MOSFETs, IEEE Electron Device Letter, ED-14, 575 (1993)) or in the LDD regions (Reference
C. S. Raferty et al., Explanation of Reverse Short Channel Effects by Defect Gradients, IEDM
Tech. Dig., 311 (1993)). This will happen because the boron solubility is higher in the damaged
regions. Note that depletion of boron under the channel decreases V
T
, except that the pile-up
near the S/D regions tends to counteract this effect. However, in very small devices, there is
insufficient channel volume for this effect to counteract re-distribution toward the S/D regions.
Wolf, Fig. 5-20
7.2.8. Punch-Through (Subsurface DI BL)
When drain and source depletion regions touch, we have punch through. What is in fact going
on is that the source is becoming forward-biased by the drain voltage, but below the surface;
hence this effect is referred to as Subsurface DI BL.

We note that Surface DIBL (see Section 7.2.2) can be distinguished from Subsurface DIBL in
that the former does not change the subthreshold swing, while the latter does.
Wolf, Figs. 5-21, 5-23
Tsividis, Fig. 5.18
7.2.9. Channel Mobility
In our long-channel modeling we assumed that the mobility of charge carriers in the inversion
layer (channel mobility) is constant for any biasing condition, which is not the case.

12
General I dea: <
bulk
due to scattering of carriers at the Si surface. Also, for higher fields
perpendicular to surface (E

), channel charge interacts with surface more lower mobility.

Then since E

varies along channel, is not constant.

7.2.9.1. Scattering Mechanisms
Dominant scattering mechanisms are

- Coulomb scattering from ionized impurities as well as charged defects near and at the
interface. This is important at low T and for lightly inverted surfaces (which holds for sub-
threshold).

- Surface roughness scattering from deviations of the Si-SiO
2
interface from an ideal flat
plane. Important at higher T (e.g. room T and above) and for heavily inverted surfaces.

- Phonon scattering due to various phonon modes of the Si lattice. This is important at higher
T (e.g. room T and above).

Room Temperature (300 K): For light inversion, Coulomb and phonon scattering dominate. For
heavy inversion, surface roughness and phonon scattering dominate.
7.2.9.2. Dependence on Gate Voltage
Low V
G
- V
T
Coulomb scattering dominates. As V
G
- V
T
increases, Coulomb scattering is
screened; eventually phonon and surface roughness dominate. Result is a peak in
eff
.
Figure: Sodini et al., Fig. 9
7.2.9.3. Mobility Models
Although many comprehensive theories have been attempted, no unified model exists to explain
all aspects of channel mobility. We have some useful empirical models; a popular one for the
decrease observed in heavy inversion is
) ( 1
T G
O
eff
V V +
=
u


where u is a process dependent parameter.

Sabnis and Clemens (1979) showed that effective mobility
eff
(note change in notation) depends
on an effective electric field at the surface. This field is

E Q q n x dx
eff
Si
B
w
inv
= +
|
\

|
.
|
| }
1
0
c
( ' ) '


13
If we average over n(x), we have
E
Q Q
eff
B I
Si
=
+
1
2
c


This gives a Universal Curve for
eff
regardless of body bias (V
B
). This applies for high T,
heavy inversion, where phonon and surface scattering dominate.
Sabnis and Clemens, Figs. 6, 7
Note that when Coulomb scattering takes effect, e.g. for heavily compensated samples at low
field, a deviation is observed (Fig. 7).

Critical Field Another empirical model is by Frohman-Bentchkowsky:

exp U
eff
Crit
O eff
|
|
.
|

\
|
E
E
=
where E
Crit
is a critical field. If we substitute ) (
2
T GS
Si
ox
eff
V V
C
= E
c
in this expression, we get

exp
) (
2
U
T GS ox
Crit Si
O eff
V V C
|
|
.
|

\
|

E
=
c
.

The fitting parameters here are
o
, E
c
, and U
exp
. This model is used in PSPICE at Level 2.

Mathiessens Rule For several scattering mechanisms, each characterized by
i
, we have

1 1 1 1
1 2 3

eff
= + + + ...

Note that if phonon scattering gives
o
and surface scattering gives
SS
, then

1 1 1

eff O SS
= +
so that
SS
O
O
eff

+
=
1


and if
o
SS eff
E

and
o
O O
E

we have
14

o eff
O
eff O
E E
=
+ 1 ( / )


which was in fact demonstrated by M. S. Liang et al. (1986).
Wolfe Fig 5-33
Experimentally determined parameters for the empirical model discussed above are given in the
table below. See Liang et al., 1986, and K. Y. Toh et al., 1989.

electrons holes holes
(buried channel)

o
(cm
2
/V/s) 670 160 290
E
o
(MV/cm) 0.67 0.70 0.35
o 1.6 1 1

7.2.9.4. Split CV Method
To use the models described above, we need an accurate technique for determining channel
charge. This one involves direct measurement of Q
I
.

) ( ~
T GS ox I
V V C Q
So dc channel conductance is
g
I
V
W
L
Q
D
D
D
I
=
Q
I
can be obtained by a measurement of displacement current in the split CV method.
Experimental set-up (from Hairapetian et al.):















A
A
0
dV
G
/dt =
constant
I
D/A
I
I
V
B

15
Note that i C
dv
dt
= , so a changing gate voltage causes a displacement current I
I
when an
inversion layer is present. Then,
Q C dv
I I G
V
V
o
G
=
}


|
.
|

\
|

dt
dv
i C
G
I I
/


Given Q
I
, can be determined from a fit to the I
D
-V
D
data.

Mobility References

- Anant G. Sabnis and James T. Clemens, Characterization of the Electron Mobility in the
Inverted <100> Si Surface, Tech. Dig., International Electron Devices Meeting, IEDM 1979,
p. 18
- S. C. Sun and James D. Plummer, Electron Mobility in Inversion and Accumulation Layers
on Thermally Oxidized Silicon Surfaces, IEEE Trans. Electron Devices ED-27 (8), p. 1497
(1980)
- M.-S. Liang, J. Y. Choi, P.-K. Ko, and C. Hu, Inversion Layer Capacitance and Mobility of
Very Thin Gate-Oxide MOSFETs, IEEE Trans. Electron Devices ED-33 (3), p. 409 (1986)
- Junji Koga, Shin-ichi Takagi, and Akira Toriumi, A Comprehensive Study of MOSFET
Electron Mobility in Both Weak and Strong Inversion Regimes, Tech. Dig. - IEDM 1994, p.
475
- T. Yamanaka, S. J. Fang, H.-C. Lin, J. P. Snyder, and C. Robert Helms, Correlation Between
Inversion Layer Mobility and Surface Roughness Measured by AFM, IEEE Electron Device
Letters 17 (4), p. 178 (1996)
- Y. P. Tsividis, Operation and Modeling of the MOS Transistor, McGraw Hill 1987, Sect. 4.8
- G. Mazzoni, A. L. Lacaita, L. M. Perron, and A. Provano, On Surface Roughness-Limited
Mobility in Highly Doped nMOSFETs, IEEE Trans. Elec. Dev. 46 (7), pp. 1423-1428 (1999)
- D. Frohman-Bentchkowsky, On the Effect of Mobility in Inversion and Accumulation Layers
on Thermally Oxidized Silicon Surfaces, Proc. IEEE, (56), p. 217 (1968)

Split-CV Technique

- C. G. Sodini, T. W. Ekstedt, and J. L. Moll, Charge Accumulation and Mobility in Thin
Dielectric MOS Transistors, Solid State Electronics, 25 (9), p. 833 (1982)
- Armond Hairapetian, Daniel Gitlin, and C. R. Viswanathan, Low Temperature Mobility
Measurements on CMOS Devices, IEEE Trans. Electron Devices, 36 (8), p. 1448 (1989)
16
7.2.10. Velocity Saturation And High Field Effects
In short channel devices, both vertical and lateral electric fields are large when the gate oxide and
channel length are reduced without a proportional decrease in terminal voltages. The result of a
high lateral field is velocity saturation; the result of high vertical fields is charge injection and
other hot carrier effects. In this section we examine the effects of velocity saturation in the
MOSFET channel using a 1 dimensional model.

Reference
- Sodini, Ko, and Moll, The Effect of High Fields on MOS Device and Circuit Performance,
IEEE Trans. Electron Devices ED-31(10), 1386 (1984)

To consider the effect of reduced channel length on the drain current, we
- Account for high vertical fields by including mobility degradation.
- Account for high lateral fields by including velocity saturation.
7.2.10.1. Model for Channel Current
Mobility
We use our empirical model for mobility, where
o
and u are fitting parameters.

u
eff
o
G T
V V
=
+ 1 ( )


Velocity
We model the channel carrier velocity empirically.

C SAT
C
C
eff
E E v
E E
E E
E
v
> =
<
+

=
/ 1

where E
C
is the critical field at which the electron velocity saturates.
Wolfe, Fig. 5-35
Note that when E = E
c
, we have (accounting for only the magnitude of E
C
)

eff
sat
C
v
E

2
=

We already can draw an important conclusion: Higher V
G
- V
T
lower
eff
higher E
C
. Thus
as gate voltage increases, the lateral field (and thus the drain voltage) at which the velocity
saturates is increased.
17

Assumptions
- Source/Drain series resistance = 0.
- Square Law model holds.
- DIBL is not a problem.

Model

We define V V V
G G T
' . As a general expression for current we have I = qnv, hence

I C V V y Wv y
D ox G
= ( ' ( )) ( )

This is the Square Law model but with I
D
expressed in terms of drift velocity v(y). The
geometry discussed for that model holds here.

Sodini 1984 Fig. 2

We can solve for E in terms of v as follows

v
E
E E
E v v
E
E
eff
C
eff
C
=

+
= +

1 /


Solving for v in the expression for I
D
and substituting gives

=

eff
D
ox G
D
ox G C
E
I
C V V y W
I
C V V y W
E
E ( ' ( )) ( ' ( ))

Thus,

= =

E
dV y
dy
I
W C V V y I E
D
eff ox G D C
( )
( ' ( )) /


We re-write this expression and integrate

W C V
I
E
W C V y dV I dy
eff ox G
D
C
eff ox
V
D
L DS
' ( )
|
\

|
.
|

(
=
} }
0 0



18
W C V
I
E
V W C V I L
eff ox G
D
C
DS eff ox DS D

'

|
\

|
.
| =
1
2
2


Solving for drain current gives

( )
I
W C V V
L V E L
V V V
D
eff ox G DS
DS C
DS DS D SAT
=

|
\

|
.
|
+
<

'
,
/
1
2
1

Saturation Region
For V
DS
= V
D,SAT
, velocity v = v
SAT
, so returning to our original expression for current we have


( )
I WC V V v
D SAT ox G D SAT SAT ,
'
,
=

Also, we have v E
SAT C eff
=
1
2
. Now put V
DS
= V
D,SAT
into the previous expression for I
D
,
and equate the result to this last expression above to get

( )
( )
1
2
1
2
1
E WC V V
W C V V
L V E L
V
C eff ox G D SAT
eff ox G D SAT
D SAT C
D SAT

'
,
,
,
,
/
=

|
\

|
.
|
+



We now solve this expression for V
D,SAT
, which gives

V
V E L
V E L
D SAT
G C
G C
,
'
'
=
+


Substituting this expression into our general current equation at saturation gives

|
|
.
|

\
|
+
=
L E V
L E V
V E WC I
C G
C G
G eff C ox SAT D
'
'
'
,
2
1


I WC E
V
V E L
D SAT ox C eff
G
G C
,
'
'
=
+
1
2
2


Besides having a model that accounts for mobility degradation and velocity saturation, we can
use these results to make some observations about short channel devices.
19
Sodini 1984 Figs. 4, 5
1. E
C
and L appear as a product, so a device is long-channel-like for large L or large E
C
.

2. A decrease in oxide thickness causes a larger vertical field (assuming no scaling in gate
voltage), hence a lower mobility and a larger critical field. All of this results in a larger
saturation drain voltage, and overall longer-channel behavior.

3. V
D,SAT
decreases with decreasing L.

4. The behavior of I
D,SAT
changes depending on whether the MOSFET is long- or short-channel
like. From this last equation for I
D,SAT
we have

I V if E L V long channel like
D SAT G C G ,
'
' ( ) >>
2

I V if E L V short channel like
D SAT G C G ,
'
' ( ) <<

So I
D,SAT
is over-predicted by simpler theories.
Wolfe, Fig. 5-36, Table 5-3, Fig. 5-38, Fig. 5-1
A note on Figures 5-36, 5-38: The reference here is K.-Y. Toh, P.-K. Ko, and R. G. Meyer, An
Engineering Model for Short-Channel MOS Devices, IEEE J. Solid State Circuits 23 (4), p. 950.
That reference sites Sodini (1984 see references above) for the original model, but includes in
the expression for I
D
the effect of an electrical gate length L
e
= L
eff
X
d
, where X
d
is the
depletion width extension into the drain (a formula is given in the paper), which depends on (V
DS

V
DSAT
). This explains the increase in I
DSAT
with V
DS
, even though the expression above clearly
indicates it should be constant. There is also some curve-fitting for g
m
. So it is not clear that
these figures can be calculated from the formulae presented here.

A note on Table 5-3: No reference is provided here. Only C
ox,
L, and V
GS
are given, with and
V
T
left unspecified. If one normalizes the long-channel current to 1 and from that determines
(V
GS
- V
T
)
2
, the values in this table are not reproduced; this means that some variation of V
T

and have been incorporated but not stated.
Saturation Transconductance
We look at the transconductance in saturation.

| |
g
I
V V
v WC V V
m SAT
D SAT
G G
SAT ox G D SAT ,
,
,
' '
( ' ) = =
c
c
c
c


( ) g v WC
V
V
m SAT SAT ox
D SAT
G
,
,
'
=
|
\

|
.
| 1
c
c

20
But
V
V E L
V E L
D SAT
G C
G C
,
'
'
=
+

so
c
c
V
V
V E L V E L E L
V E L
D SAT
G
G C G C C
G C
,
'
' ( ' )( )
( ' )
=
+ +
+
2

=
+
1
1
2
( ' / ) V E L
G C


and with a bit more manipulation we can show that

|
|
|
|
|
.
|

\
|
+
=
2 '
2 2
,
1
1
G
C
ox SAT SAT M
V
L E
C Wv g

Thus for the limiting case of L = 0 or large V
G
, the maximum g
M,SAT
is Wv
SAT
C
ox
. This is to be
compared with the prediction of long channel theory, which is that transconductance increases
with decreasing L and increasing V
G
:

( )
(

= =
2
' ,
,
2 ' '
G
ox eff
G G
SAT D
SAT m
V
L
W C
V V
I
g

c
c
c
c


( )
'
, G
ox eff
SAT m
V
L
W C
g

= . Long-Channel Model

So the long-channel model predicts a linear increase in transconductance with gate drive (V
G
);
this increase reduces to sub-linear for small devices, and eventually saturates. Note also that for
larger gate drive, deviations from a linear increase in transconductance will be observed for
larger devices.

For another view of the device performance, we can go back to the expression for current:

I C V V y Wv y
D ox G
= ( ' ( )) ( ) .

We can see what is going on at the source by setting y = 0. In that case

) 0 ( ) ' ( Wv V C I
G ox source
= .

Evidently, we have maximum current when the velocity at the source v(0) reaches saturation. As
this begins to happen, transconductance begins to saturate.
21
Sodini 1984 Fig. 11
7.2.10.2. Velocity Saturation Region
We review a model for MOSFET behavior in the velocity-saturated drain region. The model
attempts to account for 2D effects, specifically those associated with large fields near the drain
region, using the Quasi-2D formulation of Poissons Equation discussed in Section 7.2.2.

References

- Y. A. Mansey and A. R. Boothroyd, A Simple Two Dimensional Model for IGFET Operation
in the saturation Region, IEEE Trans. Electron Devices ED-24 (3), 254 (1977)

- P. K. Ko, R. S. Muller and C. Hu, A Unified Model for Hot-Electron Currents in MOSFETs,
Tech Digest, Intl Electron Devices Meeting, p. 600 (1981)

Goal We desire a model of high field effects at the drain. Two-dimensional simulations show
that electric fields increase there more dramatically than long-channel theories predict.
Wolfe, Figures 5-42, 5-43
In addition, Ko et al. (1981) have used this model to predict gate and substrate currents; we will
take up this topic in the next chapter.

Assumptions

- Geometry of Fig 5-43 holds.
- Carriers are velocity-saturated, so field is E
C
or greater.
- Current flow is restricted to depth defined by junction.

Notethe notation has changed in these figures: what we are now calling E
sat
has previously been
called E
C
. Both represent the critical (or saturation) field, at which electron velocity saturates.
Model
The feature of the model not usually accounted for is that the oxide field is reduced in magnitude
as the drain is approached. This is consistent with the reduction in mobile charge (and increase
in bulk charge) toward the drain.

We recall the Quasi-2D model of Section 7.2.2, and apply it to the problem of the velocity
saturation region by noting that from the geometry of Fig. 5-43, the relevant depletion depth over
which to average the electric field in the x-direction is r
j
. Further, the charge density in the
region of interest is = + qN qN
A M
, where N
A
is the bulk doping and N
M
is any mobile charge
present in the region. Then Poissons Equation is

22
d y
dy
V V V y
t r
qN qN
ox
Si
GS FB B
ox j
A
Si
M
Si
E( ) ( )
+

|
\

|
.
|
|
= +
c
c
|
c c
2


This is Equation (5-57) of Wolf, with notation modified to be consistent with the book. In
particular, the potential in the channel is V(y), and the Fermi potential is |
B
; thus the numerator
in the second term on the left represents the threshold condition.

We have made use of
| |
E
t
V V V y
ox
ox
GS FB B
=
1
2| ( )

The importance of this model as compared with simpler models (Fig. 5.42) is that it accounts for
the variation of the oxide electric field with position (see previous equation). In addition, it does
not assume that mobile charge (i.e., inversion layer charge) is 0, as the simplest models assume.

We proceed by noting a constraint from Gauss Law:

( ) E y
q
r N N
ox
ox
j A M
( ) = = + 0
c

also, V y V
D SAT
( )
,
= = 0
| | ( )
M A j
ox
SAT D B FB GS
ox
N N r
q
V V V
t
+ =
c
|
,
2
1


| |
dE
dy t r
V y V
ox
ox Si j
D SAT
=
c
c
( )
,


which is Equation 5-61 in Wolf.

I nterpretation To the extent that V(y) is greater than V
D,SAT
, inversion layer charge is released
by the oxide field (i.e., is no longer controlled by it), so there must be an increase in the lateral
field to the extent given by dE/dy.

Now...
| |
2
,
2
,
2
) ( ) (
l
V y V
dy
V y V d
dy
dE
SAT D SAT D

=

=

where l t r
Si
ox
ox j
2
=
c
c
. The boundary conditions on this differential equation are
23
SAT D
SAT
V y V
E y E
,
) 0 (
) 0 (
= =
= =


Solution
) / ( ) ( l y Cosh E y E
SAT
=

) / ( ) (
,
l y Sinh lE V y V
SAT SAT D
+ =

At the drain (y = AL) we have a maximum in the value of E(y) = E
m
. Thus

|
.
|

\
| A
=
l
L
Cosh E E
SAT m


|
.
|

\
| A
+ = A = =
l
L
Sinh lE V L y V V
SAT SAT D D ,
) (

Solving these two equations is a bit messy, but straightforward. We get

(

|
|
.
|

\
|
+
|
|
.
|

\
|
= A
l E
V V
E
E
l L
SAT
SAT D D
SAT
m
,
ln ;

2
2
,
SAT
SAT D D
m
E
l
V V
E +
|
|
.
|

\
|
= .


NoteThe controlling parameter here is V
D,SAT
which contains the only dependence on channel
length: recall that

'
'
,
G SAT
G SAT
SAT D
V L E
LV E
V
+
= .
Drain Current
We now go to our expression for I
D,SAT
. We again take the approach that a channel shortened by
AL will cause an increase in current, so we set I
D
= I
D,SAT
and L L L A .

(
(

A +
+
|
|
.
|

\
|
A

) (
,
,
, ,
L L E V
L E V
L L
L
I l
SAT SAT D
SAT SAT D
SAT D SAT D


24
where I
D,SAT
is evaluated from with V V
D D SAT
=
,
.

Note that we have here a model for the MOSFET current in saturation which includes the
channel modulation (channel shortening) from L to L-AL. We discussed this effect in Chapter 6,
Section 6.9, but here we have presented a much better model for AL, as well as a more accurate
model for I
D
in saturation.
7.2.11. Two-Dimensional Modeling
As we have pointed out, accurate modeling of very small devices require numerical solution of
device physics equation in two dimensions. We briefly review here the nature of 2D device
simulation programs, using Silvaco International's Virtual Wafer Fab as an illustration. In
addition, we look at some results from IBM T. J. Watson Research Labs using the Monte Carlo
device simulator DAMOCLES.
7.2.11.1. Silvaco's Virtual Wafer Fab (VWF)
ReferenceC. M. Snowden, Introduction to Semiconductor Device Modeling, World Scientific
Publishing Co, 1986

Numerical solution of device physics equations, for example, Poisson's equation and the
continuity equation, can be done using several methods. Principle among these are the finite
difference method, and the finite element method. Silvaco's VWF uses the latter.

These methods provide "discretization" of the differential equations, that is, they allow
differential equations in continuous variables to be written in terms of algebraic equations. The
algebraic equations generally express variations in space and time as differences between
variables at discrete points in the device.

The discretization process requires that we define a "mesh" throughout the device. Values of the
relevant variables are calculated at the "nodes", or intersection points of the mesh. In the finite
element method, a smoothly varying function is generally assumed to connect values between
mesh points. Solutions of differential equations are then taken as the sum of solutions within
each "finite element", i.e., within areas bounded by mesh points.

The finite element method has an important advantage over the finite difference method, in that
arbitrary and complex geometries can be handled more easily because the shape of the finite
element (i.e., the mesh geometry) is arbitrary, and indeed can be defined to change in size across
the device.

In addition to solution of differential equations describing device fabrication and electrical
properties, simulation programs such as VWF allow the user to choose from a wide variety of
physical models describing surface mobility, carrier generation/recombination, and hot carrier
generation, to name a few. In addition, several modules are available to handle special problems
including optical carrier generation and absorption, heat transfer, and quantum effects.
25

Figures:
1. A 0.5 m device showing gate/source/drain regions, as well as the grid of points (mesh) used
to solve the differential equations.
2. Plot of doping densities throughout the device, showing source/drain junctions and LDD
regions.
3. 1-D plots of doping densities along vertical and horizontal cut-lines.
4. Potential and electric field for various gate/drain voltages. Note that an increase in gate
voltage reduces the peak lateral electric field near the drain, i.e., there is a partial canceling
of the lateral field due to application of a gate voltage. Similarly, there is a decrease in the
vertical field near the drain because of application of drain voltage. (Field and potential
figures courtesy of James Beacham, UH senior, Summer 2000)
7.2.11.2. Quantum Monte Carlo Calculations from the IBM T. J. Watson
Research Center
Another attempt at modeling the small channel MOSFET comes from the quantum Monte-Carlo
simulation program DAMOCLES developed at the IBM T. J. Watson Research Laboratories. On
their web site, http://www.research.ibm.com/0.1um/laux/html_files/nmos.html, they demonstrate
simulations for a 0.15 m channel length MOSFET. The simulation models the transport of a
large number of electrons whose paths are computed individually using statistical methods, with
quantum effects such as accurate band structure and scattering rates included.

Figures:

1. Cross-section of the device with source on the left and drain on the right, along with 8000
electrons in the channel and the source/drain regions. The color code indicates the energy of
the electrons; note that the electron energy increases toward the drain. The model considers
electrons only near the edges of the source and drain regions, excluding the large volume of
electrons in the bulk of the S/D. Channel extends from approximately 0.18 m to 0.33 m.

2. Conduction band edge from the source to the drain along with electron energies plotted
vertically. Note that as the drain region is approached, more and more electrons have
energies considerably above the conduction band edge.

3. Velocity of the electrons in the channel. Note that this function peaks sharply toward the
drain. More importantly, velocities near the drain exceed the saturation velocity in silicon,
which is approximately 1 x 10
7
cm/sec. This phenomenon is known as velocity overshoot.

Velocity overshoot occurs when charge carriers travel ballistically in the channel, i.e., cross it
without scattering, or with little scattering probability. This mode of transport allows velocities
to exceed the saturation velocity of the semiconductor.

4. Increase in transconductance associated with velocity overshoot. Note that even as the
channel length drops below 0.1 m, the transconductance continues to increase. The
reference by Sai-Halasz is IEEE Electron Device Letters 9 (9), 464 (1988)
26

Recall that in our models so far, we suggested that the transconductance of the device will
saturate as the channel length approaches 0, because the velocity saturates. (See the expression
for the saturated transconductance in Section 7.2.5.1.2.) If the velocity over shoots the saturated
velocity however, then as the channel length decreases we should expect that transconductance
will continue to increase.

The IBM group has also done modeling of a Dual-Gate MOSFET, which is reviewed in Section
8.3.5.
7.3. CHANNEL DOPING FOR SHORT-CHANNEL MOSFETs
7.3.12. n-MOSFETs
It is common practice in modern MOSFET fabrication to provide both a near-surface implant for
threshold adjust (as previously described) and a deeper implant (at ~ S/D junction depth) to
suppress punch-through for L < 1 m.
VLSI Microstructure Science Vol 18 Ch 2, Fig. 2
7.3.13. Super-Steep Retrograde Doping Profiles
Reference D. A. Antoniadis and J. E. Chung, Physics and Technology of Ultra Short Channel
MOSFET Devices, Proc. IEDM 1991, pp. 21-24

Antoniadis and Chung point out that as channel length decreases and doping density increases to
control AV
T
, mobility drops due to increased scattering. However, if channel doping can be
decreased, even to the point of being intrinsic, mobility is improved, and even more importantly,
velocity overshoot is observed.

Velocity overshoot is predicted when modeling includes "non-local" transport effects, which are
included, for example, in the Monte Carlo studies shown above. See Antoniadis and Chung for
references. (See also Dual-Gate MOSFET devices below, where such effects are included in
modeling of this device by Baccarani.)

Super-Steep Retrograde Doping is achieved using In implantation to get profiles with very low
surface doping (< 5 x 10
15
cm
-3
for a 200 keV dose of 5 x 10
12
cm
-2
), but high sub-surface doping
to control short channel effects (8 x 10
17
cm
-3
at 0.08 m). Experimental results show non-
saturating transconductance as channel length drops.
27
Antoniadis, Fig. 3
The plot shows g
m
/WC
ox
, and should be compared with the calculations shown in Section
7.2.6.1, where it was argued that g
m
saturates due to velocity saturation.
7.3.14. p-MOSFETs
Historical Problem Common p-type dopants (especially B) diffuse very rapidly lateral spread
of S/D is severe DIBL and punch-through are more likely. This requires a deep channel n-
type implant to suppress punch-through.

Consequences
- Increased doping increased junction capacitance (generally undesirable).
- V
T
is already negative for n-substrate; increased doping makes it too negative.
Wolf, Fig. 4-19
Note asymmetry inherent in n- and p-MOS V
T
due to sign of |
ms
and Q
i
/C
i
(which are both
negative).

Solution Use second, p-type implant near surface to re-adjust V
T
.

Result p-MOSFET tends to be buried channel, which is more susceptible to leakage and punch-
through (see below).
Wolf, Figs. 5-54, 5-55
The solution to this problem is to use a p
+
gates, so the work function component is positive, V
T

is less negative, and the necessity for a large threshold-adjust would be removed.
7.3.14.1. p-MOSFET SHORT-CHANNEL EFFECTS
If the p-MOSFET is buried-channel due to the circumstances discussed above, it exhibits short-
channel effects which are different from those in n-MOSFETs.

Reference A theory of buried-channel devices which applies to both depletion mode FETs and
buried channel (BC) p-MOSFETs doped as described above is given by:

J. S. T. Huang, Jay W. Schrankler, and J. S. Kueng, Short-Channel Threshold Model for Buried
Channel MOSFETs, IEEE Trans. Electron Devices, ED-31 (12), 1889 (1984)
28
7.3.15. Halo Doping
To suppress punch-through without dramatically effecting channel doping, we can use halo
implants. These are especially important because of the short-channel effect in pMOS devices,
but are used for both n- and p-channel devices.
Wolf, Fig. 5-71

7.4. HIGH-FIELD EFFECTS: LEAKAGE CURRENT
There are several components of leakage current, either at the drain (I
D
) or at the gate (I
G
) which
become significant due to high fields in the drain region. These currents are of concern because
they may cause excessive power dissipation, create oxide defects, or result in DRAM discharge.

Notes
- The ordinary reverse-bias saturation current of the drain/substrate pn junction tends to be
smaller than leakage current components to be considered here, but even this component may
be large at elevated temperature.
- The current components discussed here are not inherently short-channel effects, but rather are
due to high fields in the drain region, which tend to appear in short-channel devices.
7.4.16. GI DL (Gate-I nduced Drain Leakage)
We have already considered DIBL, which is a short channel effect and is often characterized as a
leakage current.

Reference J. Chen, T. V. Chan, I .C. Chen, P. K. Ko, and Chenming Hu, Sub-breakdown Drain
Leakage Current in MOSFETs, IEEE Electron Device Lett. EDL-8 (11), 515 (1987)

Observation Excessive leakage current observed at low gate voltage. Increases with V
D
and
decreasing V
G
.
Wolfe, Fig. 4-30
J. Chen et al. (1987) Figures 1, 3, 4
Origin Band-to-band tunneling in substrate near drain.

Model Tunneling |
s
> 1.2 V. Thus
29
c c
c
c
Si Si ox ox Si
DG
Si
ox
ox
E E E
V
d
= =
12 .

Then I
D
~ A E
Si
exp(-B/E
Si
) which is a general expression for a tunneling current. This
expression is fitted to the data in Fig. 3, which shows reasonable agreement with theory.
7.4.17. SI LC (Stress-I nduced Leakage Current)
ReferenceD. J. DiMaria and E. Cartier, Mechanism for Stress-Induced Leakage Currents in Thin
Silicon Dioxide Films, J. Appl. Phys. 78 (6), 3883 (1995)

Observation After high-field stressing of an MOS oxide such as might occur in FLASH memory
devices), an increased gate current is observed. The increase occurs in a region of the I-V curve
characteristic of direct tunneling.
DiMaria Figs. 1, 3
Origin Trap-assisted tunneling via neutral electron traps generated by passage of electron
current through the oxide (see discussion on oxide defects).