Lab 08: SR Flip Flop Fundamentals:

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NOR Gate SR Flip Flop. SR Flip Flop. SR Flip Flop with a positive edge clock: SR Flip Flop with a negative edge clock: Flip Flop waveform diagrams:

Lab 08: NOR Gate SR Flip Flop :

%he cross&coupled NOR gates creates an SR Flip Flop. Flip Flops are the basic elements used in computer memory. %he S input is called Set. %he R input is called Reset.
R 01 0 1 10 0 1 1 0 00 1 Q Q settles at logic $ Q changes 2oth outputs from # to $. Q changes settle to $. #. %his 0alled from $ the to breaks the reset 1 0alledmode the Set definition. %his mode1 condition is not allowed S $ $ # # R $ # $ # Output No 0hange Q sta s at $ Reset: Q changes to $ Set: Q changes to # +mbiguous : Not allowed1

01 0 S 00 1

11 0 00 1

Output Q and Q are b definition alwa s opposite to each other. !f Q"# then Q "$.
Behaviour Table: 'ogic gates are defined b %ruth %ables. Flip Flops are defined b behaviour tables. %wo different names for tables that do essentiall the same (ob. %o generate the behaviour table ou must assume an initial condition at output Q. %his is necessar because the outputs are wired to the inputs. %his creates a feedback path that can onl be anal )ed when a starting point is assumed. Start Nextwith S,R = S,R 0,1 1,0 1,1 =:0,0 %he : %he anal anal sis procedure sis procedure works works as follows: as follows: #&*lace #&*lacethe theinitial initialconditions conditionsat atoutput outputQ Qon onthe thediagram. diagram.+ssume +ssumeQ Q"$. "#. "$. ,&*lace ,&*lacethe theinput inputconditions conditionsat atS Sand andR. R. -&+nal -&+nal )e )ethe thetop topNOR NORgate gateand andrecord recordQ. Q. .&+nal .&+nal )e )ethe thebottom bottomNOR NORgate gateand andrecord recordQ. Q. /&Repeat /&Repeatsteps steps--and and..until untilQ Qand andQ Qsettle. settle.
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Lab 08: SR Flip Flop :

0ross&coupled NOR gates create an SR Flip Flop. !t is eas to remember the operation of an SR flip flop using onl the s mbol without repeatedl anal )ing the cross coupled NOR gate s stem.
%he S input is called SE the R input is called reset. %he are both active high. !cti"e #ig# means that S $1 sets the flip flop 4S $0 does %ot set5. R $1 resets the flip flop 4R $0 does %ot reset5. S6% means set output Q to 7#8. R6S6% means reset output Q to 7$8. :hen S $0 and R $0 then Q does %ot c#a%ge. Q #olds its logic level 41 or 05. !t is e;uivalent to %ot issui%g either the set or the reset command.

10 0 00 1

S R

Q Q

10 0 1 +ssume Output Output Q reset does reset S6%s S6%s Qnot starts :: Q Q :$1 change : Q $1 at Q . $0 . $. $0 .. 01 1 0

S mbol

:: S"# &old &old : Set 'ode R"# 'ode 9ode : :: : reset 9ode : :hen S $1 and R $1 then Q is ambiguous. 2oth Q and Q outputs go to the same logic level which breaks the definition of a flip flop. <ou can think of it this wa = S $1 sa s SE and R $1 sa s reset( %he flip flop does not know whether the output should be Q $1 or Q $0. S$R$1 should never be used1

%here is a second variet of SR flip flop that uses an active low S and R inputs. %he internal s stem is cross coupled N+N> gates. !cti"e lo) means that S $0 sets the flip flop 4S $1 does %ot set5. R $0 resets the flip flop 4R $1 does %ot reset5. 0 1 1 0 1 S R Q Q 1 Output 0 +ssume Q does S6%s Q not starts : Qchange $1 at . $. 0 1 :hen S $1 and R $1 then Q does %ot c#a%ge. Q #olds its logic level 41 or 05. !t is e;uivalent to %ot issui%g either the set or the reset command. :hen S $0 and R $0 then Q is ambiguous. %he flip flop does not know whether the output should be Q $1 or Q $0. S$R$0 should never be used1

S"$ : Set 9ode : :: R"$ : &O*+ :reset 9ode 9ode Slide 3-

Lab 08: SR Flip Flop with a Positive Edge T igge ed !lo"# $nput :
+ *ositive 6>G6 triggered flip flop has a new input called clock. %he clock re;uires a transition from $ to # in order that S and R controls output Q. ?olding a constant logic # or a constant logic $ at the clock input does not allow SR to change output Q.
+n edge triggered clock is identified with 7@0lk8 on the s mbol. 1 0 S Q ,-l. R Q 0 +ssume 1 Output S6%s Q starts : Q $1 at . $. 1 0 + transition from $ to # at 7@0lk8 is re;uired in order for the flip flop to respond to S and R. %his is called a8 *ositive 6dge8. :atch the animation to see how ou would set the flip flop.

?olding 7@0lk8 at logic # will not result in S and R controlling Q. Onl the $ SR Flip Flop with edge to # transition at 7@0lk7 causes the output Q to change. triggered clock S"# : Set 9ode : /%side t#e SR Flip Flop )it# 0ositi"e Edge riggered -loc.1 %he clock signal is applied to the input. 120
S ,-l.

1 120
R

2 3

120 0 S 120 0 R

Q Q

%he NO% gate dela s the signal because it has a propagation dela . *ropagation dela is the reaction time of the inverter. 'etAs use - to #$ nanoSec.

- to #$ nanoSec dela .

>uring the - to #$ nanoSec intervalB +N> gate 3# outputs a #. +N> gates 3, and 3- transfer the logic levels to internal SR and Q responds. +fter the - to #$ nanoSec interval +N> gate 3# outputs a $. +N> gates 3, and 3- transfer the logic $ to internal SR and Q holds4S"R"$ is ?old mode5. %o re&clock the flip flop ou need another positive edge. 0lock must return to $ and re&change back to #.

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Lab 08: SR Flip Flop with a Negative Edge T igge ed !lo"# $nput :
+ negative edge triggered flip flop re;uires a transition from # to $ at at the clock input in order for the flip flop to respond to S and R. %his is called a8 Negative 6dge8. !t is the opposite of a positive edge triggered flip flop.
+n edge triggered clock is identified with 7oC@0lk8 on the s mbol. 1 0 S Q ,-l. R Q 0 +ssume 1 Output S6%s Q starts : Q $1 at . $. 1 0 :atch the animation to see how ou would set the flip flop. ?olding 7oC@0lk8 at logic $ will not result in S and R controlling Q. Onl the # to $ transition at 7oC@0lk7 causes the output Q to change.

SR Flip Flop with edge triggered clock S"# : Set 9ode :

Here is a summary o the li! lo! devices

S R Q Q S R Q Q S Q ,-l. R Q S Q ,-l. R Q

Non&0locked SR S and R control the response at Q continuousl .

6dge %riggered S and R control the response at Q onl when 0lk is making a transition. On the edge of the clock signal.

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Note Pa"# % : Flip Flop &ave'o m (iag ams :

%o draw waveforms for flip flops ou need to begin with an initial condition at QB mark the area where the clock input is asserted and then draw the output response. 'etAs use an initial condition of Q "$.
%he initial condition Q "$ is marked as a dot on the output waveform diagram. %he flip flop has a negative edge triggered clock. %he clock is asserted when 0lk makes a transition from # to $. %he asserted )one is marked off in ellow. +nal )e the waveform and draw Q.

Set Reset 0lock

S Q ,-l. R Q

Dntil On this the negative clock changes edge S"# S"R"$: from and # No to R"$: $0hange it is S6% NO% 9ode. 9ode. asserted. %hus Q sets holds to at #. $. No No anal analsis sis isis re;uired re;uired until until the neEt neEt negative edge.

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