TABLE 3.

PERFORMANCE AND GATE COUNT COMPARISON OF ROM AND NEXT 2-D LFSR FOR THE 250 MHZ SAMPLED WAVEFORM

TABLE 4. PERFORMANCE AND GATE COUNT COMPARISON OF ROM AND NEXT 2-D LFSR FOR THE SUM OF TWO SINUSOIDAL SIGNALS (105 MHZ AND 250 MHZ) SAMPLED WAVEFORM

ROM (single port ROM using NEXT 2-D Xilinx Core Generator) LFSR Performance Comparison Max. frequency 100.4 MHz 238 MHz Time to generate 18 patterns 119.52 ns 42 ns Latency 2 clock cycles None Gate Count Total equivalent gate count 65,539 51 from Xilinx Mapping Report File

ROM (single port ROM NEXT 2-D LFSR using Xilinx Core Generator) Performance Comparison Max. frequency 100.4 MHz 226 MHz Time to generate 50 patterns 471.12 ns 221 ns Latency 2 clock cycles None Gate Count Total equivalent gate 65,603 193 count from Xilinx Mapping Report File

The second waveform is sum of two sinusoidal signals, 105 MHz and 250 MHz, which was sampled and digitized at a rate of 2500 MHz (Fig. 6). Only 50 points was used for storing as the data can be repeated continuous by triggering the reset and mux select signals. The BIST hardware for 8b binary equivalent of the 50 sampled points was synthesized using the HPC based highly optimized NEXT 2-D LFSR algorithm described in section III. C. Ten configurations were required for the implementation. Each configuration embedded 5 patterns each. The performance and gate count comparison of ROM generated using Xilinx Core Generator and NEXT 2-D LFSR for the sum of two sinusoidal signals (105 MHz and 250 MHz) sampled waveform is given in Table 4. It can be observed from the above discussion that the NEXT 2-D LFSR outperforms the conventional ROM implementation not only with respect to the time needed to generate the waveforms, but also the hardware required to embed them. VI. CONCLUSION: An HPC based automated LFSR based BIST test vector generator synthesis technique for mixed-signal SoCs was proposed. The proposed technique that utilizes the parallel processing capability of GPU significantly reduces the BIST generator synthesis time. The versatility of the BIST generator, that allows it to be used for embedding deterministic patterns for LBIST and storing sinusoidal stimuli or pre-calculated Delta-Sigma modulated bit-stream for mixed-signal BIST, was demonstrated. The performance and total equivalent gate count of ROM and NEXT 2-D LFSR based BIST generators was compared and contrasted by synthesizing onto Spartan 3 FPGAs using the Xilinx ModelSim design flow. It was observed that the time to generate test patterns using the NEXT 2-D LFSR based generator is highly reduced in comparison with the ROM which has low speed and latency. The experimental results and simulations underlines the effectiveness of the proposed HPC based BIST synthesis technique that can be adopted for both LBIST and analog/mixed-signal SoC designs.

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