National Conference on Communications & Electrical Engineering, NCACEE 2K13

Design and Implementation of Low Power, Area efficient FIR Digital Filter using Vedic Multiplier
Jaideep Kumar Nag1, Hajira Fathima2, Abdul Quir Khaja Hussain3
2

Associate Professor,ECED,Muffakham Jah College of Engineering and Technology, Hyd, AP, j_k_nag@yahoo.com Assistant Professor,ECED,Muffakham Jah College of Engineering and Technology,Hyd, AP, shajirafathima@gmail.com 3 Student, M.E, (Digital Systems), Muffakham Jah College of Engineering and Technology, Hyd, AP, khajahussain20@gmail.com

Abstract In this paper low power, area efficient Finite Impulse Response (FIR) filter have been designed using IEEE-754 format floating point adder and floating point multiplier. Most of the power consumption of the filter occurs in multiplier unit. An efficient Vedic multiplier has been used in the floating point multiplier which is efficient in terms of power and area. The IEEE-754 standard provides the method for representation of binary floating point numbers. Low pass filter specifications have been given in FDA tool in matlab and the obtained coefficients will be multiplied with the given input and the result obtained after performing multiplication and addition is said to be low pass. The coefficient multiplier bits are represented in single precision IEEE-754 format. The formats are composed of 3 fields they are sign, exponent and mantissa. Mantissa is represented by 23bits, exponent is represented by 8 bits and the single bit is reserved for sign bit. The two input 23bit mantissa are multiplied using Vedic multiplication technique. Vedic mathematics is the ancient system of mathematics which has a unique technique of calculation based on 16sutras. Among those sutras Urdhva Triyagbhyam method has been used for multiplication. For addition of floating point number a standard IEEE-754 algorithm have been used in which exponents are first compared if they are equal then mantissa are added or subtracted or else they are first normalized and then addition or subtraction is performed based on the sign bit. A Digital FIR filter has been designed using this efficient floating point multiplier and floating point adder. The design have been implemented and synthesized in cadence. Index TermsFinite Impulse response, filter design and analysis tool, Institute of electrical and electronics engineers.

(FFT), Correlation etc. Most DSP tasks require realtime processing; it must perform these tasks speedily while minimizing Cost and Power. In many DSP algorithms, the multiplier lies in critical delay path and ultimately determines the performance of algorithm. In the past, multiplication was implemented generally with a sequence of addition, subtraction and shift operations. There have been many algorithms proposals in literature to perform multiplication, each offering different advantages and having tradeoff in terms of speed, circuit complexity, and area and power consumption. One of common application most commonly used in DSP is FIR filter.FIR filter requires multiplication, addition and subtraction. An efficient Vedic multiplication technique has been used for multiplication of mantissas in the multiplier block. Floating point addition is performed using standard IEEE-754 format. Computer does not understand real numbers. It first coverts the floating point number to IEEE-754 format performs the required operation and then the result is again converter back to floating point number. Inputs to the filter are in standard IEEE-754 format. Multiplier stores the coefficient values in the IEEE-754 format. The coefficients obtained from FDA tool are floating point numbers So floating point multiplier and floating point adder have been designed. Direct form realization of FIR filter have been designed and implemented in cadence and synthesized to find out area, speed and power.
II. FIR Filter

I. INTRODUCTION Power consumption is critical design issue in DSP applications. Most of the power consumption occurs in multiplier unit. Multiplication process is most commonly used in many of the DSP applications. Application such used in many Neural computing and DSP applications, communications, audio and video processing, Graphics, image enhancement, Navigation, radar, GPS, and control applications like robotics, machine vision, guidance. It is mainly used to implement algorithms like frequency domain filtering (FIR, IIR), frequency-time transformations

A filter is essentially a system or network that selectively changes the wave shape, amplitudefrequency and/or phase-frequency characteristics of a signal in a desired manner. Common filtering objective are to improve the quality of a signal, to extract information from signals or to separate two or

National Conference on Communications & Electrical Engineering, NCACEE 2K13

more signals previously combined to make efficient use of an available communication channel. A digital filter is a mathematical algorithm implemented in hardware or software that operates on a digital input signal to produce a digital output signal for the purpose of achieving a filtering objective. The term digital filter refers to the specific hardware or software routing that performs the filtering algorithm. Digital filters often operate on digitized analog signals or just numbers, representing some variable, stored in a computer memory. [9] Digital filters play very important role in DSP. Compared with analog filters they are preferred in number of applications for example data compression, biomedical signal processing, speech processing, image processing, data transmission, digital audio, telephone echo cancellation. Digital filters are of two types FIR and IIR filters. A Digital FIR filter has been designed because of their advantages over IIR filter. Among the different realizations direct form realization has been implemented in cadence. The direct form realization of FIR filter consists of multipliers and adders. Most of the power consumption of the filter occurs in multiplier unit [1]. So in this project a novel and efficient floating point multiplier have been used and standard algorithm for addition has been used. The block diagram of direct form realization of filter is shown in the Fig.1.

calculus (both differential and integral), and applied mathematics of various kinds. All these Sutras were reconstructed from ancient Vedic texts early in the last century. Many Sub-sutras were also discovered at the same time, which are not discussed here. The beauty of Vedic mathematics lies in the fact that it reduces the otherwise cumbersome-looking calculations in conventional mathematics to a very simple one. This is so because the Vedic formulae are claimed to be based on the natural principles on which the human mind works. This is a very interesting field and presents some effective algorithms which can be applied to various branches of engineering such as computing and digital signal processing [7,8]. The multiplier is based on an algorithm Urdhva Tiryakbhyam (Vertical & Crosswise) of ancient Indian Vedic Mathematics. Urdhva Tiryakbhyam Sutra is a general multiplication formula applicable to all cases of multiplication. It literally means Vertically and crosswise. The advantage is that it reduces the need of microprocessors to operate at increasingly high clock frequencies. While a higher clock frequency generally results in increased processing power, its disadvantage is that it also increases power dissipation which results in higher device operating temperatures. By adopting the Vedic multiplier, microprocessors designers can easily circumvent these problems to avoid catastrophic device failures. The processing power of multiplier can easily be increased by increasing the input and output data bus widths since it has a quite a regular structure. Due to its regular structure, it can be easily layout in a silicon chip. The Multiplier has the advantage that as the architecture is quite efficient in terms of silicon area/speed [8, 4]. The working of Vedic multiplier is as shown in the Fig.2.

Fig.1 Direct form Realization of Filter [9] III. Vedic Multiplier

The word Vedic is derived from the word Veda which means the store-house of all knowledge. Vedic mathematics is mainly based on 16 Sutras (or aphorisms) dealing with various branches of mathematics like arithmetic, algebra, geometry etc. These Sutras along with their brief meanings are enlisted below alphabetically. These methods and ideas can be directly applied to trigonometry, plain and spherical geometry, conics,

Fig.2 the Vedic Multiplication line diagram Method The working of Vedic multiplier is as follows consider numbers A and B where A = a2 a1a0 and B = b2b1b0. The LSB of A is multiplied with the LSB of B. we obtain p0=a0b0;

National Conference on Communications & Electrical Engineering, NCACEE 2K13

Then a0 is multiplied with b1, and b0 is multiplied with a1 and the result is added together as: c1p1=a1b0+a0b1; Here c1 is carry and s1 is sum. Next step is to add c1 with the multiplication results of a0 with b2, a1 with b1 and a2 with b0. c2p2=c1+a2b0+a1b1 + a0b2; Next step is to add c3 with the multiplication results of a1 with b2 and a2 with b1. c3p3=c2+a1b2+a2b1; Similarly the last step c4p4=c3+a2b2. Now the final result of multiplication of A and B is c4p4p3p2p1p0.

be used for multiplication of mantissas in the floating point multiplier unit.

Fig.4 Block diagram of 6 bit Vedic multiplier

Fig.3 three bit Vedic multiplier architecture The block of three bit Vedic multiplier architecture is show in the Fig.3 in which full adder and half adder are used for performing the required operation.Using 3 bit Vedic multiplier architecture a six bit Vedic multiplier has been designed by instantiating 3 bit Vedic multiplier. Similarly using six bit Vedic multiplier a 12 bit multiplier has been designed and using 12 bit multiplier 24 bit multiplier have been designed and implemented.As shown in the Fig.4 Six bit Vedic multiplier has been designed using seven bit adder and eight bit adder. For multiplication of input bits, three bit Vedic multiplier has been instantiated four times. Input of the multiplier is six bit wide and output is thirteen bit wide including carry out. This six bit Vedic multiplier block will be used in the twelve bit Vedic multiplier block for multiplication. As shown in the Fig.5 24 bit Vedic multiplier has been designed using 24 bit adder and 25 bit adder. For multiplication of input bits, 12 bit Vedic multiplier has been instantiated four times. Input of the multiplier is 24 bit wide and output is 48 bit wide including carry out. This 24 bit Vedic multiplier will

Fig.5 Block diagram of 24 bit Vedic multiplier As shown in the Fig.5 24 bit Vedic multiplier has been designed using 24 bit adder and 25 bit adder. For multiplication of input bits, 12 bit Vedic multiplier has been instantiated four times. Input of the multiplier is 24 bit wide and output is 48 bit wide including carry out. This 24 bit Vedic multiplier will be used for multiplication of mantissas in the floating point multiplier unit.

National Conference on Communications & Electrical Engineering, NCACEE 2K13

IV.

Floating Point Multiplier

Digital signal processing applications essentially requires the multiplication of binary floating point numbers. Institute of electrical and electronics engineers (IEEE) have provided the format for representation of binary floating point numbers. The Binary Floating point numbers are represented in Single precision format and Double precision formats. The Single precision format consists of 32 bits and the Double precision format consists of 64 bits. In single precision format the format is composed into 3 fields they are Sign, Exponent and Mantissa. The Mantissa is represented in 23 bits and 1 bit is added to the MSB for normalization and later renormalized back, Exponent is represented in 8 bits. The Exponent is biased to 127 and MSB of Single is reserved for Sign bit. When the sign bit is 1 that means the number is negative and when the sign bit is 0 that means the number is positive. Whereas for 64 bits format representation the Mantissa is represented in 52 bits, the Exponent is represented in 11 bits which is represented in excess1023 and the MSB is reserved for sign bit. In single precision format the two inputs are represented in IEEE-754 format. For the sign calculation the input bits are XOred.

Fig.7 floating point multiplier V. Binary Floating-Point Addition Algorithm

Fig.6 IEEE Format for Single Precision

The standard binary algorithm of floating point addition and the basic implementations of binary floating-point adders are as follows. Let A, B be two binary floating-point numbers whose addition results in a new floating number Z where CA, CB, and CB are the significands of A, B, and Z respectively. EA, EB, and EZ are their exponents. SA, SB, and SZ are the signs of their significands. CA*, CB*, and CZ* are their signed significands. First, the difference between the exponents EA, and EB must be computed. According to this difference, the number with the smaller exponent is multiplied by 2 raised to the power of the exponent difference (This process is called alignment). Then addition is performed. In order to be compliant with the IEEE 754 standard, the resulting number must be normalized and rounded according to the required rounding mode. The detailed algorithm of binary floating-point addition is 1) Compute the exponent difference d and set the result exponent to be the larger exponent. 2) Significand alignment: This is performed by shifting the number with the smaller exponent d positions to the right. 3) Add or subtract the aligned significands according to the effective operation. The effective operation depends on the floating-point

The standard representation of IEEE format for single precision is shown in the Fig.6.The general form of the representation is where S represents the sign bit, M represents the mantissa and E represents the exponent. Where E is the exponent and fraction part is f= b0 b1 b2 For an IEEE-754 single precision the Mantissa Calculation Unit requires a 24 bit multiplier. In this project an efficient Vedic Multiplication Technique has been used for multiplication of mantissa. The Vedic multiplier is 24 bits but the input is 23 bits for this purpose the 24 bit is assigned with one to MSB of the Vedic multiplier unit later the result is normalized. Using Vedic multiplication technique speed, area and timing have been optimized The Exponent Calculation Unit requires addition. For addition of exponent a modified carry select adder have been used. After addition the result is then biased back to -127 and is given to final result.

National Conference on Communications & Electrical Engineering, NCACEE 2K13

operation and the sign of the operands according to the Table.1 4) Normalization: The resulting significand is not necessarily normalized. If the effective operation is addition, there is a chance a final carry might have occurred. This is resolved by shifting the result one position to the right and incrementing the result exponent. If the effective operation is subtraction, there is a chance some leading zeros might occur in the significand of the result. This is resolved by first detecting the amount of leading zeros, then shifting the result to the left a number of positions equal to the number of leading zeros. The exponent must be adjusted as well. Table.1 Effective Operation Computation Floating Point Sign of the Effective operation operands operation Addition Addition Subtraction Subtraction Equal Different Equal Different Addition Subtraction Subtraction Addition

Final Adjustment: Rounding itself can generate a final carry or a special value (infinities for instance). If a final carry has occurred, normalization has to be performed again by shifting the number one position to the right and incrementing the exponent. If rounding yields a special value, the resulting number must reflect this change. Number must reflect this change. VI. Results

Fig.9. Floating point multiplier

The input given are a=-19.0 and b=9.5 these floating point number can be represent in IEEE-754 format as a=32b1_10000011_00110000000000000000000, and b=32b1_10000011_00110000000000000000000. The output obtained is p=32b1_10000110_01101001000000000000000. After normal multiplication of -19.0 and 9.5 we get -180.5. Converting the result -180.5 into IEEE-754 format we get 1_10000110_01101001000000000000000. The obtained result p is as same as the expected binary value. Various inputs have been given and output result was tested.

5) Rounding: The result should be rounded according to the specified rounding mode.

Fig.10 floating point adder

Fig.8 Block diagram of floating point adder

As shown in the Fig.10 the input given at the first stage is a=4.2782078 and b=4.2782078.these values can be represented in standard IEEE-754 format as given a=32'b 000000001_00010001110011100010100 and b=32'b000000001_00010001110011100010100. In the given inputs exponents are same so shifting is not

National Conference on Communications & Electrical Engineering, NCACEE 2K13

required. Both the mantissas are added and the obtained result is p=00000000_100100011100111000101000. The output has been cross verified using a normal system calculator. The obtained result is 8.5564156.

After Synthesis, Layout of the design is performed. using Encounter in Cadence tools. It generates GDS2 (Graphic database system) file. The layout of the main module FIR filter is shown in the Fig.13.

Fig.11 floating point adder FIR filter As shown in the Fig.11 the output has been obtained on the fifth clock cycle. We get four clock cycle delay because the order of filter is N=4. The input to the filter is 1.8572824e-2(0.018572824). The input has been taken from FDA tool. The input in multiplied with the coefficients at each stage. the multiplication and addition operation is performed by instantiating the designed floating point adder and multiplier modules. The expected output is 0.02468089924. After converting xout result back to float point number we get the same result i.e 0.02468089924.

Fig.13 Layout of the FIR filter

Table.2 Performance summary of FIR digital filter

VII. Conclusion In this project work, a low power, area efficient FIR digital filter using efficient floating point multiplier and floating point adder have been designed and implemented. Floating point multiplier, floating point adder and FIR filter is capable of computing 32 bit input. The low pass filter specification has been given in FDA tool. Coefficients have been obtained from the given specification. The obtained coefficients are floating point numbers. Because the coefficient is floating point numbers, floating point multiplier and adder have been designed. Vedic multiplier has been used in the floating point multiplier unit. For floating point adder standard algorithm have been used. These modules were designed using Verilog HDL and implemented in Cadence. The synthesis is performed using RTL complier of Cadence. Synthesis summary of filter is shown in Table.2. Using Encounter layout of filter is performed. The

Fig.12 RTL synthesis of FIR filter Fig.12 shows the synthesis of floating point FIR filter using floating point adder and floating point multiplier

National Conference on Communications & Electrical Engineering, NCACEE 2K13

desired signal first has to be first converted into digital form using ADC and then the filtering operation is performed. The ADC output format should match with the filters input format i.e. first bit(MSB) decides sign bit, next to MSB, 8 bit decides the exponent value and the remaining 23 bits decides the fractional part. References
[1] Vijaya Prakash A.M, K.S.Gurumurthy, A Novel Architecture for Low Power FIR Filter In International Journal Of Advance Engineering & Application, Jan 2011. [2] Aniruddha Kanhe, Shishir Kumar Das,Ankit Kumar Singh Design and Implementation of Floating Point Multiplier based on Vedic Multiplication TechniqueIEEE,2011. [3] Bahram Rashidi, Bahram Rashidi, Majid pourormazd Design and Implementation of Low Power Digital FIR Filter based on low power multiplier and adders on Xilinx FPGAIEEE,2011. [4] M.Ramalatha, K. Deena Dayalan, P.dharni, S.Deborah priya, High Speed Energy Efficient ALU Design Using Vedic Multiplication Techniques IEEE, 2009. [5] Aniruddha Kanhe, Shishir Kumar Das, Ankit Kumar Singh Design and Implementation of Floating Point Multiplier based on Vedic Multiplication Technique IEEE,2011 [6] Meena Talwar, Karan Gumber,Sharmelee Thangjam, Performance analysis of Floating Point Adder using Sequential Processing on Reconfigurable Hardware IJERA, Vol.2,Issue 3, May-june 2012,pp.1226-1229. [7] Emmanuel C. Ifeachor, Barrie W. Jervis Digital Signal Processing: A Practical Approach, Second Edition. Pearson Education, ISBN Number: 81-7808-609-3, 2003. [8] Ali Malik, Seok-Bum Ko, Effective Implementation of Floating-Point Adder using Pipelined LOP in FPGAs IEEE, may 2005. [9] IEEE-754 floating point conversion from decimal to floating point from http://babbage.cs.qc.cuny.edu/IEEE754.old/Decimal.html. [10] Abhishek Gupta, Utsav Malviya, Vinod Kapse, A Novel Approach to Design High Speed Arithmetic Logic Unit Based on Ancient Vedic Multiplication Technique IJMER july-aug 2012 [11] Sandesh S.Saokar,R.M.Bankar and Saroja SiddamalbHigh Speed Signed Multiplier for Digital Signal Processing Applications [12] A.Nagoor Kani Digital Signal Processing, First Edition, RBA Publications. [13] V JAyaprakasan, S Vijayakumar, V S Kanchana bhaaskaran Evaluation of the Conventional vs. ancient computation methodology for Energy Efficient Arithmetic Architecture IEEE 978-1-61284-764-1/11/2011. [14] IEEE standard for binary-floating point arithmetic, ANSI/IEEE Std 754-1985, The Institute of Electrical and Electronic Engineers Inc., New York, August 1985.

[15] Manual conversion of decimal to floating point number from the website http://sandbox.mc.edu/~bennet/cs110/flt/dtof.html [16] IEEE Floating Point Representation of Real Number, Fundamentals of Computer Science. Link: http://www.math.grin.edu/~stone/courses/fundamentals/ieee reals.html [17] Devika, jaina,Kabiraj Sethi, and Rutuparna panda and Rutuparna Panda Vedic Mathematics Based Multiply Accumulate Unit

Jaideep Kumar Nag received his B.Tech(ECE) degree in 1985 from JNTU Hyderabad and M.E(Digital Systems) in 1986 from Osmania university, Hyderabad. He has about 25 years of teach teaching experience. His areas of interest include System on Chip architecture and micro controllers based system design. He is working as Associate Professor in ECE Dept. Muffakham Jah College of Engineering and Technology Hyderabad. He is a Fellow Life member of IETE.

Hajira Fathima has received her B.E degree in 2003 and M.E (systems and signal processing) in 2008 from Osmania university, Hyderabad. She has about 10 years of experience. Her about 10 years of experience. Her areas of interest include VLSI-DSP, digital signal processing, and Adaptive Signal Processing. Presently she is working as assistant professor in ECE dept of Maulana Azad National Urdu University polytechnic, Hyderabad she is the life member of IETE. Abdul Quir Khaja Hussain received his B.E (ECE) degree in 2011 from O.U Hyderabad. Currently he is the student of M.E (Digital Systems), Muffakham Jah College of Engineering & Technology, Hyderabad. Technology, Hyderabad.