EX.

NO: AIM:

FLIPFLOPS

To design and implement flip-flops in Verilog HDL. SOFTWARE REQUIRED: Xilinx ISE 9.2i. THEORY: Flip-flops is the asi! "ilding lo!#s of the most se$"ential !ir!"its. Flipflop samples its inp"ts and !hanges its o"tp"ts onl% at times determined % !lo!#ing signal. The & main flipflops "sed are D'T and () flipflop.

D FLIPFLOP: The D flipflop is #no*n as Dela%ed Flipflop. The next state is al*a%s e$"al to the D inp"t and it is independent of the present state. Therefore o"tp"t is same as that of the inp"t. T FLIPFLOP: If the T inp"t is high' the T flip-flop !hanges state +,toggles,- *hene.er the !lo!# inp"t is stroed. If the T inp"t is lo*' the flip-flop holds the pre.io"s .al"e. This eha.ior is des!ri ed % the !hara!teristi! e$"ation.

JK FLIPFLOP: The () flip-flop is therefore a "ni.ersal flip-flop' e!a"se it !an e !onfig"red to *or# as an S/ flip-flop' a D flip-flop' or a T flip-flop. Spe!ifi!all%' the !om ination ( 0 1' ) 0 2 is a !ommand to set the flip-flop3 the !om ination ( 0 2' ) 0 1 is a !ommand to reset the flip-flop3 and the !om ination ( 0 ) 0 1 is a !ommand to toggle the flip-flop' i.e.' !hange its o"tp"t to the logi!al !omplement of its !"rrent .al"e. Setting ( 0 ) 0 2 does 45T res"lt in a D flip-flop' "t rather' *ill hold the !"rrent state.

D - Flip Flop

BLOCK DIA RAM :

TRUTH TABLE

CLK High High

D 2 1

Q 2 1

PRO RAM: mod"le dff+d' !l#' $-3 inp"t d3 inp"t !l#3 o"tp"t $3 reg $023 al*a%s 6+posedge !l#egin assign $0d3 end endmod"le T!"#$!%&' (o)*l! mod"le test en!h+-3 reg d'!l#3 *ire $3 dff d1+d'!l#'$-3 initial egin !l#017 23 fore.er 892 !l#0:!l#3 end initial egin d017 23 fore.er 892 d0:d3 8;2 <finish3 end endmod"le OUTPUT WA+EFORM :

J-K - Flip Flop

BLOCK DIA RAM

TRUTH TABLE

J 2 2 1 1

K 2 1 2 1

Q% = 2 1 :=

CLK 1 1 1 1

JK-Flip Flop PRO RAM: mod"le >#ff+!l#' >' #' $-3 inp"t !l#3 inp"t >3 inp"t #3 o"tp"t $3 reg $023 al*a%s 6 +posedge !l#egin if +>002 ?? #001assign $023 else if +>001 ?? #002assign $013 else if +>002 ?? #002assign $0$3 else assign $0:$3 end endmod"le T!"#$!%&' (o)*l! mod"le test en!h+-3 reg !l#'>'#3 *ire $3 >#ff >#1+!l#'>'#'$-3 initial egin !l#017 13 fore.er 892 !l#0:!l#3 end initial egin >017 23#017 23 892 >017 23#017 13 892 >017 13#017 23 892 >017 13#017 13 892 <finish3 end endmod"le

OUTPUT WA+EFORM :

T - Flip Flop

BLOCK DIA RAM

TRUTH TABLE
Q% 2 2 1 1 T 2 1 2 1 Q 2 1 1 2

T-Flip Flop PRO RAM mod"le tff+!l#' t' $-3 inp"t !l#3 inp"t t3 o"tp"t $3 reg $023 al*a%s 6 +posedge !l#egin if +t002assign $0$3 else assign $0:$3 end endmod"le T!"#$!%&' (o)*l! mod"le test en!h+-3 reg !l#'t3 *ire $3 tff t1+!l#'t'$-3 initial egin !l#017 13 fore.er 822 !l#0:!l#3 end initial egin t017 23 892 t017 13 892 t017 23 892 t017 13 892 <finish3 End endmod"le

OUTPUT WA+EFORM :

RESULT: Th"s the program for D' () and T Flip Flop is implemented and the o"tp"t *a.eform is .erified s"!!essf"ll%.

DATE: EX.NO: AIM:

SHIFT RE ISTERS

To design and implement Shift registers in Verilog. SOFTWARE REQUIRED: Xilinx ISE 9.2i THEORY: The inar% information +data- in a register !an e mo.ed from stage to stage *ithin the register or into or o"t of the register "pon appli!ation of !lo!# p"lses. This t%pe of it mo.ement or shifting is essential for !ertain arithmeti! and logi! operations "sed in mi!ropro!essors. This gi.es rise to a gro"p of registers !alled @ SHIFT RE ISTERSA.The% are .er% important in appli!ations in.ol.ing' storage and transfer of data in a digital s%stem. Mo)!" o, Op!-.#io% o, S'i,# R!/i"#!-" : 1. Serial in Serial 5"t 2. Serial in Barallel 5"t &. Barallel in Serial 5"t C. Barallel in Barallel 5"t SERIAL IN SERIAL OUT: PRO RAM: mod"le sisosm+d' !l#' $' *1' *2' *&-3 inp"t d3 inp"t !l#3 o"tp"t $3 ino"t *13 ino"t *23 ino"t *&3 dff d1+d'!l#'*1-3 dff d2+*1'!l#'*2-3 dff d&+*2'!l#'*&-3 dff dC+*&'!l#'$-3

SHIFT RE ISTER 0 SERIAL-IN SERIAL-OUT

BLOCK DIA RAM

TRUTH TABLE CLK High High High HIgh D 1 2 2 2 W1 1 2 2 2 W2 2 1 2 2 W3 2 2 1 2 4 2 2 2 1

endmod"le (o)*l! #!"#$!%&'567 reg d' !l#3 *ire $3 sisosm sm1+d' !l#' $-3 initial egin !l#017 23 fore.er 89 !l#0:!l#3 end initial egin d013 812 d023 812 d013 812 d023 8&2 <finish3 end endmod"le mod"le dff+d'!l#'$-3 inp"t d'!l#3 o"tp"t $3 reg $023 al*a%s6+posedge !l# $ D0 d3 endmod"le OUTPUT WA+EFORM :

SHIFT RE ISTER 0 SERIAL IN PARALLEL OUT

BLOCK DIA RAM

TRUTH TABLE:

CLK High High High HIgh

D 1 2 2 2

41 1 2 2 2

42 2 1 2 2

43 2 2 1 2

48 2 2 2 1

SERIAL IN PARALLEL OUT: PRO RAM: mod"le sip2+d' !l#' $1' $2' $&' $C-3 inp"t d3 inp"t !l#3 o"tp"t $13 o"tp"t $23 o"tp"t $&3 o"tp"t $C3 dff d1+d'!l#'$1-3 dff d2+$1'!l#'$2-3 dff d&+$2'!l#'$&-3 dff dC+$&'!l#'$C-3 endmod"le mod"le dff+d'!l#'$C-3 inp"t d'!l#3 o"tp"t $C3 reg $C023 al*a%s6+posedge !l# $C D0 d3 endmod"le mod"le test en!h+-3 reg d' !l#3 *ire $1'$2'$&'$C3 sip2 sm1+d'!l#'$1'$2'$&'$C-3 initial egin !l#017 23 fore.er 89 !l#0:!l#3 end initial egin d013 812 d023 812 d013 812 d023 8&2 <finish3 end endmod"le

SHIFT RE ISTER 0 PARALLEL IN SERIAL OUT

BLCOK DIA RAM

TRUTH TALBE INPUT CLK 2 1 1 A 1 1 1 B 2 2 2 C 1 1 2 D 1 1 2 S 2 1 1 OUTPUT Q 2 2 1

OUTPUT WA+EFORM :

PARALLEL IN SERIAL OUT PRO RAM: mod"le pinso"t+!l#' a' ' !' d' s' $-3 inp"t !l#3 inp"t a3 inp"t 3 inp"t !3 inp"t d3 inp"t s3 o"tp"t $3 *ire $1'$2'$&'*'g1'g2'g&'gC'g9'g;'d1'd2'd&3 assign * 0 :s3 dff f1+$1'a'!l#-3 dff f2+$2'd1'!l#-3 dff f&+$&'d2'!l#-3 dff fC+$'d&'!l#-3 and1 a1+$1's'gC-3 and1 a2+*' 'g1-3 and1 a&+$2's'g9-3 and1 aC+*'!'g2-3 and1 a9+$&'s'g;-3 and1 a;+*'d'g&-3 or1 r1+g1'gC'd1-3 or1 r2+g9'g2'd2-3 or1 r&+g;'g&'d&-3

endmod"le mod"le and1+a' '!-3 inp"t a' 3 o"tp"t !3 assign !0a? 3 endmod"le mod"le or1+a' '!-3 inp"t a' 3 o"tp"t !3 assign !0aE 3 endmod"le mod"le dff+$'d'!l#-3 o"tp"t $3 inp"t !l#'d3 reg $3 initial $017 23 al*a%s 6+posedge !l#$0d3 endmod"le

OUTPUT WA+EFORM :

SHIFT RE ISTER 0 PARALLEL IN PARALLEL OUT

BLOCK DIA RAM

TRUTH TABLE

INPUT CLK High High )9 2 1 )1 1 2 )2 2 1 )3 1 1 41 2 1

OUTPUT 42 1 2 43 2 1 48 1 1

PARALLEL IN PARALLEL OUT : PRO RAM: mod"le pinpo"t+!l#' *1' *2' *&' *C' $1' $2' $&' $C-3 inp"t !l#3 inp"t *13 inp"t *23 inp"t *&3 inp"t *C3 o"tp"t $13 o"tp"t $23 o"tp"t $&3 o"tp"t $C3 dff d1+!l#'*1'$1-3 dff d2+!l#'*2'$2-3 dff d&+!l#'*&'$&-3 dff dC+!l#'*C'$C-3 endmod"le mod"le dff+!l#'d' $-3 inp"t d3 inp"t !l#3 o"tp"t $3 reg $023 al*a%s 6+posedge !l#egin $D0d3 end endmod"le T!"#$!%&' (o)*l! mod"le test en!h+-3 reg !l#'*1'*2'*&'*C3 *ire $1'$2'$&'$C3 pinpo"t s1+!l#'*1'*2'*&'*C'$1'$2'$&'$C-3 initial egin !l#017 23 fore.er 89 !l#0:!l#3 end initial egin *1013*2013*&013*C013 8 22 *1023*2013*&013*C013 8&2 <finish3 end endmod"le

OUTPUT WA+EFORM :

RESULT: Th"s the design and implementation of Shift registers for .ario"s inp"t and o"tp"t are !arried o"t in Verilog.

DATE: EX.NO: AIM: To implement the program for !o"nter in VHDL "sing Feha.io"ral model. SOFTWARE REQUIRED: Xilinx ISE 9.2i THEORY: G !o"nter is a register !apa le of !o"nting the n"m er of !lo!# p"lses arri.ing at its !lo!# inp"t. Ho"nt represents the n"m er of !lo!# p"lses arri.ed. G spe!ified se$"en!e of states appears as the !o"nter o"tp"t. There are t*o t%pes of Ho"nters' S%n!hrono"s and Gs%n!hrono"s. SYNCHRONOUS COUNTER: There is no !onne!tion et*een o"tp"t of first flip-flop and !lo!# inp"t of the next flipflop. The !ommon !lo!# inp"t is !onne!ted to all of the flip-flops and th"s the% are !lo!#ed sim"ltaneo"sl%. Gs'the !lo!# is sim"ltaneo"sl% gi.en to all flip-flops there is no pro lem of propagation dela%. Hen!e the% are preferred *hen n"m er of flip-flops in!reases. ASYNCHRONOUS COUNTER: The Flip-flops are !onne!ted in s"!h a *a% that o"tp"t of the first flip-flop dri.es the !lo!# for the next flip-flop. Gll the flip-flops are not !lo!#ed sim"ltaneo"sl%. The main dra* a!# is lo* speed as the !lo!# is Bropagated thro"gh n"m er of flip-flops efore it rea!hes last flip-flop.

8 - BIT COUNTER

AYNCHRONOUS RIPPLE UP COUNTER PRO RAM: mod"le pri%a+!l#'$-3 inp"t !l#3 o"tp"t I&J2K $3 >#ff s1+!l#'1'1'$I2K-3 >#ff s2+$I2K'1'1'$I1K-3 >#ff s&+$I1K'1'1'$I2K-3

ASYNCHRONOUS RIPPLE UP COUNTER BLOCK DIA RAM

TRUTH TABLE PRESENT STATE CLOC K 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Q3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Q2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 Q1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 Q0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Q3 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 NEXT STATE Q2 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 Q1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 Q0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0

>#ff sC+$I2K'1'1'$I&K-3 endmod"le mod"le >#ff+!l#' >' #' $-3 inp"t !l#3 inp"t >3 inp"t #3 o"tp"t $3 reg $023 al*a%s 6 +negedge !l#egin if +>002 ?? #001assign $023 else if +>001 ?? #002assign $013 else if +>002 ?? #002assign $0$3 else assign $0:$3 end endmod"le

OUTPUT WA+EFORM :

SYNCHRONOUS DOWN COUNTER

BLOCK DIA RAM

TRUTH TABLE
CLOC K 0 1 2 3 4 5 6 7 PRESENT STATE Q0 0 0 0 0 1 1 1 1 Q1 0 0 1 1 0 0 1 1 Q2 0 1 0 1 0 1 0 1 Q0 1 1 1 1 0 0 0 0 NEXT STATE Q1 1 1 0 0 1 1 0 0 Q2 1 0 1 0 1 0 1 0

SYNCHRONOUS DOWN COUNTER: PRO RAM : mod"le !o"nters%n.eri +!l#' $-3 inp"t !l#3 o"tp"t I2J2K $3 *ire a3 >#ff >1+1'1'!l#'$I2K-3 >#ff >2+$I2K'$I2K'!l#'$I1K-3 assign a0$I2K?$I1K3 >#ff >&+a'a'!l#'$I2K-3 endmod"le mod"le >#ff+>' #' !l#' $-3 inp"t >3 inp"t #3 inp"t !l#3 o"tp"t $3 reg $023 al*a%s6+posedge !l#egin if+>002 ?? #001$023 else if+>001 ??# 002$013 else if+>002 ?? #002$D0$3 else

$D0:$3 end endmod"le (o)*l! #!"#$!%&'567 reg >'#'!l#3 *ire I2J2K$3 s"ganmal a1+>'#'!l#'$-3 initial egin !l#017 23 fore.er89 !l#0:!l#3 end initial egin >017 13#017 13 892 <finish 3 end endmod"le

OUTPUT WA+EFORM :

RESULT: Th"s the program for !o"nters is implemented and the o"tp"t *a.eform is .erified s"!!essf"ll%.

SYSTEM DESI N USIN

PIC MICRO CONTROLLER

PROCEDURE FOR PIC MICOCONTROLLER

STEPS : 1. 5pen the LBLGF IDE VM.&2 2. Bro>e!t-NiOard-4ext-Sele!t BIH1;FMPPG-4ext-4ext-Fro*se-+filename- LED displa%Sa.e "sing +.m!p- Q next Q next Q finish &. File-4e*-Nrite H program Q sa.e the file as +.!- extension C. Gdd so"r!e file is the LED displa% .m!p on the right side-sele!t add files Q so"r!e file is the file t%pes-!li!# o"r filename 9. Exe!"te means s*it!h on the #it at staring itself ;. Bro>e!t-F"ild-F"ild s"!!essf"l is !oming-5FF the #it P. Transfer the pin to the HBR interfa!e side. M. Here D-oSp for LEDAs' H-iSp for s*it!hes 9. Gfter transfer pin' s*it!h 54 the #it press reset-54 s*it!h on!e 12. To to start QBIH programmer-sele!t o"r IH no 11. Fro*se Q +.!- files are !ompiled in @hexA file format. Sele!t o"t file and sele!t open 12. Hommand Q program BIH-finished s"!!essf"ll% in information is !oming. Then s*it!h 5FF and ta#e IH o"tside and fix in the pre.io"s position and s*it!h 54 the #it. Then LED lights gets 54 *ith !onstant dela%. HARDWARE CONNECTIONS : 1. Bo*er s"ppl% of the #it 2. )it *ith HBR &. Honne!t /H to H41 in the !onne!tor C. Honne!t /D to H42 in the !onne!t 9. Honne!t ele.ator to H4& in the !onne!tor

DATE: EX.NO: :

PRO RAM FOR LED DISPLAY

AIM: To *rite a program for LED displa% *ith dela% "sing BIH mi!ro!ontroller. SOFTWARE REQUIRED: LBLGF IDE VM.&2 .ersion soft*are BIH Li!ro!ontroller #it

PRO RAM: Po-# Pi% Allo&.#io% 8define LEDL1 /D9 8define LEDL2 /D2 8define LEDL& /D1 8define LEDLC /D2 8define LEDL9 /D& 8define LEDL; /DC S;i#&'!" Pi% Allo&.#io% 8define HGLLVT4D /H2 8define HGLLVFI/ST /H1 8define HGLLVSEH54D /H2 8define L5VVT4D /H& 8define L5VVFI/ST /HC 8define L5VVSEH54D /H9 D!l.< Ro*#i%! .oid Dela%+"nsigned int rTimeW "nsigned int i'>3 for+i023iDrTime3iXXfor+>023>D12P93>XX-3 Y SU LED for Se!ond Floor US SU LED for First FloorUS SU LED for Tro"nd Floor US SU LED for Hall Se!ond Floor US SU LED for Hall First Floor US SU LED for Hall Tro"nd Floor US SU Hall S*it!h for Tro"nd FloorUS SU Hall S*it!h for First FloorUS SU Hall S*it!h for Se!ond Floor US SU Lo.e S*it!h for Se!ond FloorUS SU Lo.e S*it!h for First FloorUS SU Lo.e S*it!h for Tro"nd Floor US

Lain Loop .oid main+W "nsigned !har temp3 T/ISD 0 2x223 T/ISH 0 2xFF3 B5/TD 0 2x223 *hile+1W LEDL1 0 23 LEDL2 0 23 LEDL& 0 23 Dela%+122-3 LEDL1 013 LEDL2 0 13 LEDL& 0 13 Dela%+122-3 Y Y

SU Define as 5"tp"t Bort SU Define as Inp"t Bort SU Hlear BortUS

US US

SU Hlear Se!ond Floor LED US SU Hlear First Floor LED US SU Tlo* Tro"nd Floor LED US SU Linim"m Dela% US SU Hlear Se!ond Floor LED US SU Hlear Se!ond Floor LED US SU Hlear Se!ond Floor LED US

RESULT: Th"s the o"tp"t for LED displa% is .erified s"!!essf"ll%.

DATE: EX.NO:

LED BLINKIN

USIN

SWITCH

AIM: To *rite a program for LED displa% *ith dela% "sing BIH mi!ro!ontroller. SOFTWARE REQUIRED: LBLGF IDE VM.&2 .ersion soft*are BIH Li!ro!ontroller #it

PRO RAM: *hile+1W if+s*002W LEDL1 0 13 LEDL2 0 23 LEDL& 0 23 Dela%+122-3 LEDL1 023 LEDL2 0 13 LEDL& 0 23 Dela%+122-3 LEDL1 023 LEDL2 0 23 LEDL& 0 13 Dela%+122-3 Y else +s*001W LEDL1 0 23 LEDL2 0 23 LEDL& 0 13 Dela%+122-3 LEDL1 0 23 LEDL2 0 13 LEDL& 0 23 Dela%+122-3 LEDL1 0 13 LEDL2 0 23 SU Hlear Se!ond Floor LED US SU Hlear Se!ond Floor LED US SU Hlear Se!ond Floor LED US SU Hlear First Floor LED US SU Tlo* Tro"nd Floor LED US SU Linim"m Dela% US SU Hlear Se!ond Floor LED US SU Hlear Se!ond Floor LED US SU Hlear Se!ond Floor LED US SU Hlear Se!ond Floor LED US SU Hlear Se!ond Floor LED US SU Hlear Se!ond Floor LED US SU Hlear Se!ond Floor LED US SU Hlear First Floor LED US SU Tlo* Tro"nd Floor LED US SU Linim"m Dela%US SU Hlear Se!ond Floor LED US SU Hlear Se!ond Floor LED US SU Hlear Se!ond Floor LED US

LEDL& 0 23 Dela%+122-3 Y Y Y

SU Hlear Se!ond Floor LED US

RESULT: Th"s the o"tp"t for LED lin#ing is .erified s"!!essf"ll%

DATE: EX.NO: AIM:

PRO RAM FOR ELE+ATOR CONTROL

To *rite a program for Ele.ator *ith dela% "sing BIH mi!ro!ontroller. SOFTWARE REQUIRED: LBLGF IDE VM.&2 .ersion soft*are BIH Li!ro!ontroller #it

PRO RAM:
Po-# Pi% Allo&.#io% SU LED Bin Gllo!ation US 8define LEDL1 /D9 8define LEDL2 /D2 8define LEDL& /D1 8define LEDLC /D2 8define LEDL9 /D& 8define LEDL; /DC SU S*it!hes Bin Gllo!ation US 8define HGLLVT4D /H2 8define HGLLVFI/ST /H1 8define HGLLVSEH54D /H2 8define L5VVT4D /H& 8define L5VVFI/ST /HC 8define L5VVSEH54D /H9 D!l.< Ro*%#i%! .oid Dela%+"nsigned int rTimeW "nsigned int i'>3 for+i023iDrTime3iXXfor+>023>D12P93>XX-3 Y M.i% Loop .oid main+W "nsigned !har temp3 T/ISD 0 2x223 T/ISH 0 2xFF3 SU Define as 5"tp"t Bort US SU Define as Inp"t Bort US SU LED for Se!ond Floor SU LED for First Floor SU LED for Tro"nd Floor SU LED for Hall Se!ond Floor SU LED for Hall First Floor SU LED for Hall Tro"nd Floor US US US US US US

SU Hall S*it!h for Tro"nd Floor US SU Hall S*it!h for First Floor US SU Hall S*it!h for Se!ond Floor US SU Lo.e S*it!h for Se!ond Floor SU Lo.e S*it!h for First Floor US SU Lo.e S*it!h for Tro"nd Floor US US

B5/TD 0 2x223 LEDL& 0 13 *hile+1W if+HGLLVT4D 00 1W LEDLC 0 23 LEDL9 0 23 LEDL; 0 13 Dela%+&2-3 LEDL1 0 23 LEDL2 0 23 LEDL& 0 13 TndJ temp 0 23 *hile+temp Z0 1W if+L5VVFI/ST 00 1W LEDLC 0 23 LEDL9 0 23 LEDL; 0 23 Dela%+C2-3 LEDL1 0 23 LEDL2 0 13 LEDL& 0 23 temp 0 13 goto First3 Y if+L5VVSEH54D 00 1W LEDLC 0 23 LEDL9 0 23 LEDL; 0 23 Dela%+C2-3 LEDL1 0 13 LEDL2 0 23 LEDL& 0 23 temp 0 13 goto Se!ond3 Y if+HGLLVFI/ST 00 1W LEDLC 0 23 LEDL9 0 13 LEDL; 0 23 Dela%+&2-3 LEDL1 0 23 LEDL2 0 13 LEDL& 0 23 temp 0 13 goto First3 Y

SU Hlear Bort SU Tlo* Tro"nd Floor LED SUUUUUUUUU Bress SN1 - Tro"nd Floor UUUUUUUUUUUS SU Hlear Se!ond Floor LED US SU Hlear First Floor LED US SU Tlo* Tro"nd Floor LED US SU Linim"m Dela% US SU Hlear Se!ond Floor LED US SU Hlear Se!ond Floor LED US SU Hlear Se!ond Floor LED US SU Nait "ntill an% s*it!h pressed US

US US

if+HGLLVSEH54D 00 1W LEDLC 0 13 LEDL9 0 23 LEDL; 0 23 Dela%+&2-3 LEDL1 0 13 LEDL2 0 23 LEDL& 0 23 temp 0 13 goto Se!ond3 Y if+HGLLVT4D 00 1W LEDLC 0 23 LEDL9 0 23 LEDL; 0 13 Dela%+&2-3 LEDL1 0 23 LEDL2 0 23 LEDL& 0 13 temp 0 13 goto Tnd3 Y Y Y SUUUUUUUUU Bress SN2 - First Floor UUUUUUUUUUUS if+HGLLVFI/ST 00 1W LEDLC 0 23 LEDL9 0 13 LEDL; 0 23 Dela%+&2-3 LEDL1 0 23 LEDL2 0 13 LEDL& 0 23 FirstJ temp 0 23 *hile+temp Z0 1W if+L5VVT4D 00 1W LEDLC 0 23 LEDL9 0 23 LEDL; 0 23 Dela%+C2-3 LEDL1 0 23 LEDL2 0 23 LEDL& 0 13 temp 0 13 goto Tnd3

Y if+L5VVSEH54D 00 1W LEDLC 0 23 LEDL9 0 23 LEDL; 0 23 Dela%+C2-3 LEDL1 0 13 LEDL2 0 23 LEDL& 0 23 temp 0 13 goto Se!ond3 Y if+HGLLVFI/ST 00 1W LEDLC 0 23 LEDL9 0 13 LEDL; 0 23 Dela%+&2-3 LEDL1 0 23 LEDL2 0 13 LEDL& 0 23 temp 0 13 goto First3 Y if+HGLLVSEH54D 00 1W LEDLC 0 13 LEDL9 0 23 LEDL; 0 23 Dela%+&2-3 LEDL1 0 13 LEDL2 0 23 LEDL& 0 23 temp 0 13 goto Se!ond3 Y if+HGLLVT4D 00 1W LEDLC 0 23 LEDL9 0 23 LEDL; 0 13 Dela%+&2-3 LEDL1 0 23 LEDL2 0 23 LEDL& 0 13 temp 0 13 goto Tnd3 Y Y Y

SUUUUUUUUU Bress SN& - Se!ond Floor UUUUUUUUUUUS if+HGLLVSEH54D 00 1W LEDLC 0 13 LEDL9 0 23 LEDL; 0 23 Dela%+&2-3 LEDL1 0 13 LEDL2 0 23 LEDL& 0 23 Se!ondJ temp 0 23 *hile+temp Z0 1W if+L5VVFI/ST 00 1W LEDLC 0 23 LEDL9 0 23 LEDL; 0 23 Dela%+C2-3 LEDL1 0 23 LEDL2 0 13 LEDL& 0 23 temp 0 13 goto First3 Y if+L5VVT4D 00 1W LEDLC 0 23 LEDL9 0 23 LEDL; 0 23 Dela%+C2-3 LEDL1 0 23 LEDL2 0 23 LEDL& 0 13 temp 0 13 goto Tnd3 Y if+HGLLVFI/ST 00 1W LEDLC 0 23 LEDL9 0 13 LEDL; 0 23 Dela%+&2-3 LEDL1 0 23 LEDL2 0 13 LEDL& 0 23 temp 0 13 goto First3 Y if+HGLLVSEH54D 00 1W

LEDLC 0 13 LEDL9 0 23 LEDL; 0 23 Dela%+&2-3 LEDL1 0 13 LEDL2 0 23 LEDL& 0 23 temp 0 13 goto Se!ond3 Y if+HGLLVT4D 00 1W LEDLC 0 23 LEDL9 0 23 LEDL; 0 13 Dela%+&2-3 LEDL1 0 23 LEDL2 0 23 LEDL& 0 13 temp 0 13 goto Tnd3 Y Y Y Y Y

RESULT: Th"s the program has een *ritten in BIH mi!ro!ontroller for Ele.ator Hontrol *ith dela% and .erified s"!!essf"ll%.

IMPLEMENTATION OF ADAPTI+E FILTER= PERIODO RAM AND MULTIRATE SYSTEM IN MATLAB

DATE: EX.NO: AIM:

ADAPTI+E FILTER

To sim"late an adapti.e digital filter "sing LGTLGF. SOFTWARE REQUIRED:

LGTLGF P.&

THEORY: Gdapti.e filter are digital filters that perform digital signal pro!essing and adopt their performan!e ased on the inp"t signal. It is a filter that self-ad>"sts its transfer f"n!tion a!!ording to an optimiOation algorithm dri.en % an error signal.. The adapti.e filter "ses feed a!# in the form of an error signal to refine its transfer f"n!tion to mat!h the !hanging parameters. Gs the po*er of digital signal pro!essors has in!reased' adapti.e filters ha.e e!ome m"!h more !ommon and are no* ro"tinel% "sed in de.i!es s"!h as mo ile phones and other !omm"ni!ation de.i!es' !am!orders and digital !ameras' and medi!al monitoring e$"ipment Appli&.#io%" o, .).p#i>! ,il#!-" 4oise !an!ellation Signal predi!tion Gdapti.e feed a!# !an!ellation E!ho !an!ellation

AL ORITHM: 1. Honstr"!t an mUn matrix +i.e 1922- matrix. 2. Design a &1th order lo* pass FI/ digital filter and otrain the filter !oeffi!ients in . &. L"ltipl% the matrix .al"e % 2.1 and ha.e it in n. C. Rsing filter f"n!tion the data o tain from FI/ filter. 9. Honstr"!t an identit% matrix of siOe &2. ;. Honstr"!t an FI/ /LS adapti.e filter. P. Filter the !oeffi!ients of the o"tp"t of the a o.e. M. Blot the filtered data and original data.

PRO RAM : !l!3 !lose all3 x0randn+1'922-3 0fir1+&1'2.9-3 n02.1Urandn+1'922-3 d0filter+ '1'x-Xn3 p2012Ue%e+&2-3 lam02.993 ha0adaptfilt.rls+&2'lam'p2-3 I% eK0filter+ha'x'd-3 s" plot+2'1'1-3 plot+1J922'Id3%3eK-3 title+7s%stem identifi!ation of fir filter7-3 legend+7desired7'7o"tp"t7'7error7-3 xla el+7time index7-3 %la el+7signal .al"e7-3 s" plot+2'1'2-3 stem+I .7'ha.!oeffi!ients7K-3 legend +7a!t"al7'7estimation7-3 xla el+7!oeffi!ient 87-3 %la el+7!oeffi!ient .al"e7-3 grid on3

OUTPUT WA+EFORM :

RESULT: Th"s the implementation of adapti.e filter has een .erified s"!!essf"ll% in LGTLGF.

DATE: EX.NO: AIM:

PERIODO RAM

To design and implement the periodogram "sing LGTLGF SOFTWARE REQUIRED : LGTLGF P.& THEORY : The periodogram is an estimate of the spe!tral densit% of a signal. The term *as !oined % Grth"r S!h"ster in 1M9M as in the follo*ing $"oteJ [ THE BE/I5D5T/GL. It is !on.enient to ha.e a *ord for some representation of a .aria le $"antit% *hi!h shall !orrespond to the 7spe!tr"m7 of a l"mino"s radiation. I propose the *ord periodogram' and define it more parti!"larl% in the follo*ing *a%J Let

*here T ma% for !on.enien!e e !hosen to e e$"al to some integer m"ltiple of ' and plot a !"r.e *ith as a s!iss\ and

as ordinates3 this !"r.e' or' etter' the spa!e et*een this !"r.e and the axis of a s!iss\' represents the periodogram of f+t-.

PRO RAM : 40223 n02J4-13 O0&Urandn+1'4-3 x0s$rt+12-Uexp+1iU2UpiU2.19Un- X s$rt+22-U exp+1iU2UpiU2.2Un-XO3 X01S4Ua s+fft+x'29;--.]23 f0linspa!e+2'2'29;-3 s" plot+211-3 plot+f'12Ulog12+X--

OUTPUT WA+EFORM :

RESULT: Th"s the implementation of periodogram has een .erified s"!!essf"ll% in LGTLGF.

DATE : EX.NO:

UPSAMPLIN

AND DOWN SAMPLIN

AIM : To design and implement the de!imation and interpolation "sing LGTLGF.

SOFTWARE REQUIRED: LGTLGF P.& THEORY: The pro!ess of de!reasing the sampling rate is !alled de!imation. De!imation is do*n sampling *ith appropriate filtering.to de!imate +do*n sample- a signal x +n- % a fa!tor of L implies !olle!ting e.er% Lth .al"e of x+n- to a ne* signal. This is gi.en % %+n-0x+Ln-.Do*n sampling % an integer fa!tor L implies retaining one sample and dis!arding the remaining L-1 samples and this is done for e.er% samples. The pro!ess of in!reasing the sampling rate is !alled Interpolation. Interpolation is "p sampling *ith appropriate filtering.to interpolate+"p sample- a signal x+n- % a fa!tor of 4 implies !olle!ting e.er% 4th .al"e of x+n- to a ne* signal. This is gi.en % %+n-0x+nS4-.

PRO RAM: Do;%".(pli%/ : !lear all3 4092 n02J1J4-13 x0sin+2UpiUnS22-Xsin+2UpiUnS19-3 L023 x10x+1JLJ4-3 n101J1J4SL3 s" plot+2'1'1-3 stem+n'x-3 title+7inp"t se$"en!e7-3 xla el+7n7-3 %la el+7amp7-3 s" plot+2'1'2-3 stem+n1'x1-3 title+7do*nsampled se$"en!e7-3 xla el+7n7-3 %la el+7amp7-3 OUTPUT WA+EFORM :

Up".(pli%/ : !lear all3 40123 n02J1J4-13 x0sin+2UpiUnS12-Xsin+2UpiUnS9-3 L0&3 x10IOeros+1'LU4-K3 n101J1JLU43 >01JLJLU43 x1+>-0x3 s" plot+2'1'1-3 stem+n'x-3 title+7inp"t se$"en!e7-3 xla el+7n7-3 %la el+7Gmp7-3 s" plot+2'1'2-3 stem+n1'x1-3 title+7"psmapled se$"en!e7-3 xla el+7n7-3 %la el+7Gmp7-3 OUTPUT WA+EFORM :

RESULT: Th"s the design and implementation of the Do*nsampling and Rpsampling has een !arried o"t "sing LGTLGF.

SIMULATION OF QMF USIN

MATLAB

DATE: EX.NO: AIM:

QUADRATURE MIRROR FILTER

To sim"late a $"adrat"re mirror filter "sing LGTLGF. SOFTWARE REQUIRED: LGTLGF P.9 THEORY: G $"adrat"re mirror filter is a filter most !ommonl% "sed to implement a filter an# that splits an inp"t signal into t*o ands. The res"lting high- pass and lo*-pass signals are often red"!ed % a fa!tor of 2'gi.ing a !riti!all% sampled t*o !hannel representation of the original signal. In other *ords' the po*er s"m of the high-pass and lo*-pass filters is e$"al to 1.The filter responses are s%mmetri! AL ORITHM: 1. Load the d 12 s!aling filter into arra%. 2. Blot the filter !o-effi!ients. &. =LF +- !hanges the sign of the entries of the re.ersed .e!tor filter !o-effi!ients. C. Blot the a o.e !o-effi!ients 9. 5 tain the dis!rete Fo"rier transform .e!tor of the original filter !o-effi!ients and the re.ersed !o-effi!ients "sing fft+-. ;. Hal!"late the magnit"de response of the a o.e .al"es and plot them. P. Hhe!# for the orthogonall% !ondition and plot them. PRO RAM: load d 123 s" plot +&21-3 stem +d 12-3 title +7d 12 lo*-pass filter7-3 $mfd 12 0 $mf+d 12-3 s" plot+&22-3 stem+$mfd 12-3 title+7=mf d 12 filter7-3 m0fft+d 12-3 mt0 fft+$mfd 12-3 fre$0 I1Jlength+d 12-KSlength +d 12-3 s" plot +&2&-3

plot+fre$'a s+m--3 title+7Transfer mod"l"s of d 127-3 s" plot+&2C-3 plot+fre$'a s+mt--3 title+7Transfer mod"l"s of $mfd 127-3 s" plot+&29-3 plot+fre$'a s+m-.]2X a s+mt-.]2-3 title+7!he!# $mf !ondition for d 12 and $mfd 127-3 xla el+7a s fft+d 12--]2-X a s fft+$mf+d 12--]2017-3

OUTPUT WA+EFORM :

RESULT: Th"s the $"adrat"re mirror filter has een designed and .erified s"!!essf"ll%.

DATE : EX.NO :

ANALO

TO DI ITAL CON+ERTER USIN

1?-BIT

MICROPROCESSOR
AIM: To *rite and exe!"te the program for GDH "sing M2M; trainer #it. APPARATUS REQUIRED: THEORY: M2M; is a 1; it' third generation mi!ropro!essor and is s"ita le for an ex!eptionall% *ide spe!tr"m of mi!ro!omp"ter appli!ations. This flexi ilit% is one of most o"tstanding !hara!teristi!s. M2M; has got 1; data lines and 22 address lines. The lo*er 1; address lines are m"ltiplexed *ith 1; data lines. Hen!e it e!omes ne!essar% to lat!h the address lines. This is done % "sing PC LS &P&. In fa!t se.eral of the C2 HBR pins ha.e d"al f"n!tions that are sele!ted % a strapping pin. In this #it M2M; is "sed in the max. mode +L4SLx inp"t held logi!all% lo*-. The M2MM is designed *ith an M- it external path to memor% and IS5. Ex!ept that the M2M; !an transfer 1; its at a time' the t*o pro!essors ? soft*are are identi!al in almost e.er% respe!t. Soft*are identi!al in almost e.er% respe!t. alteration. Soft*are *ritten for one HBR *ill exe!"te on the other *itho"t The t*o pro!essors are designed to operate *ith the M2M9 IS5 pro!essors M2M; mi!ropro!essor trainer #it- 4V99M;G. SLBS Bo*er s"ppl%

and other pro!essors in m"ltipro!essing and distri "ted pro!essing s%stems. PROCEDURE: 1. Honne!t the External SLBS Bo*er S"ppl% to GH Bo*er and 9 pin !onne!tor to the left side on4V99M;G )it. 2. S*it!h on the Bo*er S"ppl% at the rear end of SLBS s"ppl%.

&. G messageQ4V99M;G M2M; Li!. Tr. *ill !ome on displa% +B/ESS /ESET if %o" do not get-4V99M;G M2M; Li!. Tr-. C. 4o*4V99M;G)it is read% for the "ser7s experiments for )e% oard Lode !ommands.
5. Bress reset enter G starting address of the program to enter the program.

;. T%pe the program in GLB. 7. Then press reset enter T starting address of the t%ped program to exe!"te. M. F% ad>"sting potentiometer on trainer #it the inp"t .al"e !an e !hanged and the !orresponding o"tp"t *ill e o tained on LHD displa%. /eset enter R+to .ie* program/eset enter L+to mo.e from one memor% to other/eset enter D+d"mp-to enter dire!t op!ode/eset enter G+assem le-.

PRO RAM: MEMORY ADDRESS 2C22 2C22 LABEL MNEMONICS L5V GL'9MH 5RT P;H'GL COMMENTS I4TIGLISE M299 BG ? BH Rpper as Inp"t ?BF ? BH Lo*er as 5"tp"t Sele!t HhannelG2 Send S5H and GLE B"lse and Hhe!# for E5H Hlear LHD SELEHT LHD L5HGTI54 Send Data to LHD Sele!tHhannelG1

2C2C 2C2;

HH1J

L5V GL'22H HGLL GTD

2C29 2C2H 2C2E 2C11 HH2J

HGLL HLEG/ L5V FL'M2H HGLL GTDGT L5V GL'21H

2C1& 2C1;

HGLL GTD L5V FL'2M9H SELEHT LHD L5HGTI54

2C1M 2C1F 2C1D 2C22 2C22 2C29 2C29 2C2G 2C2H 2C2F 2C&1 2C&C 2C&; 2C&9 2C&F 2C&E 2CC2 2CC& HHPJ HH;J HH9J HHCJ HH&J

HGLL GTDGT L5V GL'22H HGLL GTD L5V FL'MGH HGLL GTDGT L5V GL'2&H HGLL GTD L5V FL'MFH HGLL GTDGT L5V GL'2CH HGLL GTD L5V FL'2H2H HGLL GTDGT L5V GL'29H HGLL GTD L5V FL'2H9H HGLL GTDGT L5V GL'2;H Sele!t HhannelG; SELEHT LHD L5HGTI54 Sele!t HhannelG9 SELEHT LHD L5HGTI54 Sele!t HhannelGC SELEHT LHD L5HGTI54 Sele!t HhannelG& SELEHT LHD L5HGTI54 Sele!t HhannelG2

2CC9 2CCM

HGLL GTD L5V FL'2HGH SELEHT LHD L5HGTI54

2CCG 2CCD 2CCF 2C92 2C9C 2C9P HHMJ

HGLL GTDGT L5V GL'2PH HGLL GTD L5V FL'2HFH HGLL GTDGT (LB HH1 SELEHT LHD L5HGTI54 Sele!t HhannelGP

2C9G 2C9H 2C9E 2C;2 2C;2 2C;C 2C;; 2C;M 2C;G 2C;H E5H1J GTDJ

5RT P2H'GL L5V GL'22H 5RT PCH'GL L5V GL'2&H 5RT PCH'GL L5V GL'22H 5RT PCH'GL I4 GL'PCH

5RT GT B5/T-F TIVE S5H ? GLE BRLSE GS 2 5RT GT B5/T-H TIVE S5H ? GLE BRLSE GS 1 5RT GT B5/T-H TIVE S5H ? GLE BRLSE GS 2 5RT GT B5/T-H /EGD E5H F/5L B5/T-H HHEH) E5H GT BHC FIT (RLB TILL E5H01

G4D GL'12H (^ E5H1

2C;E 2CP2 2CP2 2CPC 2CP9 HLEG/J

L5V GL'2CH 5RT PCH'GL I4 GL'P2H /ET DF9GH'PHH' 2F2H22H2F2H HGLL2F222JF2PH /ET L5VGH'22H

TIVE 5RTBRT E4GFLE GS 1 5RT GT B5/T-H

/EGD M FIT GDH DGTG F/5LB5/T-G

Hlear LHD S!reen

2CPG 2CPF GTDGTJ

B"t 22 in GH HGLL DISBLG_ /5RTI4E Ti.e some time

DF9GH'9CH' 2F2H'22H'2F2H 3 HGLL F222JF29C L5VHX'2999H 2CM2

RESULT: Th"s the program for Gnalog to Digital Hon.erter is *ritten and its o"tp"t is .erified s"!!essf"ll%.

DATE: EX.NO: AIM:

ECHO CANCELLATION USIN

ADAPTI+E FILTER

To design and implement the program for e!ho !an!ellation "sing adapti.e filter. SOFTWARE REQUIRED: ;P1&DS) St"dio &.1 TLS&22H;P1& THEORY: G signal *hi!h !ontains error or noise in the a!t"al signal.The differen!e et*een the a!t"al .al"e and the estimated .al"e is !alled Error.To minimiOe the error *e !an "se an .aria le adapti.e filter to ma#e estimated .al"e approximatel% e$"al to original .al"e.In the noise !an!ellation gi.e one inp"t dire!tl% and gi.e se!ond inp"t *ith dela%. GDGBTIVE GLT5/ITHLJ It needs e+n- e!a"se it is "sed to meas"re its performan!e and determine ho* the filter !oeffi!ients sho"ld e modified.Nitho"t error the filter *o"ld not e a le to adopt.The effi!ien!% of the adapti.e filter depending "pon three fa!tors' 1.FI/ 5/ II/ 2.Filter Str"!t"re &.The *a% in *hi!h performan!e meas"re is define in terms of mean s$"are error or least s$"are error. 5ne of the ad.antage of this adapti.e noise !an!eller o.er a *iener filter is that it ma% e "sed *hen the pro!esses are non stationar% and the #e% to the s"!!essf"l operation is the a.aila ilit% of a referen!e signal that ma% e "sed to estimate the additi.e noise.

PROCEDURE FOR DSP PROCESSOR INTRODUCTION: The DSB pro!essor is also !alled as Floating Boint pro!essor.The inp"t !apa!it% is from M to &2 its.It has 912 /GL and ;CLF /GL memor% and speed is 229 LHO.It is *idel% in a"dio pro!essing and medi!al appli!ations.The ad.antage of this pro!essor is faster and a!!"ra!% d"e to parallel pro!essing. The DSB pro!essor has C ports. 1. Headphone !onne!tion 2. Line o"tp"t &. Line inp"t C. Li!rophone inp"t. Here head !onne!tion is "sed as o"tp"t and mi!rophone is "sed as inp"t for a"dio pro!essing.Line o"tp"t and line inp"t is "sed for H/5 !onne!tions. STEPS 1. Sele!t the ;P1& DS) diagnosti!s' !li!# start to !he!# the tools and finished. 2. 5pen ;P1&DS) st"dio &.1 &. For hard*are !onne!tion Q To to de "g Q sele!t @!onne!tA C. To to pro>e!t Q` 4e*-` pro>e!t name as [e!ho!ana sele!t lo!ation and !reate a ne* folder in des#top-` sele!t pro>e!t t%pes-`+.o"t--`sele!t series-`;PXX then Hli!# o# 9. Toto file Q`ne*-`sele!t so"r!e file ;. Nrite the program on that file-`sa.e file *ith+.!- extension in o"r folder

T5 H/EGTE G S5R/HE FILEJ P. /ight !li!# on o"r pro>e!t-` sele!t add file option- `add o"r so"r!e file in the pro>e!t M. Gdd s"pporting files from D-dri.e-` ne!essar% file Q`sele!t all files and paste it in o"r folder 9. To to li raries Q` sele!t ds#;P1& sl.li !li!# open 12. /ight !li!# on pro>e!t Q` sele!t @s!an all files dependen!iesA H/EGTE DSBSFIGS H54FITR/GTI54 F5/ GRDI5 GBBLIHGTI54J 11. To to file Q` sele!t ne* Q` sele!t DSBSFias !onfig"ration for e!ho !an!eller and sele!t o"r file @;P1&.!d A Q `!li!# o#-`a ne* *indo* *ill !ome. 12. Sa.e that *indo* Q`e!ho!an.!d and add the file to DSBSFias !onfig"ration in the pro>e!t +left-. 1&. To to pro>e!t Q` re "ild all Q` a "ild !omplete message *ill !ome. 1C. To to file Q` load program Q `sele!t o"r file as @e!ho!an.o"tA !li!# open. 19. To to de "g Q` r"n +F9- Q` a green signal *ill !ome. STEPS TO CHECK OUTPUT: 1. Honne!t Li! or pla% an% song on Line-in of DS). 2. Honne!t the headphone on Headphone of DS). &. To anal%se the o"tp"t' ma#e "se of Dip-s*it!hes. C. Bress DIB-s*it!h1' listen the inp"t signal. 9. Bress DIB-s*it!h2' listen the e!ho signal. ;. Bress DIB-s*it!h&' e!ho-!an!ellation algorithm *ill e applied and listen the original inp"t. P. _o" !an listen the o"tp"t onl% *hen DIB-s*it!hes are pressed.

PRO RAM: 8in!l"de ,e!ho1!fg.h, 8in!l"de ,ds#;P1&.h, 8in!l"de ,ds#;P1&Vai!2&.h, 8define 4 &2 8define eta 2.& 8define gain 2 Rint&2 *I4K3 Rint&2 dela%I4K3 SS*eights for adapt filter SSinp"t "ffer to adapt filter SS .aria le de!laration SS no. of samples SS8 of *eights +!oeffi!ientsSS it is a FI5S file SSthis file is added to initialiOe the DS);P1&

Rint&2 E' %n' inp"t' e!ho1' l!e!hoVo"tp"t' r!e!hoVo"tp"t3 short "fferlength 0 C2223 sampled a"dio signal short "fferIC222K3 short "fferlength1 0 M2223 short "ffer1IM222K3 short "fferlength2 0 122223 short "ffer2I12222K3 short "fferlength& 0 1;2223 short "ffer&I1;222K3 short i 0 2'> 0 2'# 0 2'l023 short amplit"de 01'a3 Rint&2 E!hoV!an!ellation+Rint&2 p' Rint&2 $-3 passes the inp"t .al"es to the f"n!tion

Rint&2 linVinp"t'rinVinp"t'linVo"tp"t' rinVo"tp"t' le!hoVo"tp"t're!hoVo"tp"t3 SS "ffers of different "fferlengths to store the

SS its pass % .al"e f"n!tion' means it

SU Hode! !onfig"ration settings US DS);P1&VGIH2&VHonfig !onfig 0 W 2x221P' SU 2 DS);P1&VGIH2&VLEFTI4V5L Left line inp"t !hannel .ol"me US b 2x221P' SU 1 DS);P1&VGIH2&V/ITHTI4V5L /ight line inp"t !hannel .ol"me USb 2x21f9' SU 2 DS);P1&VGIH2&VLEFTHBV5L Left !hannel headphone .ol"me US b 2x21f9' SU & DS);P1&VGIH2&V/ITHTHBV5L /ight !hannel headphone .ol"me US b 2x2219' SU C DS);P1&VGIH2&VG4GBGTH 2x2221' SU 9 DS);P1&VGIH2&VDITBGTH 2x22C&' SU P DS);P1&VGIH2&VDITIF 2x2221 SU 9 DS);P1&VGIH2&VDITGHT Y3 .oid main+W DS);P1&VGIH2&VHode!Handle hHode!3 DS);P1&Vinit+-3 DS);P1&VLEDVinit+-3 DS);P1&VDIBVinit+-3 DS);P1&VGIH2&VsetFre$+hHode!'1-3 fre$"en!% at M)HO *hile+1W *hile +ZDS);P1&VGIH2&Vread+hHode!'?linVinp"t--3 from the left inp"t !hannel of Hode! *hile +ZDS);P1&VGIH2&Vread+hHode!'?rinVinp"t--3 from the right inp"t !hannel of Hode! rinVinp"t0linVinp"t3 if+DS);P1&VDIBVget+2-002SS left ? right !hannel inp"ts are e$"al SS if Dip-s*it!h2 is pressed SS /ead a 1;- it sample SS /ead a 1;- it sample hHode! 0 DS);P1&VGIH2&VopenHode!+2' ?!onfig-3 SS H5DEH initialiOation SS DS);P1& initialiOation SS LED initialiOation SS DIB initialiOation SSStart the !ode! SSSetting sampling Gnalog a"dio path !ontrol US Digital a"dio path !ontrol US b b b b

2x2222' SU ; DS);P1&VGIH2&VB5NE/D5N4 Bo*er do*n !ontrol US Digital a"dio interfa!e format US b Digital interfa!e a!ti.ation US 2x222&' SU M DS);P1&VGIH2&VSGLBLE/GTE Sample rate !ontrol US

W linVo"tp"t0linVinp"t3 !hannel *hile +ZDS);P1&VGIH2&V*rite+hHode!'rinVo"tp"t--3 right !hannel DS);P1&VLEDVon+2-3 Y else DS);P1&VLEDVoff+2-3 5FF if+DS);P1&VDIBVget+1-002W le!hoVo"tp"t0+short-e!ho+?linVinp"t-3 there and o"tp"t is e!ho of inp"t *hile +ZDS);P1&VGIH2&V*rite+hHode!'le!hoVo"tp"t--3 !hannel *hile +ZDS);P1&VGIH2&V*rite+hHode!'re!hoVo"tp"t--3 right !hannel DS);P1&VLEDVon+1-3 Y else DS);P1&VLEDVoff+1-3 W r!e!hoVo"tp"t0l!e!hoVo"tp"t3 l!e!hoVo"tp"t0 E!hoV!an!ellation+linVinp"t'le!hoVo"tp"t-3 SS e!ho-!an!ellation algorithm *hile +ZDS);P1&VGIH2&V*rite+hHode!'l!e!hoVo"tp"t--3 SS Send a 1;- it sample to the left !hannel *hile +ZDS);P1&VGIH2&V*rite+hHode!'r!e!hoVo"tp"t--3 SS Send a 1;- it sample to the right !hannel DS);P1&VLEDVon+2-3 Y SSif the Dip-s*it!h is not pressed Led1 remains 5FF if+DS);P1&VDIBVget+2-002-SS if Dip-s*it!h2 is pressed SS led1 gets 54 SS Send a 1;- it sample to the SS Send a 1;- it sample to the left SS!alling the f"n!tione!ho+ -' exe!"tion goes SS if Dip-s*it!h1 is pressed SSif the Dip-s*it!h is not pressed Led2 remains SS led2 gets 54 SS Send a 1;- it sample to the SS o"tp"t is same as inp"t SS Send a 1;- it sample to the left *hile +ZDS);P1&VGIH2&V*rite+hHode!'linVo"tp"t--3

else DS);P1&VLEDVoff+2-3 SSif the Dip-s*it!h is not pressed Led2 remains 5FF if+DS);P1&VDIBVget+&-002-SS if Dip-s*it!h& is pressed W *hile +ZDS);P1&VGIH2&V*rite+hHode!'l!e!hoVo"tp"t--3 SS Send a 1;- it sample to the left !hannel *hile +ZDS);P1&VGIH2&V*rite+hHode!'r!e!hoVo"tp"t--3 SS Send a 1;- it sample to the right !hannel DS);P1&VLEDVon+&-3 Yelse DS);P1&VLEDVoff+&-3 SSif the Dip-s*it!h is not pressed Led& remains 5FF YY SS F"n!tion for E!ho-!an!ellation Rint&2 E!hoV!an!ellation+Rint&2 linVinp"t'Rint&2 le!hoVo"tp"t- SSthe !ontrol passes to the f"n!tion E!hoV!an!ellation+ -' !alled % a o.e.? its !all % .al"e f"n!tion W inp"t0linVinp"t3 e!ho10le!hoVo"tp"t3 dela%I2K0e!ho13 for +a 0 23 a D 43 aXXW %n X0 +*IaK U dela%IaK-3 E 0 +inp"t - e!ho1--%nUgain 3 Y for +a 0 4-13 a `0 23 a--W *IaK 0 *IaK X etaUEUdela%IaK3 dela%IaK 0 dela%Ia-1K3 Y l!e!hoVo"tp"t 0 E3 ret"rnl!e!hoVo"tp"t3 SS program exe!"tion goes a!# to the f"n!tion !alled and then again starts listening for next !all and this pro!ess goes on Y SS"pdate *eights SS"pdate dela% samples SSto "pdate *eights and dela%s SSe!ho m"ltiplied *ith the *eights for adapt filter SS store the inp"t signal into a .aria le SS store the e!ho signal into e!ho1 .aria le SSnoise as inp"t to adapt FI/ SSto !al!"late o"t of adapt FI/

SS F"n!tion to perform E!ho effe!t signedint e!ho+signed int xa o.e spe!ified f"n!tion W x 0 linVinp"t3 le!hoVo"tp"t 0x X 2.CUamplit"deU "fferIiKX2.&Uamplit"deU "ffer1I>KX 2.2Uamplit"deU "ffer2I#KX 2.1Uamplit"deU "ffer&IlK3 "fferIiK 0 x3 "ffer1I>K 0 "fferIiK3 "ffer2I#K 0 "ffer1I>K3 "ffer&IlK 0 "ffer2I#K3 iXX3 >XX3 #XX3 lXX3 if+i `0 "fferlength- i 0 23 if+> `0 "fferlength1- > 0 23 if+# `0 "fferlength2- # 0 23 if+l `0 "fferlength&- l 0 23 ret"rnle!hoVo"tp"t3 Y SS program exe!"tion goes a!# to the f"n!tion !alled and then again starts listening for next !all and this pro!ess goes on SSf"n!tion exe!tion !omes to e!ho+-' *hi!h is !alled %

RESULT: Th"s the 5"tp"t for E!ho Han!ellation is Verified S"!!essf"ll%.

DATE: EX.NO:

MEALY-+ERILO

FSM

AIM: To design and implement the Verilog HDL program for finite state ma!hine "sing meal% !ir!"it. SOFTWARE REQUIRED: 1. Xilinx 9.&2 . 2. TLS &22;H;P1& Trainer #it THEORY: G Fi%i#!-"#.#! (.&'i%! 5FSM6 is a mathemati!al model of !omp"tation "sed to design oth !omp"ter programs and se$"ential logi! !ir!"its. It is !onsidered as an a stra!t ma!hine that !an e in one of a finite n"m er of states. The ma!hine is in onl% one state at a time3 the state it is in at an% gi.en time is !alled the !"rrent state. It !an !hange from one state to another *hen initiated % a triggering e.ent or !ondition' this is !alled a transition. G parti!"lar FSL is defined % a list of its states' and the triggering !ondition for ea!h transition. Simple examples are .ending ma!hines *hi!h dispense prod"!ts *hen the proper !om ination of !oins are deposited' ele.ators *hi!h drop riders off at "pper floors efore going do*n' traffi! lights *hi!h !hange se$"en!e *hen !ars are *aiting' and !om ination lo!#s *hi!h re$"ire the inp"t of !om ination n"m ers in the proper order. The FSL "ses onl% inp"t a!tions' i.e.' o"tp"t depends on inp"t and state. The "se of a Leal% FSL leads often to a red"!tion of the n"m er of states. The next state and o"tp"t of an FSL is a f"n!tion of the inp"t and of the !"rrent state.

RTL SCHEMATIC DIA RAM :

9@9 STATE DIA RAM :

^E/5 I2K

9@9 1@9

54E 1 I2K

1@1

PRO RAM: mod"le .mn+!l#'reset'in'one'state'nextVstate'Oero'o"t-3 inp"t !l#'reset'in'one'Oero3 o"tp"t o"t'state'nextVstate3 reg o"t3 reg state3 reg nextVstate3 al*a%s6 +posedge !l#if +reset- state 0 Oero3 else state 0 nextVstate3 al*a%s6 +in or state!ase +stateOeroJ egin o"t 0 23 if +innextVstate 0 one3 else nextVstate 0 Oero3 end oneJ if +inegin nextVstate0one3 o"t 0 13 end else

egin nextVstate 0 Oero3 o"t 0 23 end end!ase endmod"le

OUTPUT WA+EFORM :

RESULT : Th"s the program for FSL in .erilog is implemented and the o"tp"t*a.eform is .erified.