3d chip design

CONTENTS
1. Introduction 2. Motivation for 3-D ICs 3. Scope of this study 4. Area and performance estimation of 3-D ICs . Cha!!enges for 3-D Integration ". #vervie$ of 3-D IC techno!ogy %. &resent scenario of the 3-D IC industry '. Advantages of 3-d memory (. App!ications of 3-D ICs 1). *uture of 3-D IC industry 11. Conc!usion 12. +eference

3d chip design

ABSTRACT
,he unprecedented gro$th of the computer and the Information

techno!ogy industry is demanding -ery .arge Sca!e Integrated /-.SI0 circuits $ith increasing functiona!ity and performance at minimum cost and po$er dissipation. -.SI circuits are 1eing aggressive!y sca!ed to meet this Demand2 $hich in turn has some serious pro1!ems for the semiconductor industry. Additiona!!y heterogeneous integration of different techno!ogies in one sing!e chip /SoC0 is 1ecoming increasing!y desira1!e2 for $hich p!anar /2-D0 ICs may not 1e suita1!e. 3-D ICs are an attractive chip architecture that can a!!eviate the interconnect re!ated pro1!ems such as de!ay and po$er dissipation and can a!so faci!itate integration of heterogeneous techno!ogies in one chip /SoC0. Introduction of 3-D ICs2 the $or!d of chips may never !oo4 the same again. ,he mu!ti-!ayer chip industry opens up a $ho!e ne$ $or!d of design. 3ith the

3d chip design

1. INTRODUCTION
,here is a saying in rea! estate5 $hen !and get e6pensive2 mu!ti-storied 1ui!dings are the a!ternative so!ution. 3e have a simi!ar situation in the chip industry. *or the past thirty years2 chip designers have considered $hether 1ui!ding integrated circuits mu!tip!e !ayers might create cheaper2 more po$erfu! chips. &erformance of deep-su1 micrometer very !arge sca!e integrated /-.SI0 circuits is 1eing increasing!y dominated 1y the interconnects due to increasing $ire pitch and increasing die si7e. Additiona!!y2 heterogeneous integration of different techno!ogies on one sing!e chip is 1ecoming increasing!y desira1!e2 for $hich p!anar /2-D0 ICs may not 1e suita1!e. ,he three dimensiona! /3-D0 chip design strategy e6p!oits the vertica! dimension to a!!eviate the interconnect re!ated pro1!ems and to faci!itate heterogeneous integration of techno!ogies to rea!i7e system on a chip /SoC0 design. 8y simp!y dividing a p!anar chip into separate 1!oc4s2 each occupying a separate physica! !eve! interconnected 1y short and vertica! inter!ayer interconnects /-I.ICs02 significant improvement in performance and reduction in $ire-!imited chip area can 1e achieved. In the 3-Ddesign architecture2 an entire chip is divided into a num1er of 1!oc4s2 and each 1!oc4 is p!aced on a separate !ayer of Si that are stac4ed on top of each other.

3d chip design

2. MOTIVATION FOR 3-D ICs

,he unprecedented gro$th of the computer and the information

techno!ogy industry is demanding -ery .arge Sca!e Integrated / -.SI 0 circuits $ith increasing functiona!ity and performance at minimum cost and po$er dissipation. Continuous sca!ing of -.SI circuits is reducing gate de!ays 1ut rapid!y increasing interconnect de!ays. A significant fraction of the tota! po$er consumption can 1e due to the $iring net$or4 used for c!oc4 distri1ution2 $hich is usua!!y rea!i7ed using !ong g!o1a! $ires. *urthermore2 increasing drive for the integration of disparate signa!s /digita!2 ana!og2 +*0 and techno!ogies /S#I2 Si9e2 9aAs2 and so on0 is introducing various SoC design concepts2 for $hich e6isting p!anner /2-D0 IC design may not 1e suita1!e.

INTERCONNECT LIMITED VLSI PERFORMANCE

In sing!e Si !ayer /2-D0 ICs2 chip si7e is continuous!y increasing despite

reductions in feature si7e made possi1!e 1y advances in IC techno!ogy such as !ithography and etching. ,his is due to the ever gro$ing demand for functiona!ity and high performance2 $hich causes increased comp!e6ity of chip design2 re:uiring more and more transistors to 1e c!ose!y pac4ed and connected. Sma!! feature si7es have dramatica!!y improved device performance. ,he impact of this miniaturi7ation on the performance of interconnect $ire2 ho$ever2 has 1een !ess positive. Sma!!er $ire cross sections2 sma!!er $ire pitch2 and !onger !ine to traverse !arger chips have increase the resistance and capacitance of these !ines2 resu!ting in a significant increase in signa! propagation /+C0 de!ay. As interconnect sca!ing continues2 +C de!ay is increasing!y 1ecoming the dominant factor determining the performance of advanced IC;s.
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3d chip design

PHYSICAL LIMITATIONS OF Cu INTERCONNECTS

At 2 ) nm techno!ogy node2 Cu $ith !o$-4 die!ectric $as introduced to

a!!eviate the adverse effect of increasing interconnect de!ay.<o$ever21e!o$ 13)nm techno!ogy node2 su1stantia! interconnect de!ays $ou!d resu!t in spite of introducing these ne$ materia!s2 $hich in turn $i!! severe!y !imit the chip performance. *urther reduction in interconnect de!ay is not possi1!e. ,his pro1!em is especia!!y acute for g!o1a! interconnects2 $hich comprise a1out 1)= of tota! $iring in current architectures. ,herefore2 it is apparent that materia! !imitations $i!! u!timate!y !imit the performance improvement as techno!ogy sca!es. A!so2 the pro1!em of !ong !ossy !ines cannot 1e fi6ed 1y simp!y $idening the meta! !ines and 1y using thic4er inter!ayer die!ectric2 since this $i!! !eas to an increase in the num1er of meta! !ayers. ,his $i!! resu!t in an increase in comp!e6ity2 re!ia1i!ity and cost.

SYSTEM ON A CHIP DESIGN

System > on > a >chip /SoC0 is a 1road concept that refers to the

integration of near!y a!! aspects of a system design on a sing!e chip. ,hese chips are often mi6ed-signa! and?or mi6ed-techno!ogy designs2 inc!uding such diverse com1inations as em1edded D+AM2 high > performance and !o$-po$er !ogic2 ana!og2 +*2 programma1!e p!atforms /soft$are2 *&9As2 *!ash2 etc.0. SoC designs are often driven 1y the ever-gro$ing demand for increased system functiona!ity and compactness at minimum cost2 po$er consumption2 and time to mar4et. ,hese designs form the 1asis for numerous nove! e!ectronic app!ications in the near future2 in areas such as $ired and $ire!ess mu!timedia communications inc!uding high speed internet app!ications2 medica! app!ications

3d chip design

inc!uding remote surgery2 automated drug de!ivery2 and non invasive interna! scanning and diagnosis2 aircraft?automo1i!e contro! and safety2 fu!!y automated industria! contro! systems2 chemica! and 1io!ogica! ha7ard detection2 and home security and entertainment systems2 to name a fe$. ,here are seve !" #$!""e%&es to effective SoC designs@ 1. .arge sca!e integration of functiona!ities and disparate techno!ogies on a sing!e chip dramatica!!y increases the chip area2 $hich necessitates the use of numerous !ong g!o1a! $ires. ,hese $ires can !ead to unaccepta1!e signa! transmission de!ays and increase the po$er consumption 1y increasing the tota! capacitance that needs to 1e driven 1y the gates. 2. Integration of disparate techno!ogies such as em1edded D+AM2 !ogic2 and passive components in SoC app!ications introduces significant comp!e6ity in materia!s and process integration. 3. ,he noise generated 1y the interference 1et$een different em1edded circuit 1!oc4s containing digita! and ana!og circuits 1ecomes a cha!!enging pro1!em. 4. A!though SoC designs typica!!y reduce the num1er of I?# pins compared to a system assem1!ed on a printed circuit 1oard/&C802 severa! high performance SoC designs invo!ve very high I?# pin counts 2 $hich can increase the cost per chip . Integration of mi6ed techno!ogies on a sing!e die re:uires nove! design methodo!ogies and too!s 2$ith design productivity 1eing a 4ey re:uirement.

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3d chip design

3D ARCHITECTURE

,hree-dimensiona! integration to create mu!ti!ayer Si ICs is a concept that can significant!y improve interconnect performance 2increase transistor pac4ing density2 and reduce chip area and po$er dissipation. Additiona!!y 3D ICs can 1e very effective !arge sca!e on chip integration of different systems. In 3D design architecture2 and entire/2D0 chips is divided into a num1er of 1!oc4s is p!aced on separate !ayer of Si that are stac4ed on top of each other. Aach Si !ayer in the 3D structure can have mu!tip!e !ayer of interconnects/-I.ICs0 and common g!o1a! interconnects.

3d chip design

ADVANTAGES OF 3D ARCHITECTURE
,he 3D architecture offers e6tra f!e6i1i!ity in system design2 p!acement

and routing. *or instance2 !ogic gates on a critica! path can 1e p!aced very c!ose to each other using mu!tip!e active !ayers. ,his $ou!d resu!t in a significant reduction in +C de!ay and can great!y enhance the performance of !ogica! circuits. ,he 3D chip design techno!ogy can 1e e6p!oited to 1ui!d SoCs 1y p!acing circuits $ith different vo!tage and performance re:uirements in different !ayers. ,he 3D integration can reduce the $iring 2there1y reducing the capacitance2 po$er dissipation and chip area and therefore improve chip performance. Additiona!!y the digita! and ana!og components in the mi6ed-signa! systems can 1e p!aced on different Si !ayers there1y achieving 1etter noise performance due to !o$er e!ectromagnetic interference 1et$een such circuits 1!oc4s. *rom an integration point of vie$2 mi6ed-techno!ogy assimi!ation cou!d 1e made !ess comp!e6 and more cost effective 1y fa1ricating such techno!ogies on separate su1strates fo!!o$ed 1y physica! 1onding.

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3d chip design

3. SCOPE OF THIS STUDY

A 3D so!ution at first g!ance seems an o1vious ans$er to the interconnect de!ay pro1!em. Since chip si7e direct!y affects the inter connect de!ay2 therefore 1y creating a second active !ayer2 the tota! chip footprint can 1e reduced2 thus shortening critica! inter connects and reducing their de!ay. <o$ever2 in today;s microprocessor2 the chip si7e is not Bust !imited 1y the ce!! si7e 21ut a!so 1y ho$ much meta is re:uired to connect the ce!!s. ,he transistors on the Si surface are not actua!!y pac4ed to ma6imum density2 1ut are spaced apart to a!!o$ meta! !ines a1ove to connect one transistor or one ce!! to another .,he mea! re:uired on a chip for inter connections is determined not on!y 1y the num1er of gates 21ut a!so 1y other factors such as architecture2 average fan-out2 num1er of I?# connections2 routing comp!e6ity2 etc ,herefore2 it is not o1vious that using a 3D structure the chip si7e $i!! 1e reduced.

3d chip design

'. AREA AND PERFORMANCE ESTIMATION OF 3D ICs

Co$ $e present a methodo!ogy that can 1e used to provide an initia! estimate of the area and performance of high speed !ogic circuits fa1ricated using mu!tip!e si!icon !ayer IC techno!ogy. ,he approach is 1ased on the empirica! re!ationship 4no$n as +ent;s +u!e.

Re%()s Ru"e*
It corre!ates the num1er of signa! input and output /I?#0 pins ,2 to the num1er of gates C2 in a random !ogic net$or4 and is given 1y the fo!!o$ing e6pressions @ ,D4C& -------------/i0 <ere 4 E & denote the average num1er of fan out per gate and the degree of $iring comp!e6ity /$ith &D1 representing the most comp!e6 $iring net$or402 respective!y2 and are empirica!!y derived as constants for a given generation of ICs. A+ 2-D AND 3-D ,IRE-LENGTH DISTRIBUTIONS ,he $ire-!ength distri1ution can 1e descri1ed 1y i/!02an interconnect density functions /i.d.f02 or 1y I/!02 the cumu!ative interconnect distri1ution function /c.i.d.f0 $hich gives the tota! num1er of interconnects that have !ength !ess than or e:ua! to ! /measured in gate pitches0 and is defined as ? I/!0D 1
l

i/60d6

-----------/ii0

1)

3d chip design

3here 6 is a varia1!e of integration representing !ength and ! is the !ength of the interconnect in gate pitches. ,he derivation of the $ire-!ength distri1uted in a Ic is 1ased on +ent;s +u!e. ,o derive the $ire !ength distri1ution I/!0 of an integrated circuit2 the !atter is divided up into C !ogic gates2 $here C is re!ated to the tota! num1er of transistor Ct in an integrated circuit 1y CDCt?# $here # is a function of the average fan-in/f.i) and fan-out/f.o0. ,he gate pitch is defined as the average separation 1et$een the !ogic gates and is e:ua! to s:t/Ac?C0 $here Ac is the area of the chip. In order to derive the comp!ete $ire-!ength distri1ution for a chip2 the stochastic $ire-!ength distri1ution of a sing!e gate must 1e ca!cu!ated.

,he num1er of connections from the sing!e !ogic gate in 8!oc4 A to a!! other gate that are !ocated at a distance of ! gate pitches is determined using +ent;s +u!e. ,he gates sho$n in the figure are grouped into three distinct 1ut adBacent 1!oc4s/A28EC02 such that a c!osed sing!e path can encirc!e one2 t$o or three of these 1!oc4s. ,he num1er of connections 1et$een 8!oc4 A and 8!oc4 C is ca!cu!ated 1y conserving a!! I?# termina!s for 1!oc4s2 A2 82 and C2 $hich states

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3d chip design

that termina!s for 1!oc4s A2 82 and C2 are either inter!oc4 connections or e6terna! system connections. <ence2 app!ying the princip!e of conservation of I?# pins to this system of three !ogic 1!oc4s2 sho$n gives ,A F ,8 F ,C D ,A to C F ,A to 8 F ,8 to C F ,A8C GGGGG./iii0 3here ,A2 ,82 ,C are the num1er of I?# 1!oc4s A2 82 and C respective!y. ,A to C 2 ,A to 82 ,8 to C are the num1er of I?#s 1et$een 1!oc4s A and C2 1!oc4s A and 82 and 1et$een 1!oc4s 8 and C2 respective!y. , A8C represents the num1er of I?#s for the entire system comprising of a!! three 1!oc4s. *rom conservation of I?#s2 the num1er of I ?#s 1et$een adBacent 1!oc4s A and 82 and 1et$een adBacent 1!oc4s A and 8 and 1et$een adBacent 1!oc4s 8 and C can 1e e6pressed as ,A to 8 D ,A F ,8 - ,A8 ,8 to C D ,8 F ,C > ,8C Su1stituting /iv0 and /v0 into /iii0 gives ,A to C D ,A8 F ,8C > ,8 - ,A8C GGGGGGGGGG/vi0 GGGGGGGG..GG./iv0 ..GGGGGGGGGG./v0

Co$ the num1er of I?# pins for any sing!e 1!oc4 or a group of 1!oc4s can 1e ca!cu!ated using +ent;s +u!e. If $e assume that C2 C2 and C are the num1er of gates in 1!oc4s A2 82 and C2 respective!y2 then it fo!!o$s that ,8 D 4 /C80& ,A8 D 4/CA F C80& ,8C D 4/C8 F CC 0& ,A8C D 4/CA F C8 FCC0& GGGGGGGGG/vii0 GG..GGGGGG../viii0 GGG.GGGGGG/i60 GGGGGGGGG./60
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3d chip design

3here C D CA F C8 F CC. Su1stituting /vii0 > /60 into /vi0 gives ,A to C D 4 H/ CA F C80& > /C80& F /C8 F CC0& > /CA F C8 F CC0&I GG../6i0 ,he num1er of interconnects 1et$een 8!oc4 A and 8!oc4 C /I A determined using the re!ation IA to C D J4 /,A to C0 3here J is re!ated to the average fan out /f.o.0 1y J D f.o. ? /1Ff.o.0 App!ying +ent;s +u!e to a!! the !ayers2 $e have
n

to C

0 is

,D4C& D / ,i0 > ,int D n4/C?n0& - ,int

i =1

<ere2 , is the num1er of I?#s for the entire design2 , i represents the num1er of I?# ports connecting n !ayers. <ence it fo!!o$s that ,int D n /1- n&-10 4 /C?n0& and

,e6t2i D ,i > ,int?n D 4n&-1 /C?n0& <ere2 ,e6t2i 2 is the average of I?# ports per !ayer. B+ ESTIMATING 2-D AND 3-D CHIP AREA In integrated circuits that are $ire-pitch !imited in si7e2 the area re:uire 1y the $iring net$or4 is assumed to 1e much greater than the area re:uired 1y the
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3d chip design

!ogic gates. *or the purpose of minimi7ing si!icon rea! estate and signa! propagation de!ays2 the $iring net$or4 is segmented into separate tiers that are physica!!y fa1ricated in mu!tip!e !ayers. An interconnect tier is categori7ed 1y factors such as meta! !ine pitch and cross-section2 ma6imum a!!o$a1!e signa! de!ay and communication mode /such as intra 1!oc42 or inter 1!oc40. A tier can have more than one !ayer of meta! interconnects if necessary2 and each tier or !ayer is connected to the rest of the $iring net$or4 and the !ogic gates 1y vertica! vias. ,he tier c!osest to the !ogic devices /referred to as the "-#!" (.e 0 is norma!!y for short distance intra 1!oc4 communications. Meta! !ines in this tier $i!! norma!!y 1e the shortest. ,hey $i!! a!so norma!!y have the finest pitch. ,he tier furthest a$ay from the device !ayer /referred to as &"-/!" (.e 0 is responsi1!e for !ong distance across chip inter 1!oc4 communications2 c!oc4ing and po$er distri1ution. Since this tier is popu!ated 1y the !ongest of $ires2 the meta! pitch is the !argest to minimi7e signa! propagation de!ays. A typica! modern IC interconnects architecture $i!! define three $iring tiers@ "-#!"0 se1.-&"-/!"0 !%2 &"-/!". ,he semi-g!o1a! tier is norma!!y responsi1!e for inter 1!oc4 communications across intermediate distances.

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3d chip design

,he area of the chip is determined 1y the tota! $iring re:uirement. IC terms of gate pitch2 the tota! area re:uired 1y the interconnect $iring can 1e e6pressed as Are:uired D KAc /&!oc.tota!L!ocF&semi.tota!LsemiF&g!o1.tota!Lg!o10?C 3here2 Ac C &!oc &semi &g!o1a! .tota!Lsemi .tota!Lg!o1 Chip area 5 num1er of gates5 !oca! pitch5 semi g!o1a! pitch5 g!o1a! pitch5 tota! !ength of semi g!o1a! interconnects5 tota! !ength of g!o1a! interconnects5

.tota!L!oc tota! !engths of !oca! interconnects5

,he tota! interconnects !ength for any tier can 1e found 1y integrating the $ire-!ength distri1ution $ithin the 1oundaries that define the tier. <ence it fo!!o$s that .tota!L!ocD M N !i /!0 d!
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3d chip design

.tota!LsemiDM N !i /!0 d! .tota!Lg!o1 D M N !i /!0 d! 3here M is a correction factor that converts the point >to > point interconnect !ength to $iring net !ength /using a !inear net mode!2 MD4?/f.o. F 30 C+ T,O ACTIVE LAYER 3-D CIRCUIT PERFORMANCE ,his ana!ysis is used to compare area and de!ay va!ues for 2-D and 3-D ICs. ,he avai!a1i!ity of addition of si!icon !ayers gives the designer e6tra f!e6i1i!ity in trading off area $ith de!ay. A num1er of different cases are discussed as fo!!o$s@ 1. C$.3 ! e! 1.%.1.4!(.-% 5.($ 6.7e2 .%(e #-%%e#( 2e"!8 <ere2 -I.ICs are assumed to consume neg!igi1!e area2 interconnect !ine $idth is assumed to e:ua! ha!f the meta! pitch at a!! times2 and the tota! num1er of meta! !ayers for 2-D and 3-D case $as conserved. A 4ey assumption for the geometrica! construction of each tier of the mu!ti!eve! interconnect net$or4 is that a!! cross sectiona! dimensions are e:ua! $ithin that tier. As &semi increase from its va!ue at the minimum A c the semi g!o1a! and g!o1a! pitches increase resu!ting in a !arger $iring re:uirement and thus a !arger Ac. *urthermore2 as &semi increases2 even !onger $ires can no$ satisfy the ma6imum de!ay re:uirement in the semi g!o1a! tier. ,hese resu!ts in g!o1a! $ires to 1e rerouted to the semi g!o1a! tier2 $hich in turn $i!! re:uire greater chip area. Onder such circumstances2 the semi g!o1a! tier 1egins to dominate and determine the chip area. Converse!y2 as &semi decreases from its va!ue at the minimum A c2 the !onger $ires in the semi g!o1a! tier no !onger satisfy the ma6imum de!ay re:uirement of that tier and they need to 1e rerouted to the g!o1a! tier $here they can enBoy a !arger pitch. ,he popu!ations of $ires in g!o1a! tiers increases and
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3d chip design

since these $ires have a !arge cross section they have a greater area re:uirement. Onder such circumstances the g!o1a! tier 1egins to dominate and determine the chip area. ,he curve for the 3-D case has a minimum simi!ar to the one o1tained for the 2-Dcase.it can 1e o1served that the minimum chip area for the 3-D case is a1out P3)= sma!!er than that of the 2-D case. Moreover2 since the tota! $iring re:uirement is reduced2 the semi g!o1a! tier pitch is reduced for the 3-Dchip. ,he significant reductions in chip area demonstrated 1y the 3-D resu!ts are a conse:uence of the fraction of $ires that $ere converted from hori7onta! in 2-D to vertica! -I.ICs in 3-D. it is assumed that the area re:uired 1y -I.ICs is neg!igi1!e. ,hese resu!ts demonstrate2 $ith given assumptions2 that a 3-D IC can operate at the same performance !eve!2 as measured 1y the !ongest $ire de!ay2 as its 2-D counterpart $hi!e using up a1out 3)= !ess si!icon rea! estate. <o$ever2 it is possi1!e for 3-D ICs to achieve greater performance than their 2-Dcounterparts 1y reducing the interconnect impedance at the price of increased chip area as discussed ne6t. 2. I%# e!s.%& C$.3 A e! !%2 Pe 6- 1!%#e 3-D IC performance can 1e enhanced to e6ceed the performance of 2-D ICs 1y improving interconnect de!ay. ,his is achieved 1y increasing the $ire pitch2 $hich causes a reduction in the resistance. ,he effect of increasing p semi and pg!o1a! on the operating fre:uency and Ac. ,his i!!ustrates ho$ the optimum semi g!o1a! pitch /i.e.2 the p semi associated $ith the minimum Ac0 increases to o1tain higher operating fre:uencies. A!so2 as the semi g!o1a! tier pitch increases2 chip area and2 therefore2 interconnect !ength a!so increases. <o$ever2 $e can see that the increase in chip
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3d chip design

area sti!! remains $e!! 1e!o$ the area re:uired for the 2-D case. ,he figure a!so he!ps defines a ma6imum > performance 3-D chip > a chip $ith the same area as the corresponding 2-D chip2 $hich can 1e o1tained 1y increasing the semi g!o1a! pitch 1eyond that for the 4-9<7 case. ,$o scenarios are considered 10 g!o1a! pitch is increased to match the g!o1a! pitch for the 2-d case and 20 g!o1a! pitch is increased to match the chip area /footprint0 for the 2-d case. Cote that the de!ay re:uirements sets a ma6imum va!ues of interconnect !ength are given tier. ,herefore2 as interconnect !engths are increased2 !ines $hich e6ceed this ma6imum !ength criterion for that particu!ar tier need to 1e rerouted on upper ties.

8eyond the ma6imum performance point for the 3-d chip2 the performance gain 1ecomes increasing!y sma!!er in comparison to the decrease in performance resu!ting from the increase in chip area or reconnect de!ay. *urthermore2 as the semi g!o1a! $ires need to 1e rerouted on the g!o1a! tiers2 $hich eventua!!y !eads to overcro$ding of the g!o1a! tier . Any further increases in the $iring density in the g!o1a! tier forces a reduction in the g!o1a! pitch. D+ EFFECT OF INCREASING NUMBER OF SILICON LAYERS As the num1er of si!icon !ayers increases 1eyond t$o2 the assumption that a!! inter!ayer interconnects /I.ICs0 are vertica! and consume neg!igi1!e area 1ecomes !ess tena1!e. ,he area used up 1y these hori7onta! I.ICs can 1e estimated from their tota! !ength and pitch. ,he decrease in interconnect de!ay 1ecomes progressive!y sma!!er as the num1ers of active !ayers increase. ,his is due to the fact that the area re:uired 1y

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3d chip design

I.ICs 1egins to offset any area saving due to increasing the num1er of active !ayers. E+ EFFECT OF INCREASING THE NUMBER OF METAL LAYERS It is !i4e!y that there are !oca! and semi g!o1a! tiers associated $ith every active !ayer2 and a common g!o1a! tier is used . ,his $ou!d resu!t in an increase in the tota! num1er of meta! !ayers for the 3-D case. ,he effect of using 3-D case. ,he effect of using 3-D ICs $ith constant meta! !ayers and the effect of emp!oying t$ice the num1er of meta! !ayers as in 2-D are summari7ed in the figure.

It can 1e o1served that 1y using t$ice the num1er of meta! !ayers the performance of the 3-D chip can 1e increased 1y an additiona! amount of 3 = as compared to the 3-d chip $ith the same tota! num1er of meta! !ayers as in 2-d . It can 1e o1served that for the more aggressive techno!ogies 2 the decrease in
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3d chip design

interconnect de!ay from 2-D to 3-D case is !ess impressive. ,his indicates that more than t$o active !ayers are possi1!y needed for those advanced nodes. ,he figure a!so sho$s the impact of moving on!y the repeaters to the second !ayer Si !ayer . It can a!so 1e o1served that for more aggressive techno!ogies 2 the decrease in interconnect de!ay from 2-D to 3-D case is !ess impressive ,his indicates that more than t$o active !ayers are possi1!y needed for those advanced nodes. F.OPTIMI9ATION OF INTERCONNECT DISTRIBUTION In estimating chip area2 the meta! re:uirement is ca!cu!ated from the o1tained $ire-!ength distri1ution. ,he tota! meta!!i7ation re:uirement is appropriate!y divided among the avai!a1!e meta! !ayers in the corresponding techno!ogy . ,hus each tier 2 the !oca! 2 the semi g!o1a! and the g!o1a! has three meta! !ayers . the resu!ting area of most dense!y pac4ed tier determines the chip area. Conse:uent!y2 higher tier are routed $ithin a !arger than re:uired area . An optimi7ation for this scenario is possi1!e 1y rerouting some of the !oca! $ires on the semi g!o1a! tier and the !atter on the g!o1a! 2 $ithout vio!ating the ma6imum a!!o$a1!e .ength / or de!ay 0 per tier. ,his is achieved 1y reducing the ma6imum a!!o$ed interconnect !ength for the !oca! and semi g!o1a! tiers. Minimum chip area $i!! achieved $hen a!! the tiers are e:ua!!y congested. ,he 2D chip area is seen to reduce 1y (= as a resu!t of this optimi7ation is a!so app!ied to app!ied to 3-D ICs .

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3d chip design

:.CHALLENGES FOR 3-D INTEGRATION

A+ THERMAL ISSUES IN 3-D ICs
An e6treme!y important issue in 3-D ICs is heat dissipation. ,herma! effect s are a!ready 4no$n to significant!y impact interconnected ?device re!ia1i!ity and performance in high-performance 2-D ICs. ,he pro1!em is e6pected to 1e e6acer1ated 1y the reduction in chip si7e2 assuming that same po$er generated in a 2-D chip $i!! no$ 1e generated in a sma!!er 3-D chip2 resu!ting in a sharp increase in the po$er and density Ana!ysis of therma! pro1!ems in 3-D circuits is therefore necessary to comprehend the !imitations of this techno!ogy and a!so to eva!uate the therma! ro1ustness of different 3-D techno!ogy and design options. It is $e!! 4no$n that most of the heat energy in integrated circuits arises due to transistor s$itching. ,his heat energy is typica!!y conducted through the si!icon su1strate to the pac4age and then to the am1ient 1y a heat sin4 .3ith mu!ti !ayer device designs2 devices in the upper !ayer $i!! a!so generate a significant fraction of the heat .*urthermore2 a!! the active !ayers $i!! 1e insu!ated from each other 1y !ayers of die!ectrics /.,#2 <SQ2 po!yamide2 etc.0 $hich typica!!y have much !o$er therma! conductivity than Si .<ence 2the heat dissipation issue can 1ecome even more acute for 3-D ICs and can cause degradation in device performance 2and reduction in chip re!ia1i!ity due to increased Bunction !ea4age2 e!ectro migration fai!ures 2and 1y acce!erating other fai!ure mechanisms.

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B+ RELIABLITY ISSUES IN 3-D ICs

,hree dimensiona! IC s $i!! possi1!y introduce some ne$ re!ia1i!ity pro1!ems. ,hese re!ia1i!ity issues may arise due to the e!ectro therma! and thermo mechanica! effects 1et$een various active !ayers and the interfaces 1et$een the active !ayers2 $hich can a!so inf!uence e6isting IC re!ia1i!ity ha7ards such a e!ectro migration and chip performance. Additiona!!y2 heterogeneous integration of techno!ogies using 3-d architecture $i!! increase the need to understand mechanica! and therma! 1ehavior of ne$ materia! of ne$ materia! interfaces and thin fi!m materia! therma! and mechanica! properties.

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;. OVERVIE, OF 3-D IC TECHNOLOGY

1+ BEAM RECRYSTALI9ATION
A very popu!ar method of fa1ricating a second active !ayer /Si0 on top of an e6isting su1strate /o6idi7ed Si $afer 0is to deposit po!ysi!icon and fa1ricate thin fi!m transistors /,*,0. ,o enhance the performance of such transistors 2an intense !aser or e!ectron 1eam is used to induce recrysta!isation of the po!ysi!icon fi!m to reduce or even e!iminate most of the grain 1oundaries.

A2v!%(!&e
1. M#S on transistors fa1ricated on po!ysi!icon e6hi1it very !o$ surface mo1i!ity va!ues Hof the order of 1) cm?-sI. 2. M#S transistors fa1ricated on po!ysi!icon have high thresho!d vo!tages /severa! vo!ts0 due to the high density of surface states /severa! 1) cm 0 present at the grain 1oundaries.

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3d chip design

D.s!2v!%(!&e
1. ,his techni:ue2 ho$ever2 may not 1e very practica! for 3-D devices 1ecause of the high temperature invo!ved during me!ting of the po!ysi!icon. 2. Difficu!ty in contro!!ing the grain si7e variations.

2+ SILICON EPITA<IAL GRO,TH

Another techni:ue for forming additiona! Si !ayers is to etch a ho!e in a passivated $afer and epita6ia!!y gro$ a sing!e crysta! Si seeded from open $indo$ in the I.D. ,he Si crysta! gro$s vertica!!y and then !atera!!y to cover the I.D.

A2v!%(!&e* 1. ,he :ua!ity of devices fa1ricated on these epita6ia! !ayer can 1e as good as those fa1ricated underneath on the seed $afer surface2 since the gro$n !ayer is sing!e crysta! $ith fe$ defects.

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3d chip design

D.s!2v!%(!&e
1. ,he high temperatures invo!ved in this process cause significant degradation in the :ua!ity of devices on !o$er !ayers.

2.

PROCESSED ,AFER BONDING*

An attractive a!ternative is to 1ond t$o fu!!y processed $afers on $hich

devices are fa1ricated on the surface 2inc!uding some interconnects2 such that the $afers comp!ete!y over!ap.Interchip vias are etched to e!ectrica!!y connect 1oth $afers after meta!!i7ation and prior to the 1onding process at 4)) degree Ce!sius. *or app!ications $here each chip is re:uired to perform independent processing 1efore communicating $ith it;s neigh1or 2 this techno!ogy can prove attractive .

A2v!%(!&e
1. Devices on a!! active !eve!s have simi!ar e!ectrica! properties. 2. Since a!! chips can 1e fa1ricated separate!y and !ater 1onded 2there is independence of processing temperature.

D.s!2v!%(!&e
1. ,he !ac4 of precision restricts the interchip communication to g!o1a! meta! !ines.

3. SOLID PHASE CRYSTALLI9ATION =SPC+

In this techni:ue2 a !ayer of amorphous Si is crysta!!i7ed on top of the !o$er active !ayer devices. ,he amorphous fi!m is random!y crysta!!i7ed to form a po!ysi!icon fi!m. Device performance can 1e enhanced 1y e!iminating the grain 1oundaries in the po!ysi!icon fi!m. *or this purpose 2!oca! crysta!!i7ation can 1e induced using !o$ temperatures processes /R"))C0 such as using patterned
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3d chip design

seeding of germanium . In this method2 9e seeds imp!anted in narro$ patterns made on amorphous Si can 1e used to inc!uded !atera! crysta!!i7ation. ,his resu!ts in the formation of sma!! is!ands2 $hich are near!y sing!e crysta!. CM#S transistors can then 1e fa1ricated $ithin these is!ands to give S#I !i4e performance.

A2v!%(!&es
1. ,his techni:ue offers f!e6i1i!ity of creating mu!tip!e active !ayers 2. ,his is a !o$ temperature techni:ue

B+ VERTICAL INTERLAYER INTERCONNECT TECHNOLOGY OPTIONS

,here is direct re!ation 1et$een improved chip performance and increased uti!ity of -I.ICs. It is therefore important to understand ho$ to connect different active !ayers $ith a re!ia1!e and compati1!e process. Opper !ayer processing needs to 1e compati1!e $ith meta! !ines underneath connecting !o$er !ayer devices and meta! !ayers. 3ith Cu techno!ogies2 this !imits the processing temperatures to R4 ) c for upper !ayers. #ther$ise 2 Cu diffusion through 1arrier !ayers 2 and the re!ia1i!ity and therma! sta1i!ity of materia! interfaces can degrade significant!y. ,ungsten is a refractory meta! that can 1e used to $ithstand higher processing temperatures2 1ut it has higher resistivity. Current via techno!ogy can a!so 1e emp!oyed to achieve -I.IC functiona!ity. ,he under!ying assumption here re:uires that inter!ayer gates are interconnected using regu!ar hori7onta! meta! $ires and vias2 $hi!e inter!ayer interconnects can 1e -I.ICs connecting the $iring net$or4 for each !ayer.

2"

3d chip design

+ecent!y2 inter!ayer /-.IC0meta!!i7ation schemes for 3-d ICs have 1een demonstrated using direct $afer 1onding. ,hese techni:ues are 1ased on the 1onding of t$o $afers $ith their active !ayers connected through vias 2$hich serve as -I.ICs . #ne method is 1ased on the 1onding of a thinned top $afer to a 1ottom $afer $ith a organic adhesive !ayer of po!yamide in 1et$een. Interchip vias are etched through the I.D/inter !eve! die!ectric 02the thinned top si!icon $afer and through the cured adhesive !ayer 2$ith an appro6 depth of 2) m prior to the 1onding process .the interconnect chip via made of chemica! $afer depositor /C-D0. ,in !iner and C-D-3 p!ug provides a vertica! interconnect /-I.IC01et$een the upper most meta!!i7ation !eve!s of 1oth !ayers . the 1onding 1et$een the t$o $afers is done using a f!ip-chip 1onder $ith sp!it 1eam optics at a temperature of 4)) degree Ce!sius A second techni:ue rea!i7es on the ($e 1- #-13 ess.-% 1onding 1et$een the meta! parts in each $afer. In this method2 Cu-,a pads on 1oth $afers save as e!ectrica! contacts 1et$een the interchips via on the top thinned si!icon $afer and the upper most interconnects on the 1ottom si!icon $afer. ,he Cu-,a pads can a!so function as sma!! 1ond pads for $afer 1onding. Additiona!!y2 dummy meta! patterns can 1e made to increase the surface area for $afer 1onding. ,he Cu-,a 1i!ayer pads $ith a com1ined thic4ness of %)) nm are fused together 1y app!ying a compressive force at 4)) degree Ce!sius. ,his techni:ue offers the advantage of a meta! >meta! interface that $i!! !o$er the interface therma! resistance 1et$een the t$o $afers /and2 hence2 provide 1etter conduction0 and can 1e 1eneficia! as a partia! ground p!ane for !o$ering the e!ectromagnetic effects.

>. PRESENT SCENARIO OF THE 3-D IC INDUSTRY

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3d chip design

Many companies are $or4ing on the 3-D chips 2inc!uding groups at Massachusetts institute of techno!ogy /MI,02internationa! 1usiness machines/I8M0. +ensse!ar &o!ytechnic and SOCS A!1any are a!so doing

research on techni:ues for 1onding conventiona! chips together to form mu!tip!e !ayers .$hichever approach u!timate!y $ins 2the mu!ti!ayer chip 1ui!ding techno!ogy opens up a $ho!e ne$ $or!d of design . <o$ever 2the Santa C!ara2 Ca!ifornia OS 1ased startup company matri6 semiconductor $i!! 1ring the first mu!ti!ayer chip to the mar4et 2$hi!e matri6;s techni:ues $i!! not !i4e!y resu!t in more computing po$er 2they $i!! produce cheaper chips for certain app!ications2 !i4e memory used in digita! cameras 2 persona! digita! assistants 2ce!!u!ar phones 2hand he!d gaming devices 2etc .matri6 has adapted the techno!ogy deve!oped for ma4ing f!at >pane! !i:uid crysta! disp!ays to 1ui!d chips $ith mu!ti!ayer of circuitry. ,he company;s first products $i!! 1e memory chips ca!!ed 3-Dmemory2 for consumer e!ectronics !i4e digita! cameras and audio p!ayers. current f!ash memory cards for such devices are re$rita1!e 1ut e6pensive .ho$ever the ne$!y produced chips $i!! cost ten times !ess2 a1out as much as an audio tape or a ro!! of fi!m2 1ut $i!! on!y record information once. ,he cost is so !arge!y 1ecause the stac4ed chips contain the same amount of circuitry as f!ash cards 1ut use a much sma!!er area of the e6treme!y e6pensive si!icon $afers that form the 1asis for a!! si!icon chips. ,he chips $i!! a!so offer a permanent record of the images and sounds users record. ,he amount of computing po$er the company can u!timate!y 1ui!d in to its chips cou!d 1e !imited .the company hopes to eventua!!y 1ui!d chips for ce!! phones2 or !o$ performance micro processors !i4e those found in app!iances5 such chips $ou!d 1e a1out one tenth as e6pensive as current ones.

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3d chip design

,he patent techno!ogy opens up the a1i!ity to 1ui!d ICs in three dimensions- TupU as $e!! as ToutU in the hori7onta! directions as in the case no$ $ith conventiona! chip designs. ,he resu!t is a ten fo!d increase in the potentia! no of 1its on a si!icon die2 according to the company .moreover2 the 3-D circuits can 1e produced $ith todays standard semiconductor materia!s2 fa1 e:uipments and processors the 3-D memory $i!! 1e used in memory devices $hich $i!! 1e mar4eted under $e!! 4no$n 1rand names for porta1!e e!ectronics devices2 inc!uding digita! cameras digita! audio p!ayers2 games2 &DAs and archiva! digita! storage .the 3-D memory can a!so 1e used for pre recorded content such as music2 e!ectronics 1oo4s2 digita! maps2 games2 and reference guides.

2(

3d chip design

?. ADVANTAGES OF 3-D MEMORY

Dis4s are ine6pensive2 1ut they re:uires drives that are e6pensive 1u!4y 2fragi!e and consume a !ot of 1attery po$er . Accidenta!!y dropping a drive or scratching a dis4 can cause significant damage and the potentia! !oss of va!ua1!e pictures and data. *!ash and other non vo!ati!e memories are much more rugged2 1attery efficient compact and re:uire no 1u!4y drive techno!ogies . Dropping them is not a pro1!em they are ho$ever much more e6pensive. 8oth re:uire the use of a pc. ,he idea! so!ution is a 3-D memory that !everages a!! the 1enefits of non vo!ati!e media2 costs as !itt!e as a dis42 and is as convenient as 3 mm fi!m and audio tape.

3)

3d chip design

@. APPLICATIONS
&orta1!e e!ectronic digita! cameras2 digita! audio p!ayers2 &DAs2 smart

ce!!u!ar phones2 and handhe!d gaming devices are among the fastest gro$ing techno!ogy mar4et for 1oth 1usiness and consumers. ,o date2 one of the !argest constraints to gro$th has 1een afforda1!e storage2 creating the mar4eting opportunity for u!tra !o$ cost interna! and e6terna! memory. ,hese app!ications share characters 1eyond rapid mar4et gro$th. &orta1!e devices a!! re:uire sma!! form factors 21attery efficiency2 ro1ustness2 and re!ia1i!ity. 8oth the devices and consuma1!e media are e6treme!y price sensitive $ith high vo!umes coming on!y $ith the a1i!ity to hit !o$ price points. Device designers often trade app!ication richness to meet tight cost targets. A6isting mas4 +#M and CACD f!ash non vo!ati!e techno!ogy force designers and product p!anners to ma4e the difficu!t choice 1et$een !o$ cost or fie!d programma1i!ity and f!e6i1i!ity. Consumers va!ue the convenience and ease of vie$s of readi!y avai!a1!e !o$ cost storage. ,he potentia! to dramatica!!y !o$er the cost of digita! storage $eapons many more mar4ets than those !isted a1ove. Manufacturers of memory driven devices can no$ reach price points previous!y inaccessi1!e and deve!op richer2 easier to use products.

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3d chip design

1A. FUTURE OF THE 3-D IC INDUSTRY

Matri6 is $or4ing $ith partners inc!uding Microsoft Corp2 ,homas Mu!timedia2 Aastman Voda4 and Sony Corp. three product categories are p!anned@ 1!and memory cards@ cards so!d pre!oaded $ith content2 such as soft$are or music 5 and standard memory pac4ages2 for using em1edded app!ications such as &DAs and set-top 1o6es . T$-1s-% e"e#( -%.#s2 the Auropean e!ectronic giant2 $i!! 1egin to incorporate 3-D memory chips from matri6 semiconductor in porta1!e storage cards2 a strong endorsement for the chip start >up. T$-1s-% 1u"(.1e2.! $i!! incorporate the 3-D memory in memory cards that cane 1e used to store digita! photos or music. A!though the cards p!ug into cameras ,homson is a!so $or4ing on card readers that $i!! a!!o$ consumers to vie$ digita! photos on a te!evision. ,he ,homson ?matri6 cards price ma4es the difference from comp!eting f!ash cards from Sony and ,oshi1a .the "4 M8 ,homson card $i!! cost a1out as much as camera fi!m does today. to further strengthen the re!ationship $ith fi!m 2the cards $i!! 1e so!d under the name ,echnico!or Digita! Memory Card. Simi!ar f!ash memory cards from other companies cost around +s.1()) or more-though consumers can erase and rerecord data on them2 un!i4e the matri6 cards. As a resu!t of their price2 consumers 1uy very fe$ of them. ,homson2 1y contrast 2 e6pects to mar4et its $rite-once cards in retai! out!et such as 3a!Mart. ,he first ,echnico!or cards $i!! offer "4 M8 of memory5 version $ith 12' M8 and 1(2 M8 $i!! appear !ater. ,he first 3-D chips $i!! contain "4 M8. ,ai$an Semiconductor Manufacturing Co. is producing the chips on 1eha!f of matri6.
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3d chip design

11. CONCLUSION
,he 3 D memory $i!! Bust the first of a ne$ generation of dense2 ine6pensive chips that promise to ma4e digita! recording media 1oth cheap and convenient enough to rep!ace the photographic fi!m and audio tape. 3e can understand that 3-D ICs are an attractive chip architecture2 that can a!!eviate the interconnect re!ated pro1!ems such as de!ay and po$er dissipation and can a!so faci!itate integration of heterogeneous techno!ogies in one chip. ,he mu!ti!ayer chip 1ui!ding techno!ogy opens up a $ho!e ne$ $or!d of design !i4e a city s4y!ine transformed 1y s4yscrapers2 the $or!d of chips may never !oo4 at the same again.

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3d chip design

12. REFERNCES
1. &roceedings of the IAAA2 vo! '(2no 2may 2))1@ /a0 Wose A Schutt-Aine 2 sung-Mo Vang2 TInterconnections >addressing the ne6t cha!!enge of IC techno!ogyU at page '3 /10 +o1ert h <ave Mann2 Wames A <utch 1y2 T<igh performance interconnects@ an integration overvie$U at page '". /c0 Vaustav 8anerBee2 Shu4ri W Souri2 &a$an Vapur and Vrishna C Sara s$ath 3-D ICs@ a nove! chip design for improving deep su1 micrometer interconnect performance and Soc integration at page ")2. 2. A!ectronics today Wune 2))2.

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