Lecture 1 IC Technology

R. Dutton, B. Murmann Stanford University

R. Dutton, B. Murmann

EE 114 (HO #4)

Technological Progress
Vacuum Tube 1906 Transistor 1947 Modern Discrete Transistors

Integrated Circuit 1958

Modern CMOS

Jack Kilby
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Kilby, Moore and Bob

Bob Gordon Moore

Bobs Summer Internship Fairchild Semiconductor (1967)

13 12 11 10 9 8 7 6 5 4 3 2 1 0 LOG2 O OF THE NUMBER OF C COMPONENTS PER INTEGRAT TED FUNCTION

G.E. Moore Electronics, 1965

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Transistor IC
R. Dutton, B. Murmann

1959 1960 1961 1962 1963 1964 1965 1966 1967 1968 1969 1970 1971 1972 1973 1974 1975 YEAR
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Economics

[European Nanotechnology Roadmap]

R. Dutton, B. Murmann

EE 114 (HO #4)

Signal Processing
Theres a big, big world out there--both application space and viable technology
Digital Signal Processing (DSP) Analog Signal Processing

Apps: Geo-(ULF); Bio-(LF); Voice; AM; FM

Apps: Base-band-->multi-GigaHz

Need Analog-to-Digital Conversion (ADC); basically solve the signal processing digitally (I.e. mainstream CMOS)

Determined by combination of application requirements and technology capabilities

Low-voltage Medium-voltage (CMOS)

R. Dutton, B. Murmann

High-voltage (CMOS++, BJT+)

RF

OE

(CMOS+, BJT)
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(Si, III-Vother)
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(BJT voltage limits)

(Silicon/MOS limits--freq., photons etc.)

Technology Comparison
Parameter
Device Speed Noise Transconductance Intrinsic gain

CMOS
High Poor Poor Poor

Si BJT
High Good Good Better

SiGe BJT
High Good Good Best

Why y use CMOS for analog g integrated g circuits? Low cost, driven by high volume digital ICs Integration with high density digital circuits
BiCMOS tends to be expensive

R. Dutton, B. Murmann

EE 114 (HO #4)

Historic Comment + Prospective View

Historic Comment: Bipolar Technology is COOL and has evolved dramatically using both Si-mainstream (I.e. SiGe BiCMOS) and with compound materials (I.e. InP etc.). (the new) EE214 will include consideration of these trends. You can also (if you are interested) look at the notes from EE215 (no longer offered eeclass.stanford.edu/spr08/ee215) offered, eeclass stanford edu/spr08/ee215)

Prospective View: CMOS is the circuit building material of choice in the information age. Hence, this class will focus exclusively on CMOS circuits.

The previous slide mentions CMOS+ and CMOS++ versions. This simply refers to the fact that mainstream (low-voltage) CMOS has limits in terms of voltage g and circuit components p ( (for analog) g) that, if they y add masks and cost to the IC fabrication process, are not broadly available*.

Footnote: selectively analog options are certainly available for a cost and depending on your relationship with the supplier/foundry (money does talk)
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How to Build an nMOS Transistor

Side note: n stands for negative carrier type (I.e. electron) p stands for positive carrier type (I.e. (I e hole)

Slide Courtesy S. Mitra, EE271

poly n+ p n+

Diffusion is made by adding (diffusing) impurities into the silicon n+ diffusion means the region has a lot of n impurities (dopant atoms) Lots of impurities increase its conductivity (lower resistance) p regions have p impurities and moderate #s of impurities (+ means lots) p region i i is f formed d fi first t (f (for example, l wafer-level f l ld doping), i ) The n+ over-doped parts of the p region form the n+ regions n+ dopant is added after the poly is patterned so poly blocks dopant pMOS transistor is identical except that ps and ns are swapped

R. Dutton, B. Murmann

EE 114 (HO #4)

CMOS Has Two Transistor Types

Slide Courtesy S. Mitra, EE271

g Look at cross-section s nMOS n+ p n+ to p substrate substrate b t t must t be b p substrate b t t must t be b n n+ d pMOS p+ n p+

CMOS devices require two types of substrates nMOS must be in a p region; pMOS must be in an n region Region is called a well
R. Dutton, B. Murmann EE 114 (HO #4) 9

Well Requirement
Slide Courtesy S. Mitra, EE271

OFF -V

n+ p

n+ tied to most negative potential Gnd.

OFF +V

p+ n

p+ tied to most positive potential V dd

Well must to be tied to a power supply to keep the isolation diodes reversed biased. This is accomplished by using well contacts (ohmic connection to the well)
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R. Dutton, B. Murmann

Aside: Well Contacts

Slide Courtesy S. Mitra, EE271

Formed by placing p+ doped region in a pwell or n+ doped region in a nwell

These regions make good electrical contact (ohmic, not diode) to the well and thus the well potential is made equal to the potential of the diffusion

Need to have at least one well (substrate) contact in each well well.

These contacts are then connected to the correct power supply to ensure that the diodes are always reversed biased.
R. Dutton, B. Murmann EE 114 (HO #4) 11

Fabricating Chips
Slide Courtesy S. Mitra, EE271 Masks

Chips Processed Wafer

Processing Wafers (todays wafers 300mm or 12 inch.) Chemicals

R. Dutton, B. Murmann

EE 114 (HO #4)

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Photolithography The Key

Slide Courtesy S. Mitra, EE271

Take an image on a plate of glass Project on to a wafer Like photo photo-enlarger enlarger EXTREMELY HIGH Resolution (and HIGH COST $100M+) If you printed the US at this resolution See every house in nation This equipment is KEY to determining channel length L (and resulting performance)

R. Dutton, B. Murmann

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Basic Fabrication Steps

Slide Courtesy S. Mitra, EE271

Transfer an image of the design to the wafer Do something to imaged parts of wafer Implant add impurities to change electrical properties Deposit deposit metal or insulator from chemical wafer Grow place silicon in oxidizing ambient Etch Cut into surface of topmost layer(s) Polish Make surface of wafer flat Strip off imaging material (resist) and proceed to next step Key points: Entire die image transferred in one step (stepper) Entire wafer surface processed at once (multi-steps) Economical because everything done in parallel
R. Dutton, B. Murmann EE 114 (HO #4) 14

Basic Processing
Slide Courtesy S. Mitra, EE271 Start with wafer at current step

Spin on a photoresist (PR)

Photons that entered (through mask) here allow selective PR removal

Pattern photoresist with mask

Step specific processing etch, implant, etc...

Pattern transfer to underling layer. In this case an ETCH of the blue layer

Wash off resist

R. Dutton, B. Murmann

EE 114 (HO #4)

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Making Transistors - 1
Slide Courtesy S. Mitra, EE271
P-type N-well counter-doped

Implant N-Well

wafer material

Etch away silicon where there wont be transistors

Deposit oxide in trenches

Polish top of wafer flat and expose silicon

oxide isolation

R. Dutton, B. Murmann

EE 114 (HO #4)

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Making Transistors - 2
Slide Courtesy S. Mitra, EE271

Implant gate and grow oxide

Implant sets turn-on voltage of transistor to the correct value. value

Deposit and Etch Polysilicon for gate

Implant source and drain

Diffusion self aligns to edges of gate

Coat Poly and Silicon with metal to reduce Resistance (C i)

R. Dutton, B. Murmann

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Actual Transistors
Slide Courtesy S. Mitra, EE271 TSMC 0.13 TI 0.09

Source: Nikkei Microdevices 11/00

Source: Nikkei Microdevices 9/02

(To-ra-n-zi-su-ta) (To-ra-n-zi-su-ta)

Much more complex structure generated from drawn polysilicon gate

R. Dutton, B. Murmann

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Making Wires - 1
Slide Courtesy S. Mitra, EE271 Deposit Dielectric

Etch metal trenches

Etch via trench

R. Dutton, B. Murmann

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Making Wires - 2
Slide Courtesy S. Mitra, EE271

Deposit p metal

Polish surface back

Same steps can be repeated to add additional metal layers

R. Dutton, B. Murmann

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Wire Scaling
Slide Courtesy S. Mitra, EE271

As chips scale, wires have increased in number and complexity Cross-sectional Cross sectional areas and spacings have decreased

Intel's 0.25m process, 1997

Intel's 0.13m process, 2002 Drawn to scale

Only this part is substrate and transistors
Source: www.intel.com

R. Dutton, B. Murmann

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45nm CMOS (Intel)

Steve Cowden THE OREGONIAN July 2007

R. Dutton, B. Murmann

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Discrete vs. Integrated Circuits

Discrete Audio Amplifier Integrated CMOS Audio Amplifier

Minimize transistor count Devices usually don't match Arbitrary resistor values Capacitors 1pF10F

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"Unlimited" number of transistors Devices match well (more later) Keep resistors < 10100k Keep capacitors < 1050pF
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R. Dutton, B. Murmann

Diffused Resistors
n-well contact

contact must be at (+) potential

parasitic diodes to worry about

n-well contact

1 2

3 4

p-type diffusion

n-well contact

n-well p-type substrate

R. Dutton, B. Murmann

EE 114 (HO #4)

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Kinds of Resistors
Diffused Resistors ~10-K/sqr (units) Epi Resistors ~K/sqr Epi Pinch (pinched by diffused region) Resistors ~K/sqr Polysilicon Resistors ~0.5-1K/sqr (easy to do) Thin Film Resistors ~100-2K/sqr (extra $$)
poly silicon (or other TF) oxide substrate Comments:

##
1 1

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Matching M t hi between b t resistors i t of f the same type is critical (and useful) Absolute values are hard to achieve in general
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R. Dutton, B. Murmann

Kinds of Capacitors
Cox Cdeplsubstrate

Cox Coxparasitic

poly silicon oxide substrate

metal layers

oxide substrate Comments: Matching between capacitors of the same type is critical Absolute values are hard to achieve in general
R. Dutton, B. Murmann EE 114 (HO #4)

junction capacitors (very bias-dependent)

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