Boosted and Distributed Rail Clamp Networks for ESD Protection in Advanced CMOS Technologies

Michael Stockinger, James W. Miller, Michael G. Khazhinsky, Cynthia A. Torres, James C. Weldon, Bryan D. Preble, Martin J. Bayer, Matthew Akers, and Vishnu G. Kamat*
Motorola, 3501 Ed Bluestein Blvd., Austin TX 78721, USA, tel.: (512)933-6016, e-mail: M.Stockinger@motorola.com * Synopsis Inc., 700 E. Middlefield Rd., Mountain View, CA 94043, USA

Abstract - A new, area efficient, boosted and distributed active MOSFET rail clamp network for I/O pad ESD protection is presented. In addition, a compact new rail clamp trigger circuit with high resistance to false triggering is introduced.

I. Introduction
Increasingly prevalent in advanced CMOS integrated circuits, networks of active MOSFET rail clamps have proven to offer robust, scalable, portable and easily simulated I/O pad ESD protection [1-8]. In a paper presented at this Symposium two years ago [6], we showed that highly efficient ESD protection networks can be built by distributing RC triggered active MOSFET clamps, wired in parallel, in each I/O and power supply pad cell around the perimeter of an integrated circuit. We also provided guidelines for accurate SPICE simulation of these ESD networks and procedures for using these simulations to optimally size key ESD elements to just meet the required ESD performance, while minimizing layout area. In this paper we extend the framework presented in [6] by introducing four significant improvements. First we present a new boosted RC triggered ESD rail clamp circuit configuration, wherein the rail clamp NMOS gate is boosted to a voltage higher than the device drain during an ESD event. Compared to prior approaches, this boosted configuration allows for up to 2.3x reduction in the clamp NMOS width and layout area, while still retaining comparable ESD protection. In addition, when implemented in a distributed rail clamp network, the boosted approach enables the effective use of remote rail clamp trigger circuits, thereby eliminating the need for a trigger circuit local to the clamp NMOS in each I/O pad cell. This further reduces layout area. Second, we introduce a more comprehensive distributed ESD network optimization strategy which allows for precise sizing of the high-current ESD elements in the I/O pad cell. In our optimizations, we size the ESD elements to move the required ESD current and protect both the fragile NMOS and PMOS output buffers for all worst case zap conditions, while occupying an absolute minimum combined layout area. Third, we further extend the distributed clamp idea presented in [6] to its ultimate embodiment. Whereas in our previous paper distributed networks were formed from discrete clamps placed in each I/O and

power supply pad cell, here we introduce a new approach where clamp NMOS devices are continuously distributed along the IC periphery included not only in pad cells, but also between pad cells to fill any gaps in the continuous distributed network. We will show that this further reduces ESD layout area and increases design modularity. Fourth, we introduce a new robust and compact slew rate sensing trigger circuit for active MOSFET ESD rail clamps, which is significantly superior to prior circuits in terms of immunity to false triggering due to both power supply noise and during very fast normal ramp-up of the VDD power supply. In this paper, we will demonstrate that the combination of all these improvements, when applied to products in both 130nm and 90nm CMOS process technologies [9,10], may produce the most layout area efficient on-chip ESD protection yet reported in the literature. In addition, we will show that the ESD networks described herein are proven on a large number of products, with a very high rate of first pass ESD qualification.

II. Boosted ESD Rail Clamps

Before introducing the boosted ESD rail clamp configuration, we first review a typical non-boosted design. In Figure 1, we show a simple schematic demonstrating the use of a single non-boosted VDD to VSS active MOSFET rail clamp for ESD protection of an adjacent pair of I/O pads. Throughout this paper we assume that all output drivers and ESD MOSFETs are formed with the 2.5V, Tox=50, I/O transistors available in both the 130nm and 90nm process technologies. The active MOSFET rail clamp shown in Figure 1 consists of a very simple trigger circuit (RC filter plus three inverter/buffer stages) and a large clamp NMOS M0. In each of the two I/O pad cells, the NMOS output buffer, with the underlying parasitic lateral NPN (LNPN) bipolar junction transistor, and the PMOS output buffer, with the underlying lateral PNP (LPNP) is shown. For ESD protection in each I/O pad cell we add a p+ emitter perimeter intensive vertical PNP (VPNP) device A1 and an n+ perimeter

2003 EOS/ESD Symposium 2003 ESD Association

intensive substrate return diode B. The intended current paths for an I/O1 positive to I/O2 grounded ESD stress are shown with grey arrows in Figure 1. The primary ESD current path is from the I/O1 pad through the forward biased emitter-base junction of A1 to the VDD bus, through M0 to the VSS bus, and finally through the forward biased B diode at the grounded I/O2 pad. A much smaller portion of the ESD current flows directly from I/O1 to local VSS via the collector of A1, bypassing M0 [6]. It is important to note that there is no intended or desired path for ESD current through the LNPN or LPNP devices parasitic to the output drivers. During the I/O to I/O zap illustrated in Figure 1, the LNPN at the positively stressed hot pad (I/O1) and the LPNP at the grounded pad (I/O2) are both at risk of firing if the local MOSFET Vds exceeds Vt1 for these devices. Throughout this paper we assume that both output buffers are configured in the most fragile and compact manner possible, with fully silicided source/drains and no added ballast resistance. TLP measurements with our 120ns pulse duration TLP source have shown that Vt1 for the NMOS (LNPN) is 7.9-8.2V, while It2 is effectively zero. Vt1 for the PMOS (LPNP) is also 7.98.2V, while It2 is much higher, about 3mA/m. These TLP results are valid for 2.5V I/O transistors in both the 130nm and 90nm process technologies. Throughout this paper we will use the term VNBUF to define the peak Vds for the NMOS buffer and VPBUF to define the peak Vds for the PMOS buffer during a simulated ESD event. In order to provide some margin to failure, elements in our ESD networks are typically sized to limit VNBUF and VPBUF to 7V or less during the ESD event. To obtain the ESD device sizes required to achieve this level of protection, we performed SPICE simulations using techniques described in [6]. ESD compact models for A1 and B, calibrated with TLP measurements, were used in all simulations. The simulation goal was to determine the p+ perimeter of A1, the n+ perimeter of B, and the transistor width of M0 to just achieve a 7V target for both VNBUF (in I/O1) and VPBUF (in I/O2) assuming an applied 3.8A ESD current. In the simulated circuit we included a pair of parasitic VDD bus resistors R2=0.2
VDD
VPNP VSS

and used typical device sizes for the ESD diodes A1=384m and B=199m. Based on these simulations we found, for the circuit of Figure 1, that M0=5446m was sufficient to just meet the 7V/3.8A ESD performance target for both VNBUF and VPBUF. Also shown in Figure 1 are nodal voltages during the ESD event. It is interesting to compare the magnitude of the voltage drops across A1 (3.3V), R2+R2 (1V), M0 (2.7V), and B (3.8V) along the primary ESD current path. Note that both the gate and drain of M0 are biased at Vgs=Vds=2.7V, as is typically desired for optimum rail clamp operation. We now introduce the basic concept of the boosted rail clamp configuration. It is well known that for a given Vds, the conductance of an NMOS increases as Vgs is increased. In the ESD stress event illustrated in Figure 1, Vgs for M0 is only 2.7V, much less than the total 7V applied between I/O1 and VSS. In the boosted ESD configuration we have found a way to apply a larger fraction of this total voltage to the gate of M0. In Figure 2, we show a schematic demonstrating the boosted active MOSFET rail clamp configuration. Note that there are only two changes to the nonboosted configuration from Figure 1. First we add a new, very narrow Boost bus, with two parasitic bus resistors R1=20. The Boost bus serves as a power supply bus for the rail clamp trigger circuit. Note that the drain of M0, remains connected to VDD. Second, we add a small 20m p+ perimeter VPNP device A2 in each I/O pad cell. The A2 device couples ESD current onto the Boost bus from the hot I/O pad. Note that the primary ESD current path through A1, M0 and B remains unchanged. Since the trigger circuit draws very little current during an ESD event, there is very little current flow through, or IR voltage drop across, A2 in the hot I/O pad. Therefore the voltage on the Boost bus at I/O1 is only about a diode drop below the I/O1 pad voltage. In addition, an insignificant voltage drop is seen across the two Boost bus resistors R1. Therefore, while Vds for rail clamp NMOS M0 remains 2.7V, Vgs is boosted from 2.7V to 5.8V. By coupling the rail clamp trigger circuit to the zapped pad via a separate Boost bus, we are able to significantly increase the resulting Vgs on clamp
7V
VPNP VSS

7.5V
PMOS

R2

R2

6.5V
TRIGGER CIRCUIT

VDD

PMOS

A1
LPNP

A1
LPNP

M0

6.5V

3.8A

I/O1 Pad

10.8V
LNPN

I/O2 Pad

0V
LNPN

B
NMOS

B
NMOS

3.8V VSS

NMOS CLAMP M0 W = 5446m Vds = 2.7V Vgs = 2.7V Ids = 0.58 mA/m

Figure 1: Non-boosted rail clamp configuration

VSS

Boost

9.6V VDD 7.5V

PMOS

R1 R2

9.6V 7V
VPNP VSS VPNP VSS

R1 R2

9.6V 6.5V VDD

TRIGGER CIRCUIT

Boost

VPNP VSS

VPNP VSS

PMOS

A2

A1
LPNP

A2 0V

A1
LPNP

M0

9.6V

3.8A

I/O1 Pad

10.8V
LNPN

I/O2 Pad

LNPN

B
NMOS

B
NMOS

3.8V VSS

NMOS CLAMP M0 W = 2384m Vds = 2.7V Vgs = 5.8V Ids = 1.34 mA/m

VSS

Figure 2: Boosted rail clamp configuration

NMOS M0, as compared to the circuit in Figure 1. Based on SPICE simulations of this boosted configuration, we found that with both A1 and B unchanged, M0=2384m was sufficient to just meet the 7V/3.8A target for both VNBUF and VPBUF. In this example, M0 in the non-boosted configuration is about 2.3x larger than in the boosted configuration. An obvious concern with the boosted ESD rail clamp configuration is that the clamp NMOS M0 may be at increased risk of damage under the Vgs>Vds boosted bias conditions. The plot in Figure 3 shows how Vt1 of an NMOS transistor in the 130nm technology varies as a function of Vgs. As Vgs is increased from 0V, Vt1 falls from an initial value of 8.1V at Vgs=0V, to a minimum value of 7.2V at intermediate gate bias conditions (Vgs=1V), and then rises again to higher levels when approaching the Vgs=Vds bias condition. The initial decrease of Vt1 is caused by the increase of drain current as Vgs exceeds the NMOS threshold voltage Vth,n. At larger Vgs, the increase of Vt1 is due to the decreased impact ionization rate [11,12]. For Vth,n<Vgs<Vds+Vth,n the number of electron-hole pairs generated in the pinch-off region is dependent on the lateral electric field, which decreases with increasing Vgs. For Vgs>Vds+Vth,n the pinch-off region in the MOSFET channel disappears and impact ionization
10 Vt1 Failure Vds (V) Vgs=Vds
Non-boosted

becomes limited by carrier scattering in the inversion region. The NMOS gate oxide is permanently damaged for transient Vgs greater than about 10V, independent of the applied Vds. Note that Vt1(Vgs) and Vgs<10V describe the safe ESD operating regime of the NMOS. For all network optimizations described in this paper we ensured that the boosted NMOS clamp devices stay well within the defined boundaries of safe operation.

III. Distributed Boosted Networks

Similar to the distributed networks described in [6], the single large boosted active MOSFET rail clamp NMOS M0 described above may easily be broken into multiple, much smaller clamp NMOS devices M1, wired in parallel, and distributed in each of the I/O and power supply pad cells for efficient, uniform ESD protection. A conceptual schematic of a nine pad cell group utilizing such a distributed boosted rail clamp network is shown in Figure 4. Eight identical I/O pad cells and a VSS pad cell are placed along Boost, ESD, Trigger, and VSS buses. The incremental parasitic bus resistances R1, R2, R3, and R4 for each bus are shown between each pad cell. Each of these bus resistance values are measured from the center line of one pad cell to the center line of the adjacent pad cell. While only nine pad cells are shown here, it is assumed that this network is extended in a closed ring around the entire IC periphery, containing at least 50 equally spaced pad cells. R1, R2, R3, and R4 are assumed constant between all pad cells in the ring. In the boosted and distributed ESD rail clamp network of Figure 4, the ESD bus serves as the high current rail clamp anode bus and the VSS bus serves as the cathode bus. Therefore, it is important that these two buses be as wide as possible to ensure low resistance to ESD currents flowing around the chip periphery. The ESD bus may b e either a floating bus, not directly connected to any external power supply, or may also serve as a positive power supply (i.e. VDD) bus. The Boost and Trigger buses do not move

6 4 2 0 0

Safe Operating Regime

I/O1 I/O2 I/O3 I/O4

Boosted

6 Vgs (V)

10

Figure 3: Boundaries of safe NMOS operation in the Vds and Vgs voltage space

Oxide Failure.

significant current during an ESD event, and may therefore be much more narrow and resistive. As described in [6], for applications where the ESD bus covers only a segment of the IC periphery, a distributed network of small rail clamp NMOS devices M1 may be perfectly terminated by simply placing appropriately sized terminating large rail clamp NMOS devices M0 at each end of the ESD bus segment. Large rail clamp NMOS devices fit most easily in VDD or VSS pad cells which may then be placed on both ends of the ESD bus segment. It was shown in [6] that, independent of the number of pad cells in an ESD ring or in a terminated bus segment, the ESD elements may be sized so that the worst case ESD performance for all I/O pads is identical. This is a primary benefit of distributed ESD rail clamp networks. Each I/O pad cell in Figure 4 contains a small rail clamp NMOS M1 and ESD diodes A1, A2, and B. A1 and A2 represent the emitter-base junction diodes of the VPNP devices A1 and A2 from Figure 2. Note that the VSS pad cell in Figure 4 contains the same ESD elements as the I/O pad cells and also provides a convenient location for a remote ESD rail clamp trigger circuit. This trigger circuit is defined as remote because, in addition to the local NMOS M1, it also drives, via the Trigger bus, NMOS devices M1 beyond the extent of the VSS pad cell. With remote trigger circuits, no local trigger circuits are needed in the I/O pad cells, saving significant layout area. For optimum ESD network performance we typically place trigger circuits in every VDD and VSS pad cell and, if needed, in special narrow spacer cells, and require that no I/O pad may be further than five pad cells away from a trigger circuit. Smaller or larger trigger circuit placement frequency is possible depending on bus resistance values and trigger circuit design.

IV. Network Optimization

SPICE-based optimizations were performed on the boosted and distributed ESD network from Figure 4,
10.3 7.2 10.2
R1 R2 R3

using the techniques described in [6]. For all optimizations, a network netlist containing 100 pad cells in a closed ring was used. Optimizations were run to determine, for a given pair of ESD and VSS bus resistance values (R2 and R4), the minimum p+ perimeter of A1, the minimum n+ perimeter of B, and the minimum width of M1, such that the three devices occupy a minimum combined layout area in the I/O pad cell. The optimizations were constrained by the requirement that, for a 3.8A peak current I/O pad to adjacent I/O pad ESD event, both VNBUF (in the hot pad) and VPBUF (in the grounded pad) not exceed either 6V, 7V, or 7.9V, depending on choice of this optimization target. In addition, we required that the rail clamp NMOS devices must all operate within the safe operating region as defined in Figure 3. During the optimizations, A1, B, and M1 for all the pad cells in the network were adjusted simultaneously. For all simulations, the size of VPNP device A2 was set to 1/16 the size of A1. Incremental Boost and Trigger bus resistors (R1 and R3) were fixed at 5 and 17, respectively. Optimizations were repeated for a range of typical R2 and R4 values. Worst-case distributed bus capacitances were included in all transient simulations, but did not show any significant impact on ESD performance. The input variables and example output results for these optimizations are shown for our 130nm process technology in Table 1 and for our 90nm process technology in Table 2. It can be seen in the highlighted row in Table 1 that for the 130nm technology, with a 7V target for both VNBUF and VPBUF, and with R1=R2=0.165, the optimum ESD device sizes are A1=250m, B=162m, and M1=186m. For comparison, the corresponding values for a non-boosted network, shown at the bottom of Table 1, are A1=347m, B=238m, and M1=322m. Note that all three devices are significantly smaller in the boosted configuration. The total combined layout area of all I/O pad cell ESD elements in this boosted example is 860m2, while the corresponding area for the non-boosted network is 1126m2. This layout area includes the A1, A2, B, and
Boost ESD Trigger
R1 R2 R3

10.3 7 10.2

R1 R2 R3

10.3 6.7 10.2

R1 R2 R3

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R1 R2 R3

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10.2 6.3 10.2

R1 R2 R3

10.2 6.1 10.2

R1 R2 R3

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R1 R2 R3

10.2 6 10.2

A2

M1 A1

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3.8A

I/O1 Pad
11.7
B

I/O2 Pad
B

I/O3 Pad
B R4 R4

I/O4 Pad
B R4

VSS Pad
B

TRIGGER CIRCUIT

I/O5 Pad
B

I/O6 Pad
B R4 R4

I/O7 Pad
B R4

I/O8 Pad
B

4.7

R4

4.3

4.6

4.8

4.9

VSS

R4

5.1

5.2

5.3

5.4

Figure 4: A pad cell group representing an optimized boosted and distributed active MOSFET rail clamp network. Nodal voltages are shown for a positive 3.8A ESD event applied at I/O1 with I/O2 grounded

Table 1: Summary of 130nm technology optimization inputs and outputs utilizing the ESD network of Figure 4
Target Pad Voltage R2, R4 Bus Resistance ( ) 0.110 0.165 0.220 0.275 0.110 0.165 0.220 0.275 0.110 0.165 0.220 0.275 0.165 Optimum A1 Optimum B Perimeter Perimeter ( m) ( m) 291 306 317 325 237 250 258 270 202 212 221 227 347 191 205 216 226 151 162 170 181 125 134 142 147 238 Optimum M1 Width (m) 201 253 299 338 147 186 222 245 120 152 178 204 322 Total Combined Layout Area (m 2) 930 1003 1063 1114 804 860 907 947 730 776 814 847 1126+350

V. Boosted Network Discussion

To further demonstrate the benefits of the boosted configuration in a distributed rail clamp network, we show in Figure 4 nodal voltages at various points in the network when using network targets and ESD device sizes from the highlighted row in Table 1. Note that while significant and unavoidable voltage drops occur across A1 in I/O1 and along the ESD bus with increasing distance away from the hot pad, the Boost and Trigger bus voltages remain nearly constant at a much higher voltage. With all the distributed clamp NMOS devices M1 biased at Vgs>Vds, the conductance of the distributed clamp network is greatly increased, compared to non-boosted networks. None of the M1 device biases approach their failure thresholds. This is shown in Figure 3, where (Vgs, Vds) datapoints are plotted for M1 in I/O1, I/O2, I/O3 and I/O4. A further advantage of the boosted configuration in a distributed ESD network is that remote trigger circuits may now be efficiently used. Since there is very little IR voltage drop along the Boost and Trigger buses, trigger circuits may be placed both some distance from the stressed pad and some distance from the distributed clamp NMOS devices they drive. In a non-boosted network, large IR voltage drops along the ESD bus make it almost impossible to effectively use remote trigger circuits in this manner. In summary, there are three primary benefits of the boosted and distributed active MOSFET rail clamp configuration over the non-boosted configuration; Benefit 1: The trigger circuit is coupled to any stressed I/O pad via an A2 device separate from the high current A1 device. Therefore the large voltage drop across A1 is not seen at the trigger circuit. Benefit 2: The trigger circuit is coupled to any stressed I/O pad via a Boost bus separate from the high current ESD bus. Therefore the large voltage drops along the ESD bus are not seen at the trigger circuit. Benefit 3: Due to the fact that the Boost bus voltage remains relatively constant over a wide area, remote trigger circuits may be effectively used. Therefore the I/O pad cells need not contain local trigger circuits, saving significant layout area. It should be pointed out that the boosted and distributed ESD network described above does have one clear weakness, which must be addressed in the network design. For ICs where the ESD bus is also a VDD bus connected to an external pad, VDD zaps positive to grounded I/O can be a problem. Under this zap condition, the rail clamp network is not as strongly boosted as in zap paths where the ESD current is coupled onto the VDD bus via an A1 diode. We define the ESD network under these VDD positive zaps as being partially boosted because, while we lose Benefit 1 listed above, we retain Benefits 2 and 3. We

6 6 6 6 7 7 7 7 7.9 7.9 7.9 7.9 non-boosted: 7

Table 2: Summary of 90nm technology optimization inputs and outputs utilizing the ESD network of Figure 4
Target Pad Voltage R2, R4 Bus Resistance ( ) 0.110 0.165 0.220 0.275 0.110 0.165 0.220 0.275 0.110 0.165 0.220 0.275 0.165 Optimum A1 Optimum B Perimeter Perimeter ( m) ( m) 131 140 150 156 104 111 117 122 87 92 98 102 157 133 143 153 159 106 113 120 125 88 93 100 104 162 Optimum M1 Width (m) 175 226 266 304 127 164 196 224 100 132 155 180 322 Total Combined Layout Area (m 2) 542 590 630 664 475 511 541 567 436 465 489 510 679+300

6 6 6 6 7 7 7 7 7.9 7.9 7.9 7.9 non-boosted: 7

M1 devices, as well as all required interconnects, buses, and guardrings. While for the boosted network this is everything required for ESD protection in the I/O pad cell, this area does not account for the local trigger circuit required for the non-boosted network, which may add about 350m2 area in every I/O pad cell, as shown in the last row of Table 1. All of these numbers reflect conservative layout used on a large number of qualified (five and six layer metal) 130nm process technology products. As shown in Table 2, even smaller I/O pad ESD device sizes are required in the 90nm technology. For an input target voltage VNBUF=VPBUF=7V, and R2=R4=0.165, the optimization output values are A1=111m, B=113m, and M1=164m. The corresponding optimum values for a non-boosted network, shown at the bottom of Table 2, are A1=157m, B=162m, and M1=322m. The total combined layout area for all I/O pad cell ESD elements in this boosted example is 511m2, while the corresponding area for the non-boosted network is 679m2 plus about 300m2 for the required local trigger circuit. Note that the 90nm A1 and B device sizes are much smaller than the corresponding 130nm devices. This difference is due primarily to a much greater diode conductance per unit layout area.

provide a special subcircuit in each trigger circuit, which pulls the Boost bus up to the full ESD bus voltage whenever VESD>VBoost. However, this may not adequately protect the PMOS output buffer in the grounded pad. It is possible that the PMOS in the grounded I/O pad may be stressed such that VPBUF>Vt1. We have found three possible approaches to address this problem. In the first approach, we change nothing in the ESD network, allow the LPNP to fire, and rely on Vt2>Vt1 to protect the PMOS. We have done this on several qualified products and have seen no problems. However this approach violates our goal to hold Vds below Vt1 for all output buffers. In the second approach we increase the sizes of B and M1 in each I/O pad cell to reduce VPBUF to less than Vt1, even for VDD positive zaps. The obvious disadvantage with this approach is that it adds up to 15% to the total ESD layout area in the I/O pad cell. However, since we retain Benefits 2 and 3, it is greatly preferable to non-boosted networks. In the third and generally most desirable approach, we place large clamp NMOS devices M0, in each VDD pad cell, to locally compensate for the ESD clamp performance reduction with hot zaps at VDD. Therefore, here we use large clamp NMOS devices M0 for two purposes; first to terminate a bank of distributed small rail clamp NMOS devices M1, and second to locally compensate for hot zaps at VDD. In the most difficult scenario, when a VDD pad cell is placed at one end of a VDD bus segment, we require two large rail clamp NMOS devices M0 at that end of the bus segment. One large clamp serves to terminate the network of distributed small clamp NMOS devices M1, while the second large clamp NMOS M0 serves to locally compensate for hot zaps at the VDD pad. A second optimization may be easily run to determine the appropriate large rail clamp NMOS M0 width to meet both of these requirements. The clear advantage of this approach is that we always guarantee VPBUF<Vt1 and retain the absolute minimum layout area for the space-critical I/O pad cell.

VI. Continously Distributed Clamps

Up to this point, we have assumed that the distributed networks were formed from discrete clamp NMOS devices M1 placed in each I/O and power supply pad cell, and separated along the chip periphery by constant incremental ESD and VSS bus resistors R2 and R4. One problem with this approach is the following: If we assume that all the pad cells are abutted in the I/O ring, then we will extract the smallest possible values for both the incremental bus resistors and for ESD devices A1, B, and M1. However, if we then use these same device sizes in a subsequent chip design with significant spacings between pad cells, the ESD performance will degrade,

since the incremental bus resistances must increase. We now propose an effective and simple solution to this problem. In any IC design where there are significant gaps between pad cells, additional variable width spacer clamp NMOS devices M1 may be placed. The pad cell and spacer clamp NMOS devices abut around the IC periphery, each acting as segments in a cumulative, continuously distributed rail clamp NMOS. In a typical configuration we form the clamp NMOS M1 with an array of very short transistor fingers, placed perpendicular to the die edge, like a row of dominoes on edge. We typically place this ESD rail clamp NMOS network in a continuous very narrow band, adjacent to the die edge, around the integrated circuit. A major advantage of this continuously distributed rail clamp NMOS configuration is that we can size ESD elements assuming abutted pad cells, yielding the smallest possible ESD devices. Then, in any chip application which requires gaps between pad cells, we simply insert spacer rail clamp NMOS M1 cells, and retain the target level of ESD performance. This approach allows for minimum M1 area in the region of each I/O pad cell, and no variability in ESD performance from one pad to the next, while allowing the maximum flexibility to place pad cells around the IC periphery with any arbitrary spacing. It turns out that the distributed network shown in Figure 4 offers significant advantages in design simplicity, modularity and flexibility. In many cases, we design and lay out only five unique ESD elements for a family of ICs. One standard ESD cell containing the A1, A2, B, and M1 devices, and overlying metal for the four ESD-related buses, is placed in every single I/O, VDD and VSS pad cell. The second cell contains a large rail clamp NMOS M0, which may be dropped into any VDD or VSS pad cell for ESD bus segment termination or local VDD compensation. The third cell contains the remote ESD rail clamp trigger circuit, which may be placed in VDD or VSS pads or in spacer cells as desired. The fourth cell is a variable width parameterized spacer rail clamp NMOS M1 cell, with overlying buses, stretchable in layout to fit any arbitrary gap between pad cells. The fifth and final cell is a modified spacer cell for the chip corners. An entire ESD protection network can easily be built with multiple instances of just these five modular cells.

VII. Slew Rate Detecting Trigger Circuit

ESD trigger circuits are required in active MOSFET rail clamps to detect an ESD event and to turn on the clamp device until the end of the ESD event, typically for 500ns to 1s. A transient trigger circuit detects a fast rising voltage signal, which is characteristic of an ESD event. Usual ESD rise times are between 100ps

Boost VDD R VRC C

rise time detector RC= 866ns

Boost VDD R V RC C
rise time detector RC = 37.5ns

M0 Vout
predriver

R2 V out V R2C2 M2

C2

VTrig

M0 V Trig

on-time control circuit

VSS
Figure 5: Active MOSFET rail clamp with conventional rise time detector

VSS
Figure 6: Active MOSFET rail clamp with conventional rise time detector and separate on-time control circuit

and 60ns. False triggering during normal power-up can occur if the rise time of VDD is detected as an ESD event, especially in applications where the power supply is hot-plugged to the chip. To maximize the available VDD rise time range for power-up, the ESD detection range needs to be tailored to the maximum expected ESD rise time. Figure 5 shows a simplified schematic of an active MOSFET rail clamp using a conventional transient trigger circuit that consists of an RC filter and three CMOS inverters [1,2,4,6,13-15]. The RC stage and the first inverter form a rise time detector, while the second and third inverters serve as predrivers that drive the gate of the large clamp NMOS M0. During a fast rising voltage signal VBoost on the Boost bus, the RC stage delays the voltage rise on the RC node VRC. The output of the rise time detector Vout goes high, which turns on M0. This simple transient trigger circuit uses just one time constant for both the ESD detection and the on-time control of the rail clamp. Therefore, the RC time constant must be quite large (e.g. 866ns) in order to ensure that the rail clamp stays turned on for the entire duration of an ESD event (e.g. 600ns.) This requires large R and C devices and increases the susceptibility to false triggering during power-up because the ESD detection range is unnecessarily wide. Another transient trigger circuit utilizes separate time constants for ESD detection and on-time control, as shown in the simplified schematic of Figure 6 [16]. The topology of the rise time detector is the same as in Figure 5, but now the RC time constant of the detector can be designed specifically for a desired ESD detection range, e.g. 60ns. This requires much smaller R and C devices and improves the immunity to false triggering. A separate on-time control circuit, or monostable latch, keeps the clamp NMOS M0 turned on for the expected maximum duration of an ESD event, e.g. 600ns. The rise time detector provides only a short voltage pulse that triggers the on-time control circuit by turning on NMOS M2 and, consequently, M0 through the last inverter. The ontime is set by a second RC stage, which can be found in the on-time control circuit (R2, C2.) At the end of the voltage pulse provided by the rise time detector,

M2 turns off. Capacitor C2 connected to the input node of the last inverter is slowly discharged through resistor R2 until the inverter finally flips its state and turns M0 off. Figure 7 demonstrates the operation of the rise time detector of Figure 6. A linear voltage ramp on the Boost bus from 0V to 4V is used to investigate the trigger performance. In Figure 7a the rise time of the voltage ramp is 60ns, which equals the limit of the ESD detection range chosen for this example. The RC node voltage VRC is initially zero and starts to pick up with the voltage ramp, but with a characteristic delay time equal to the RC time constant. The time dependent RC node voltage can be derived analytically, t VRC (t ) = S R C e R C 1 + t , (1) with S as the slew rate of VBoost, here 4V/60ns. The inverter switch point Vswitch shown in Figure 7 is assumed to be precisely half of VBoost. For the time VRC stays below Vswitch, the detector output Vout will be high indicating an ESD event. If Vout exceeds the trigger voltage Vth,n of the on-time control circuit (the threshold voltage of NMOS M2), the clamp turns on. In Figure 7b the rise time of VBoost is 80ns, which is slightly above the ESD detection range in this example. Figure 7b shows that, if the rise time of VBoost is outside the ESD detection range, the voltage pulse Vout is shorter than the Boost ramp. This results in an early time-out of the on-time control circuit due to incomplete charging of capacitor C2 because the discharging of C2 starts from a voltage level on VR2C2 that is lower than the maximum ramp voltage (4V in this example.) The early time-out behavior for rise times outside the ESD detection range is depicted in Figure 8. It shows the gate voltage of M0 for various rise times as labeled in the figure. For rise times below 60ns, the full ontime of 600ns is achieved. If the rise time is increased above 60ns as shown in Figure 8, the on-time decreases until the clamp does not trigger at all for rise times above 250ns. Therefore, rise times above 250ns can be safely used for power-up. In the powerup regime the RC node voltage VRC exceeds the

(Volts)

VBoost VRC

Stockinger_M_ESD_Symp_paper_rev9d. (Volts) doc V

Boost

VTrig (V)

(a)

Vout Vswitch

(b)
Vout

VRC

60 ns
Vswitch

210 ns 250 ns

100 ns 180 ns

Vth,n

Vth,n

time (ns)

time (ns)

Figure 8: Early time-out of the rail clamp with conventional rise time detector

Figure 7: Operation of the rise time detector of Figure 6 for (a) 60ns rise time and (b) 80ns rise time

inverter switch point Vswitch at a time when VBoost is still smaller than the threshold voltage of Mclamp, which, therefore, cannot turn on. The rise time range between 60ns and 250ns shows some ESD triggering, but suffers from early time-out of the on-time control circuit. To achieve a certain ESD detection range, the RC time constant of the rise time detector of Figure 6 needs to be tuned so that the cross-over between the RC node voltage VRC and the inverter switch point Vswitch happens precisely at the end of a Boost ramp operating at the ESD detection limit. Using (1) and assuming that the inverter switch point is half of VBoost, the RC time constant can be derived from solving the implicit formula x t (2) 1 exp ( x ) = 0 , x = DL 2 R C with tDL as the ESD rise time detection limit. This results in t R C = DL , (3) 1 .6 or 37.5ns for the example of Figure 7. The rise time detector of Figure 6 suffers from a wide transition zone in the rise time range between the ESD regime and the power-up regime, as already shown earlier. In the given example of Figure 7 and Figure 8 this transition zone is more than three times larger than the ESD detection range. Worst case temperature and process conditions can cause this transition zone to become much wider. Consequently, this type of detector does not qualify for fast power-up applications. The detailed schematic of a detector with a greatly improved detection scheme is shown in Figure 9 [17]. The RC filter is implemented using MOSFET devices M3 with resistance R and M4 with capacitance C. The added compensation capacitor M5 is quite small compared to M4 and helps to raise the voltage on VRC at the beginning of a voltage ramp on VBoost before M3 turns on. The improved detection scheme is achieved by a modified switch point of the inverter circuit connected to VRC. Compared to Figure 6, the

conventional CMOS inverter is replaced by an inverter circuit that consists of a PMOS M7, a load device M6, and a current source M8, all connected in series. Compared to a conventional CMOS inverter with a voltage switch point that equals half of VBoost, the voltage switch point of this new inverter circuit has a constant voltage offset Voff from VBoost. This voltage offset is set by the voltage drop across M6 plus the gate-source voltage of M7. The cross current is set by current source M8. This results in g m ,M 8 , (4) Voff = 2 Vth , p + (VBoost Vth ,n ) g m ,M 6 + g m ,M 7 where Vth,n and Vth,p are the NMOS and PMOS threshold voltages, respectively, and gm,M6, gm,M7, and gm,M8 are the transconductances of M6 , M7, and M8, respectively. If gm,M8 is large compared to gm,M6 and gm,M7, Voff is kept fairly constant at 2Vth,p. The on-time control circuit leverages the large intrinsic gate capacitance of M13 as the primary charge storing element to achieve an on-time of 600ns. The slow discharge of the gate capacitance of M13 is accomplished by a current source M11, which is biased by M9 and M10 and only turned on during an ESD event when VTrig is high. During normal operation, reset device M12 guarantees that the clamp is fully turned off by strongly pulling up the input of the last inverter stage M13, M14. An important feature of this trigger circuit is that the only leakage current on VBoost
Boost VDD
M6 M5 M3 VRC RC= 21ns slew rate detector M7 Vout M10 M8 M2 on-time control circuit M14 M9 M11 M12 M13 VTrig M0

M4

VSS
Figure 9: Active MOSFET rail clamp with new slew rate detector and on-time control circuit

is off-state leakage. No device operates in the active regime during normal powered-up operation of the chip. Figure 10 demonstrates the operation of the new detector of Figure 9. All circuit simulations were performed using 2.5V, Tox=50, I/O transistors of our 130nm technology [9]. The applied voltage ramps are the same as in Figure 7 to allow for a direct comparison with the rise time detector of Figure 6. Due to the constant (vertical) voltage offset Voff between the inverter switch point Vswitch and VBoost, Vswitch rises with the same slew rate as VBoost. Therefore, the (lateral) time offset toff between the VBoost voltage ramp and Vswitch becomes Voff toff = , (5) S with S as the slew rate of VBoost. The RC node voltage VRC asymptotically approaches the VBoost slew rate with a (lateral) time offset of RC to VBoost as derived in (1) and also shown in Figures 7 and 10. The new detection scheme is based on a comparison between the time offset of the voltage on VRC and the slew rate dependent time offset toff of the inverter switch point Vswitch. For a given ESD slew rate detection limit SESD (the smallest VBoost slew rate that is detected as an ESD event) the RC time constant can be calculated from (5) and becomes Voff R C = , (6) S ESD In the example shown in Figure 10 Voff is 1.4V and SESD is 4V/60ns. This results in an RC time constant of 21ns. While the detector of Figure 6 effectively detects a rise timethis can be concluded from (2), which calculates the RC time constant only from the ESD rise time detection limitthis new circuit detects a slew rate, and is therefore called a slew rate detector. The inverter switch point design of this detector can be considered optimal for the given application as it is matched to the characteristic of the detected signal VRC. The transition zone in the rise time range between the ESD regime and the power-up regime is almost zero compared to 190ns for the detector of
(Volts) VRC Vswitch VBoost
(Volts)

Figure 6. By comparing Figure 10a and Figure 10b it can be seen that, while the VBoost ramp with 60ns rise time is still detected as an ESD event, the 80ns ramp is already in the safe power-up regime. This is further confirmed by Figure 11, which shows the gate voltage of M0 for the two rise times of Figure 10. For rise times below 60ns, the full on-time of 600ns is achieved. For any rise time above 80ns the clamp does not trigger at all, which maximizes the available rise time range for power-up. So far all simulations have been performed assuming typical process conditions. In the process corners, the ESD detection range shifts only marginally from 60ns to 55ns and the onset of the safe power-up regime from 80ns to 95ns. Even if false triggering occurred during power-up or normal chip operation, this trigger circuit would not permanently latch, but rather time-out after 600ns. Simulations have also shown that no false triggering can occur due to noise on the power supply or I/O ringing if the peak-to-peak voltage on VBoost stays below 2V. The built-in voltage threshold Voff of the inverter switch point of Figure 9 simply prevents triggering for small signals on VBoost. While an ESD detection range of 60ns is usually sufficient, there may be applications where an ESD event is slowed down, e.g. due to unusually large capacitance between power supply rails. In that case the ESD detection range needs to be extended by increasing the RC time constant of the slew rate detector (M3 and M4 in Figure 10) at the price of stricter power-up speed requirements. In a typical remote configuration the new trigger circuit requires about 500m2 layout area in our 130nm technology [9]. Though we have only shown boosted trigger circuit implementations in this paper, it should be obvious that the new trigger circuit can be used in non-boosted applications as well.

VIII. Comparison to Alternate ESD Protection Approaches

One of the most common arguments against using active MOSFET rail clamp networks for ESD protection has been the perception that these networks

    
VBoost VRC Vswitch

(a)

(b)


 

Vout

Vth,n
Vout

Vth,n

time (ns)

time (ns)

Figure 10: Operation of the new slew rate detector of Figure 9 for (a) 60ns rise time and (b) 80ns rise time

Figure 11: Time-out characteristic of the rail clamp with new slew rate detector

occupy a huge amount of layout area in the IC, when compared to snapback-based protection approaches. As shown in Table 1 and Table 2, this is simply not the case. It can be seen in Table 1 that with a 7.9V target for both VNBUF and VPBUF (actual failure thresholds), and with R1=R2=0.165, the total combined layout area for all the ESD elements in the I/O pad cell is only 776m2. Assuming ESD failure will occur at 3.8A, the 776m2 area translates into an ESD layout area efficiency of 7.3VHBM/m2. For the 90nm technology the corresponding layout area efficiency is even better, at 12.2VHBM/m2. Recent publications [19,20] quote a single snapback direct I/O pad to VSS LNPN clamp exhibiting up to 5VHBM/m2, and a single SCR clamp exhibiting 4VHBM/m2 layout area efficiency. It is difficult to make direct comparisons here since our area numbers include everything for ESD in the I/O pad cell, not just a single clamp device, for one zap polarity. In addition, these prior references quote efficiency based on failure thresholds of the clamp devices themselves, not failure thresholds in a real circuit application where other fragile devices wired in parallel may fail sooner. In all the networks described here, none of the A1, B, or M1 device biases approach their failure thresholds during the ESD stress. For 130nm CMOS process technologies and beyond, we think that the boosted and distributed ESD networks introduced here are the most layout area efficient yet reported in the literature.

[2] S. Dabral, R. Aslett, and T. Maloney, Core Clamps for Low Voltage Technologies, EOS/ESD Symposium Proceedings, 1994. [3] T. Maloney and S. Dabral, Novel Clamp Circuits for IC Power Supply Protection, EOS/ESD Symposium Proceedings, 1995. [4] E. Worley, R. Gupta, B. Jones, R. Kjar, C. Nguyen, and M. Tennyson, Sub-micron Chip ESD Protection Schemes Which Avoid Avalanching Junctions," EOS/ESD Symposium Proceedings, 1995. [5] W. Anderson, J. Montanaro, and N. Howorth, CrossReferenced ESD Protection for Power Supplies, EOS/ESD Symposium Proceedings, 1998. [6] C. Torres, J. Miller, M. Stockinger, M. Akers, M. Khazhinsky, and J. Weldon, Modular, Portable, and Easily Simulated ESD Protection Networks for Advanced CMOS Technologies, EOS/ESD Symposium Proceedings, 2001. [7] F. Takeda, J. Miller, Electrostatic Discharge (ESD) Protection Circuit, US Patent No. 6,385,021 B1, May 2002. [8] J. Miller, G. Hall, A. Krasin, M. Stockinger, M. Akers and V.Kamat, Patent application filed with the USPTO. [9] A.H. Perera et al., A versatile 0.13 m CMOS Platform Technology supporting High Performance and Low Power Applications, IEDM Proceedings, 2000. [10] G.C-F Yeap et al., A 90nm Copper/Low-K Bulk CMOS Technology with Multi Vt and Multi Gate Oxide Integrated Transistors for Low Standby Power, High Performance and RF/Analog System on Chip Applications , VLSI Technology Symposium, Honolulu, Hawaii, June 2002. [11] F. Hsu, P.Ko, S. Tam, C. Hu, and R. Mulle, An Analytical Breakdown Model for Short-Channel MOSFETs , IEEE Trans. Electron Devices, vol. ED-29, pp.1735-1740, 1982. [12] S.M. Sze, Physics of Semiconductor Devices, John Wiley & Sons, 1981. [13] N. Tandan, ESD Trigger Circuit, EOS/ESD Symposium Proceedings, 1994. [14] T. Maloney, W.Kan, Stacked PMOS Clamps for High Voltage Power Supply Protection, EOS/ESD Symposium Proceedings, 1999. [15] S. Poon, T. Maloney, New Considerations for MOSFET Power Clamps, EOS/ESD Symposium Proceedings, 2002. [16] J.W. Miller, C.A. Torres, T.L. Cooper, Circuit for Electrostatic Discharge Protection, US Patent No. 5946177, Aug. 1999. [17] M. Stockinger, J. Miller, Patent application filed with the USPTO. [18] C. Richier, et al, Investigation on different ESD Protection Strategies Devoted to 3.3V RF applications (2GHz) in a 0.18um Process, EOS/ESD Symposium Proceedings, 2000. [19] M. Mergens, K. Verhaege, C. Russ, J. Armer, P. Jozwiak, G. Kolluri, and L. Avery, Multi-Finger Turn-on Circuits and Design Techniques for Enhanced ESD Performance and Width-Scaling, EOS/ESD Symposium Proceedings, 2001. [20] M. Mergens, C. Russ, K. Verhaege, J. Armer, P. Jozwiak and R. Mohn, High Holding Current SCRs (HHI-SCR) for ESD Protection and Latch-up Immune IC Operation, EOS/ESD Symposium Proceedings, 2002.

IX. Circuit Level Verification

To the best of our knowledge, all Motorola CMOS products at the 130nm technology node feature distributed active MOSFET rail clamps as described in [6]. The majority of these products also utilize the boosted networks introduced in this paper. These products cover a wide range of applications in the wireless, desktop, networking, and automotive space. We have seen nearly 100% first pass ESD qualification success across this entire protfolio. The small number of failures have always been due to a few weak pins, rather than large scale pin fallout. All failures were due to simple network configuration errors, such as forgetting to terminate a VDD bus segment with a large rail clamp NMOS M0. For the first time in 20 years at Motorola, across an entire CMOS process technology, ESD is not a significant issue affecting product qualifications. We are still awaiting ESD test results from lead 90nm technology products.

References
[1] R. Merril and E. Issaq, ESD Design Methodology, EOS/ESD Symposium Proceedings, 1993.