Lecturer1 179

Introduction to VHDL

Introduction to VHDL The Five Design Units Modeling Styles Concurrent/Sequential Statements
Authored by Dr. Tri Caohuu& Vivek Verma
What is VHDL?

VHSIC (Very High Speed Integrated Circuit) Hardware Description Language VHDL is a description language, not a programming language like C, Pascal, Java. Originally developed for Department of Defense, first released in 1985 as an IEEE standard, last major revision IEEE Std 10761993 Enjoys industry wide acceptance Intel, IBM, Sun Microsystems, NEC, Synopsys, Cadence, etc. Not technology specific but predominantly used for digital system design Primary uses are for design verification through simulation and design creation through synthesis
Authored by Dr. Tri Caohuu& Vivek VermaDr. Tri Caohuu 2006 Andy Davis
Lecture 2
VHDL Capabilities

Exchange medium between chip vendors and CAD tool users Supports a wide range of abstraction levels, design, modeling styles a. Behavioral b. Dataflow c. Structural d. Mixed Clear separation of components architecture and interface Supports both synchronous and asynchronous timing models Various delay constraints can be described Allows defining new data types Supports parameterized design using generics and attributes Is case insensitive and a strongly typed language IEEE and ANSI Standard, therefore very portable
Authored by Dr. Tri Caohuu& Vivek VermaDr. Tri Caohuu 2006 Andy Davis Lecture 2 3

VHDL Primary Constructs
VHDL has five primary design constructs, also known as Design Units, used to describe logic 1. Entity The interface of a logic circuit is represented by entity 2. Architecture Architecture describes a particular implementation of an entity 3. Configuration Configuration binds entities, architectures, and component declarations 4. Package declaration Package allows a convenient way to define and group functions, procedures, types, components, etc. 5. Package body Package body contains the implementation of the functionality exposed by package declaration
Lecture 2
Design Unit : Entity

Entity defines the interface of the hardware module to the outside environment in which it is used Entity declaration syntax structure is as follows
Port is used to pass the declared signals to and from external design Generic is used to pass parameters from higher level design to the module
Example
Lecture 2
Design Unit : Architecture
Architecture is the functionality description of the system declared by the entity It can be a behavioral description or it can be a structural decomposition of the body in terms of simpler components An architecture/entity pair defines a circuit. Multiple architectures can be defined for an entity
signal are any internal signals to be generated inside the module component is used for declaring any external entities to be used in this module description can be either behavioral or structural
Lecture 2
Design Unit : Architecture
Example
architecture dataflow of full_adder is signal temp : bit; begin P1 : temp <= a xor b; P2 : sum <= cin xor temp; P3 : cout <= (a and b) or (a and cin) or (b and cin); end dataflow;
temp is a declared signal , a, b, cin, sum, cout are port signals P1, P2, P3 are optional implicit process labels
Lecture 2
Design Unit : Configuration

Serves two purposes Used to bind an architecture to an entity Used to bind an entity to a component declaration Configuration specification must be placed inside the architecture body Configuration syntax structure is as follows
use clauses are for binding an entity/architecture or an entity/component pair forend for are for defining configuration block specifications, not be confused with for loops
Design Unit : Configuration

Example Library ieee; Use ieee.std_logic_1164.all; Entity counter is Port ( load, clear, clk : in std_logic; data_in : in std_logic; data_out : out integer); End counter; Architecture count_255 of counter is Begin process(clk) Variable count : integer := 0; Begin if clear = 1 then count := 0; else if load = 1 then count := data_in; else if (clkevent) and (clk = 1) and (clk last_value = 0) then if (count = 255) then count := 0; else Count := count + 1; End if; end if; end if; Data_out <= count; End process; End count_255;
Lecture 2
Architecture count_64k of counter is Begin Process (clk) Variable count : integer := 0; Begin If clear = 1 then Count := 0; Elsif load = 1 then Count := data_in; Else If (clkevent) and (clk = 1) and (clklast_value = 0) then if (count = 65535) Count := 0; Else Count := count +1; End if; End if; End if; Data_out <= count; End process; End count_64k;
Configuration small_count of counter is For count_255 End for; End small_count; Configuration big_count of counter is For count_64k End for; End big_count;
Lecture 2
10
Design Unit : Package Declaration

Packages are used to store commonly referenced types, functions, procedures, resolution functions, or components Package declaration may only define the visible contents of the package Example
package my_pkg is -- Package Declaration type bit3 is (`0',`1',`Z'); type bit_array is array (integer range <>) of bit3; component or_gate generic (or_blk_dly : time := 4 ns); port (a0, b0 : in bit; c0 : out bit); end component; component and_gate generic (and_blk_dly : time := 4 ns); port (a1, b1 : in bit; c1: out bit); end component;
component xor_gate generic (xor_blk_dly : time := 4 ns); port (a2, b2 : in bit; c2 : out bit); end component; function citbv (p: integer) return bit_vector; end my_pkg;
Lecture 2
12
Design Unit : Package Body

The package body is essentially a listing of the implementations for functionality exposed by the package declaration Example
package body my_pkg is -- Package body function citbv (p: integer) return bit_vector is Begin case p is when 0 => return "000"; when 1 => return "001"; when others => return "000"; end case;
Lecture 2
13
Package body: conti.

entity and_gate is generic (and_blk_dly : time := 4 ns); port (a0, b0 : in bit; c0 : out bit); architecture andgate of and_gate is begin c0 <= a0 and b0 after and_blk_dly; end; entity or_gate is generic (or_blk_dly : time := 4 ns); port (a1, b1 : in bit; c1 : out bit); architecture orgate of or_gate is begin c1 <= a1 or b1 after or_blk_dly; end; entity xor_gate is generic (xor_blk_dly : time := 4 ns); port (a2, b2 : in bit; c2 : out bit); architecture xorgate of xor_gate is begin c2 <= a2 xor b2 after xor_blk_dly; end; end my_pkg;
VHDL Modeling Styles
Commonly used modeling styles in hardware description are Structural Circuit is described as a network of interconnected components Behavioral Circuit is described as an i/o relationship using sequential statements inside a process Dataflow Circuit is described using concurrent statements Mixed - This style of modeling uses any combination of other styles
Lecture 2
15
VHDL Modeling Styles : Structural

Focus is on how components are interconnected rather than the operation of each fundamental component. Three features of a structural description 1. Ability to define a list of components 2. Definition of signals to interconnect these components 3. Ability to distinguish between multiple copies of same component using labels Example
Lecture 2
16
VHDL Modeling Styles : Behavioral

This style describes a behavior in a program-like (procedural) manner, using the process constructs provided in VHDL Multiple process statements can be used to describe concurrency Notice the following example uses sequential statements inside a process
Lecture 2
17
VHDL Modeling Styles : Dataflow

This style is convenient for illustrating asynchronous and concurrent events, where the delays represent actual hardware component delays It is a realistic way of modeling hardware dependencies and concurrencies Notice the following example uses concurrent statements
Lecture 2
18
VHDL Modeling Styles : Mixed

This style of modeling uses any combination of other styles Notice the following example uses structural, concurrent and sequential statements
Lecture 2
19
VHDL Statements : Sequential
Sequential Statements - These statements execute in a procedural fashion i.e. serially, inside a process Process statement Wait statement Sequential signal assignment Variable assignment Assertion statement Report statement If statement Case statement Loop statement Null statement Next statement Exit statement Function call Procedure call
VHDL Statements : Concurrent
Concurrent Statements: These statements execute in a simultaneous fashion i.e. in parallel Block Concurrent signal assignment Component instantiation Concurrent procedure call Concurrent assertion Generate
Lecture 2
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Introduction to VHDL

Authored by Dr. Tri Caohuu& Vivek Verma

VHDL Primary Constructs

Design Unit : Entity

Design Unit : Architecture

Design Unit : Architecture

Design Unit : Configuration

Design Unit : Configuration

Design Unit : Package Declaration

Design Unit : Package Body

Package body: conti.

VHDL Modeling Styles

VHDL Modeling Styles : Structural

VHDL Modeling Styles : Behavioral

VHDL Modeling Styles : Dataflow

VHDL Modeling Styles : Mixed

VHDL Statements : Sequential

VHDL Statements : Concurrent

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