VHDL DESIGN AND FPGA IMPLEMENTATION OF A FULLY PARALELL ARCHITECTURE FOR ITERATIVE DECODER OF MAJORITY LOGIC CODES FOR

HIGH DATA RATE APPLICATIONS

Chapter I

INTRODUCTION 1.1 Scope and Introduction

The radio frequency spectrum is filled with noise and other signals, especially those frequencies where unlicensed transmitter operation under FCC part 15 rules is allowed. When using a wireless remote control system it is desirable to have a way of filtering out or ignoring those unwanted signals to prevent false data from being received. A simple way to accomplish this is to use an encoder IC at the transmitter and a decoder IC at the receiver. The encoder generates serial codes that are automatically sent three times and must be received at least twice before data is accepted as valid by the decoder circuit. In the early days of radio control", before these coding

ICs were available, radio controlled garage doors sometimes opened themselves when they received transmissions from a plane passing overhead or a two-way radio operating in the area. Encoding and decoding is now used in most wireless control systems to prevent this type of interference. The complexity and the latency, which are often higher during the decoding process, make up the major decoding drawbacks in the current digital systems. The decoding data rate depends of the parallelism of the chosen architecture, i.e., its ability to process simultaneously multiple data. The architecture presents a high level of parallelism more it is able to achieve a very high data rate. In electronic design, the complexity of the circuit (i.e., its surface) is often considered as a critical parameter. In this context of very high data rate, operating speed must be maximized with limitation of complexity induced by the parallelism of calculations. We will specially study the decoding of the codes belonging to the OSMLD (one step majority logic decoding) codes family and used in an iterative decoding process. The majority logic decoding uses a linear combination of a reduced set of syndromes represented by orthogonal equations. Hence it allows, by choosing a pipeline and / or parallelized architecture, to have a less complex decoding circuit with a high data rate.

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Chapter II

LITERATURE SURVEY
2.1 VHDL Design and FPGA Implementation of Weighted Majority Logic Decoders
In this work, us propose a design and FPGA (Field Programmable Gate Arrays) implementation of two parallel architectures for majority logic decoder of low complexity for high data rate applications are proposed. These architectures are hard decision architecture (Hard in - Hard out (HIHO)) and the SIHO threshold decoding. The code used is the Difference Set Cyclic code (DSC (21, 11)). The VHDL (Very high speed integrated circuit Hardware Description Language) design and the synthesis of such architecture shows such decoders can achieve high data rate with low complexity

Fig 2.1: Parallel implementation of the proposed architecture LD for DSC (21, 11) code

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The complexity and the latency, which are often higher during the decoding process, make up the major decoding drawbacks in the current digital systems. The decoding data rate depends on the parallelism of the chosen architecture, i.e., its ability to process simultaneously multiple data. The architecture presents a high level of parallelism more it is able to achieve a very high data rate. In electronic design, the complexity of the circuit (i.e., its surface) is often considered as a critical parameter. In this context of very high data rate, operating speed must be maximized with limitation of complexity induced by the parallelism of calculations. After reminding the principle of majority logic decoding, this paper will present the proposed the work with a hard decision and architecture of Massey's APP (A Posterior Probability) algorithm. Both architectures use the joint exploitation of parallelism of symbols and sub-blocks to achieve high data rate. The algorithmic structure of the threshold decoding is summarized as follows: For each j = n,,1 Calculate the terms Bi and Wi, i in {1,..,J} Calculate Bo et Wo Calculate the extrinsic information W (yj) The output decoder is obtained by LLR(yj )=4 ES Decision { yj +W(yj)

Summary: VHDL design and FPGA (Field Programmable Gate Arrays) implementation of two parallel architectures for majority logic decoder is proposed. The architectures are hard decision architecture and the SIHO threshold decoding. Aim is to obtain low complexity for high data rate applications. The code used is the Difference Set Cyclic code. In electronic design, the complexity of the circuit is a critical parameter and operating speed must be maximized with limitation of complexity induced by the parallelism of calculations. The architecture of the threshold decoding has three fundamental units.

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The shift register contains the quantified symbols received in parallel, the loading of the register is controlled by input on the first rising front of the clock. In the implementation of the add-min operator and the adder, the number of input ports must be configurable as well as the number of bits per port to avoid poor performance of the correction errors.

The results of the add-min operation, the addition and the decision are available at the output at each rising edge of the clock. The approach of the VHDL design and FPGA implementation of the decoder proposed allow to achieve very high data rate with reducing complexity. A combinatorial architecture working in pipelined and parallelized mode has been adopted. The hard decision decoder responds on the first rising edge of the clock with a complexity of 173 LEs, for threshold decoding requiring 22 clock cycles so as that the code word is decoded with a complexity of 259 LEs.

The decoder can be used on a turbo process in order to achieve a high data rate turbo decoder with a reasonable complexity.

Fig 2.2: Parallel implantation of proposed architecture of the threshold decoding of MLC code

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2.2 An FPGA Implementation of Array LDPC Decoder

Low-Density Parity-Check (LDPC) code is one kind of prominent error correcting codes (ECC) being considered in next generation industry standards. This paper presents an FPGA implementation of array code based Low-Density Parity- Check code decoder. The advantages of the proposed architecture as compared to the fully parallel or partially parallel architecture are: less memory requirement, avoidance of complex global interconnects and its satisfying throughput. These advantages are derived from exploiting the well-defined structure of the parity check matrix of array code based LDPC codes. Iterative decoding algorithms, also known as the message-passing algorithms are used for decoding LDPC codes. LDPC codes, due to their near-Shannon limit performance under iterative soft decoding have received significant attention. LDPC codes have been recently selected by the digital video broadcasting standard and are being seriously considered in various real-life applications such as magnetic storage, 10 GB Ethernet, and high-throughput wireless local area network. In the past few years, significant improvement in LDPC code construction and performance analysis has been experienced. In addition, several efforts are given to the implementation of LDPC code decoder. In general, the complex routing, large message memory requirement and limited throughput are the main obstacles in designing an LDPC decoder. This paper presents an efficient FGPA implementation for array based LDPC (ALDPC) codes, which can achieve a good trade-off between hardware complexity and decoding speed. Typically, over 70% memory can be reduced and 117Mbps throughput can be achieved. LDPC codes can typically be defined by an MxN parity check matrix H. The symbol N, represents the length of the block (i.e. the number of bits in the codeword), while the symbol M, represents the number of parity checks in the code. The rate of such a code is thus at least (N-M)/N. The LDPC code can be represented by a bipartite graph (Tanner graph) of variable nodes and check nodes as shown in Fig.

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Fig 2.3. Tanner graph for a regular (2, 3) LDPC code

The decoder mainly consists of CPUs and VPUs. 47 (p) VPUs and 188 (M) CPUs are instantiated in the decoder. The CPUs are separated into four groups. CPU have four groups Each group has 47 members (CPU). Group 1 contains from CPU-1 to CPU-47, in charge of the row operation of row 1~47. Group 2 contains from CPU-48 to CPU-94, in charge of the row operation of row 48~94. Group 3 contains from CPU-95 to CPU-141, in charge of the row operation of row 95~ 141. Group 4 contains from CPU-142 to CPU-188, in charge of the row operation of row 142~188. There is no communication between groups. Except the CPUs in Group 1 (CPU-1iCPU-47), every 47 CPUs in a group form a chain, and each CPU communicates with its two neighbors.

Channel Information

CPU GROUP 1

CPU GROUP 2 CONTROL VPU UNIT CPU GROUP 3

Decoder bits

CPU GROUP 4

Fig 2.4: Architecture of the decoder

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Summary: Low Density Parity Check (LDPC) code is an error correcting code. FPGA implementation for array based LDPC codes helps achieve a trade-off between hardware complexity and decoding speed. Over 70% memory can be reduced and 117Mbps throughput can be achieved. Calculations are independent between variable nodes or check nodes at each iteration. LDPC codes are suitable for parallel implementation. Low logic consumption

2.3 Design and FPGA Implementation of Stochastic Turbo Decoder

Turbo codes are a recent development in the field of forward-error-correction channel coding. The codes make use of three simple ideas: parallel concatenation of codes to allow simpler decoding; interleaving to provide better weight distribution; and soft decoding to enhance decoder decisions and maximize the gain from decoder interaction. Turbo codes immediately achieved performance results in the near range of the theoretically best values, giving a less than 1.2-fold overhead.

Fig 2.5: The generic turbo encoder

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Stochastic decoding that is inspired by stochastic computation is an alternative technique for decoding of error-correcting codes. The extension of this approach to decode convolutional codes and turbo codes is discussed in this article. The switching activity sensitivity is circumvented and the latching problem is reduced by transforming the stochastic additions into stochastic multiplications in the exponential domain and using multiple streams with deterministic shufflers. The number of decoding cycles is thus considerably reduced with no performance degradation. Stochastic decoding, previously applied to the decoding of LDPC codes, can now be applied to decoding of turbo codes. In addition, the first hardware architecture for stochastic decoding of turbo codes is presented. The proposed architecture makes fully-parallel turbo decoding viable on FPGA devices. Results demonstrate the potential of stochastic decoding to implement fully-parallel turbo decoders. Principles of stochastic computation were elaborated in the 1960s by Gaines and Poppelbaum et al. As a method to carry out complex operations with a low hardware complexity. The main feature of this method is that the probabilities are converted into streams of stochastic bits using Bernoulli sequences in which the information is given by the statistics of the bit streams. Complex arithmetic operations on probabilities such as multiplication and division are transformed into operations on bits using elementary logic gates. Stochastic decoding of Forward Error Correction (FEC) is inspired by these principles. The two main appealing features of this approach for iterative decoding are very simple hardware structures of computing nodes and high-throughput decoding. Early stochastic methods were only successful for decoding special short/acyclic Hamming or LDPC codes . These methods result in poor decoding performance when used to decode practical codes on factor graphs (with cycles). An improved stochastic decoding approach was then proposed to decode practical LDPC codes. When compared with conventional Sum-Product implementations, stochastic decoding could provide near-optimal performance for practical LDPC codes. The potential of this method for low- complexity decoding was validated by an FPGA implementation of a (1024, 512) LDPC decoder. This first implementation provides a throughput of 706 Mbps at a Bit Error Rate (BER) of 106 with performance loss of about 0.1 dB, compared to the floating-point BP, while occupying only 36% of a Virtex-4 LX200 FPGA device . High data rates and architecture efficiencies were achieved thanks to many recent improvements. In addition, this approach was extended to well-known linear block codes with high-density parity-check matrices, namely BCH codes, Reed Solomon codes and
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product codes. Moreover, stochastic decoding is also of high interest for low power decoders and fault-tolerant Nano scale circuits. Turbo codes are a family of FECs that are especially attractive for mobile communication systems and have been adopted as part of several channel coding standards for high data rates such as UMTS and CDMA2000 (thirdgeneration) or 3GPP-LTE (the last step toward the fourth generation). A major challenge in the implementation of turbo decoders is high-throughput decoding. Indeed, the next generations of mobile communication systems will require data rates of 1 Gb/s and beyond. Designers try to exploit the maximum feasible amount of parallelism in turbo decoders for the sake of higher throughput. However, due to the lack of parallelism in the MAP-based decoding algorithm, the implementation of fully-parallel turbo decoders is still challenging for practical turbo codes. Another form of stochastic algorithm was proposed in and used for trellis decoding algorithm of an acyclic (16, 11) Hamming code and a (256,121) product Turbo code based on 32 component decoders of this Hamming code. An improved stochastic decoding approach was recently introduced to decode convolutional codes and turbo codes. The results provided in this paper validate the potential of stochastic decoding as a practical approach for highthroughput turbo decoders and encourage to keep on investigating in this way. One major problem in stochastic decoding which deeply degrades the performance is related to the sensitivity to the level of random switching activity. Different solutions such as Edge Memories (EMs) have been suggested to solve this latching problem. An original idea is introduced to reduce the number of clock cycles required to decode one code word and to replace the EMs by simple deterministic shufflers. The proposed architecture, that uses multiple streams in parallel to represent the same probability, presents the best architecture efficiency defined as the ratio between data throughput and hardware complexity. Summary: Stochastic decoding is an alternative technique for decoding of error-correcting codes. The switching activity sensitivity is circumvented and the latching problem is reduced by transforming the stochastic additions into stochastic multiplications in the exponential domain and using multiple streams with deterministic shufflers. The probabilities are converted into streams of stochastic bits using Bernoulli sequences in which the information is given by the statistics of the bit streams.

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The two main features of this approach for iterative decoding are very simple hardware structures of computing nodes and high-throughput decoding. Turbo codes are a family of FECs that are especially attractive for mobile communication systems. Exploitation of the maximum feasible amount of parallelism in turbo decoders is preferred for the sake of higher throughput.

One major problem in stochastic decoding which deeply degrades the performance is related to the sensitivity to the level of random switching activity. The proposed architecture uses multiple streams in parallel. The number of decoding cycles is considerably reduced with no performance degradation by transforming the stochastic additions into stochastic multiplications in the exponential domain and using multiple streams with deterministic shufflers.

The proposed architecture makes fully-parallel turbo decoding viable on FPGA devices.

2.4 VHDL Design and FPGA Implementation of a fully parallel BCH SISO Decoder
In this work, a design and (FPGA) implementation of architecture of an entirely parallel SISO decoder for turbo decoding of the product codes with low complexity for high data rate applications. As an example we study a soft input/output decision decoding for the BCH (31, 26, 3) code. The VHDL design and synthesis of such architecture showed that the use of the structure combining the sub-blocks parallelism with the symbols parallelism for the establishment of such decoder can achieve a data rate of 75.5 Gb/s with low complexity, about 2199 CLBs. The turbo codes in blocks (TCB) are an alternative to convolutional turbo codes introduced in 1993 by C. Berrou, (TCBs) have been proposed by R. Pyndiah in 1994, the decoding uses weighted (Soft) input/output SISO algorithm. The current digital systems, the channel coding especially decoding, require high data rate rates. The decoder data rate depends on the parallelism of the chosen architecture, i.e. its ability to process multiple data simultaneously. More the architecture provides a high level of parallelism, more it is able to achieve very high speed. In electronic design, the complexity of the circuit (i.e, its surface) is often considered as a critical parameter. In this context of very high speed operating speed must be maximized, with limitation of complexity induced by the parallelism of calculations.

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After recalling the principle of decoding produced codes by Chase-Pyndiahs algorithm. This paper presents the VHDL design and FPGA implementation of SISO decoder architecture with joint exploitation of parallelism symbol and parallelism of sub blocks to achieve high data rate. This establishment leads to architectures without interleaving memory or interconnection networks. The VHDL implementation will be treated and simulated using

the Quartus II software capable of operating on circuits running around 1GHZ. In BCH (31, 26) decoder design, the product codes are obtained by concatenation of linear block codes. Consider two codes C1 and C2 characterized by the parameters (n1, k1, d1) and (n2, k2, d2), the parameters of the product code C1X C2 are (n, k, d) such as: n=n1 X n2 k=k1 X k2 d=d1 X d2 Each codeword of the product code is in the form of matrix with n1 lines and n2 columns. For this study, we choose codes: C1 = C2 = BCH (31, 26, 3). The binary information symbols are represented by a matrix M in k1 lines and k2 columns, Each of the k1 rows of the matrix M is encoded by the code C2 to get a matrix M. Each of the n2 columns of the matrix M is encode by the code C1.

n2
K2

M matrix information of binary K1 Symbols

Redundancy on the lines

n1

Redundancy on the columns

Redundancy on redundancy

Fig 2.6: Principle encoding of product code.

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The decoder works in soft decision way. The entry consists of analog samples (called symbols) encoded on q=5 bits: 4 bits for reliability and 1 for sign. The sign bit represents the binary value of the symbol ('0 'or '1'), the absolute value of a received bit represent its reliability (high reliability means that this bit has more chance to be correct). The implemented decoder uses the Chase-Pyndiah algorithm. The Chase-Pyndiah algorithm consists of three parts: The first section of the algorithm is extracting some useful parameter from the received word (reception part). Access to data is performed in parallel; the implementation of this part is done in parallel, this presupposes that the last part of the algorithm (transmission part) is also implemented in parallel. The intermediate part, named processing part occurs at the level of test vectors. This part can be implemented according to different degrees of parallelism. The proposed architecture introduces the combinatorial approach to the implementation of each basic block (part). To implement this elementary decoder, we have to translated the steps of decoding (for the half iteration) in simple blocks. The sub-block of the receiving part works in parallel on the input symbols simultaneously. These operations are the computation of the syndrome and the sorting to get the least reliable components. We obtain all data on the first rising edge of the clock. One period allows to process all test vectors: calculating syndrome, decoding and computing metric for each hard decision related to test vector. Thereafter, since the decided vector and its competitor (s) are known, computing reliability can be done in one clock period, according to this the chosen architecture requires only 2-clock-cycle latency.

Summary: A design and (FPGA) implementation of architecture of a fully parallel SISO decoder for turbo decoding of the product codes with low complexity for high data rate applications is proposed. In this, joint exploitation of parallelism symbol and parallelism of sub blocks are done to achieve high data rate. Chase-Pyndiah algorithm is used in the proposed system. The decoder can reach some data rate superior to the Gbit/s with a reasonable complexity by limiting the degradation The sub-block of the receiving part works in parallel on the input symbols simultaneously.
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These operations are the computation of the syndrome and the sorting to get the least reliable components. All data on the first rising edge of the clock is obtained. One period allows to process all test vectors: calculating syndrome, decoding and computing metric for each hard decision related to test vector. The chosen architecture requires only 2-clock-cycle latency.

2.5 A New Iterative Threshold Decoding Algorithm for One Step Majority Logic Decodable Block Codes
The performance of iterative decoding algorithm for one-step majority logic decodable (OSMLD) codes is investigated. A new soft-in soft-out of APP threshold algorithm which is able to decode theses codes nearly as well as belief propagation (BP) algorithm. However the computation time of the proposed algorithm is very low. The developed algorithm can also be applied to product codes and parallel concatenated codes based on block codes. Numerical results on both AWGN and Rayleigh channels are provided. The performance of iterative decoding of parallel concatenated code (17633,8595) with rate 0.5 is only 1.8 dB away from the Shannon capacity limit at a BER of 10-5. TURBO codes or LDPC codes are currently the most effective solution for Forward Error-Correction (FEC) in applications requiring either high code rates (R > 0.8), very low error floors, or low-complexity decoders able to operate at several hundreds of megabits per second and even higher. Practical implications of theses codes are numerous namely 3G wireless phones, Digital Video Broadcasting (DVB) systems, or Wireless Metropolitan Area Networks (WMAN). Turbo decoding relies on the exchange of probabilistic messages (the so-called extrinsic information) between two soft-input soft-output (SISO) decoders for the component convolutional codes. However, for concatenated schemes with block component codes, the computational complexity of trellis-based SISO decoding algorithms is often high. This has led to look for new SISO decoding algorithms with low complexity and high performance. These algorithms calculate extrinsic information using classical decoders such as Chase algorithm, ordered statistics decoding algorithm and Hartmann/Rudolph algorithm. In this perspective we present a new iterative decoding algorithm based on a SISO extension form of threshold algorithm.

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The proposed algorithm is attractive for three reasons: (1) It can be simply implemented; (2) the decoding delay is short; (3) and it has good performances. The use of the threshold algorithm in iterative decoding was introduced for the first time by Sviridbut for convolutional codes. Our iterative decoding process follows that given by Pyndiah. However, instead of using an extension of Chase algorithm on BCH codes, we will apply an extension of Massey algorithm on one step majority logic decodable (OSMLD) codes. On the other hand Lucas et al. introduce an iterative decoding algorithm for several families of codes (e.g. OSMLD codes) but they use an approximation of Hartmann/Rudolph algorithm. This paper is focused on iterative decoding of OSMLD codes. The algorithmic structure of the SISO threshold decoding can be summarized as follows: For each j 1,.., n Compute the terms Bi and Wi , i 1,..,J Calculate Bo and Wo Compute the extrinsic information E j The Soft-output is obtained by: LLRj = Lcrj+E On the Rayleigh fading channel, the availability of channel side information is the key issue in determining the necessary modification for the iterative threshold decoding algorithm. The threshold decoding algorithm has to be modified slightly by changing equation given below, which define the reliability value of the channel. Lc= 4Es/No has to be modified Lc= 4Es/No aj. Where aj= The Rayleigh variable.

Summary: The performance of iterative decoding algorithm for one-step majority logic decodable (OSMLD) codes is investigated. The developed algorithm can also be applied to product codes and parallel concatenated .codes based on block codes. The proposed algorithm is attractive for three reasons: (1) It can be simply implemented; (2) the decoding delay is short; and (3) it has good performances. On the Rayleigh fading channel, the availability of channel side information is the key issue in determining the necessary modification for the iterative threshold decoding algorithm
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A new iterative threshold decoding algorithm for simple codes, product codes and parallel concatenated block codes based on one-step majority logic decodable code. We use an extension of Masseys algorithm as a Soft input/ Soft-output component decoder. The structure of our iterative decoder follows the model of Pyndiah with some modifications.

This algorithm has been tested on several codes based on OSMLD codes and good performances have been obtained over the Gaussian and Rayleigh fading channels. It is interesting to extend this iterative decoding algorithm on quasi- cyclic and multistep majority logic decodable codes.

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CHAPTER III

WORKTO BE DONE
3.1 Introduction
Over the years of experimentation and research in regards to FPGA implementation of weighted majority decoders; The significance of the combinational architecture working in pipeline and parallelized mode has resulted in very high data rate and reduced complexity. Since complexity and high data rate are critical parameters in electronic design, even the above proposed method was an ideal one. Therefore our project comprises of a SISO architecture model in addition to the other two architecture models. So that the working model can be much more efficient in regards to speed optimization and complexity.

3.2 Proposed work 3.2.1 Design of SISO threshold decoding

The basic idea is to modify the conventional threshold algorithm by associating a reliability to each decision exploited in iterative decoding
Y_rec SISO threshold decoder Fig 3.1: Implementation of SOFT output decoder Extrinsic information Decision function

3.2.2 Implementation of the parallel SISO threshold decoder of DSC code

Several studies on the "SISO decoders" have already been carried out. In this paper the VHDL description of the SISO threshold decoding is made so that each unit of the proposed architecture is described in an independent entity. The final architecture of the parallel SISO threshold decoding is given in figure 3.2. The proposed architecture has been described in VHDL and embedded on FPGA using the Alteras Quartus II tool. The FPGA circuit used is similar to the one used toold decoder, the operations are obtained on the first rising edge of the clock and the occupied area for this decoder is 3672 LEs (logic elements) with 190 inputs/outputs for the DSC (21, 11) code.

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Fig 3.2 : Parallel Implementation of proposed architecture of the SISO

3.2.3 Iterative Threshold Decoding

A. Iterative threshold decoding The iterative decoding of codes OSMLD was introduced for the first time by Lucas. Two years after, the latter with Fossorier et al. have proposed the belief propagation algorithm for decoding of OSMLD codes, They showed that the iterative Hartmann-Rudolf-Lucas decoding, originally used for the decoding of product codes can be used to decode the codes OSMLD. In the process of iterative decoding, each decoder takes advantage of the extrinsic information produced by the other decoder in the previous step. How extrinsic information is transmitted and the way it is exploited by decoders to make their decision are not yet closed. The iterative decoding process that we use follows the Pyndiahs scheme.

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Fig 3.4: Component decoder

B. Implementation of parallel iterative threshold decoding The final design of the parallel iterative decoder is de- scribed in VHDL and embedded on FPGA using the Alteras Quartus II tool. For the complexity of the global entity, the area occupied by the fully parallel iterative show in table 3.1 for the two codes DSC (21, 11) and DSC (73, 45) with 4 and 5 bits quantification. We were able to simulate and verify the decoding of 2000 words used for each SNR following a simulation pro-tocol shows the performances of our iterative decoder using the quantified data of 5 bits and (q) fixed for the DSC(21, 11) (resp. DSC(73, 45)) code.

Table 3.1

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Summary: The complexity and the latency are often higher during the decoding process, creating major decoding drawbacks in the current digital systems. In electronic design, the complexity of the circuit is often considered as a critical parameter. Operating speed must be maximized with limitation of complexity induced by the parallelism of calculations for high data rate. The architecture presents a high level of parallelism more than it is able to achieve a very high data rate. The architectures described can be used in digital systems for high data rate and reduced complexity. Can be incorporated with digital systems to increase efficiency of data decoding.

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REFERENCE
[1] Hagenauer, E. Offer, and L. Papke, "iterative decoding of binary block and convolutional codes", IEEE Trans. Inform. Theory, Mar. 1996, Vol. 42, pp. 429-446 [2] R. Lucas, M. Bossert and M. Breitbach, "On Iterative Soft-Decision Decoding of Linear Binary Block Codes and Product Codes", IEEE Journal on selected areas in commu- nications, February 1998, Vol. 16, N 2, pp. 276-296. [3] R. Pyndiah, Near optimum decoding of product codes: Block Turbo Codes", IEEE Trans. on Comm., vol 46, n8, August 1998, pp. 1003-1010. [4] R. Lucas, M. P. C. Fossorier, Yu Kou, and Shu Lin, "Iterative Decoding of One-Step Majority Logic Decodable Codes Based on Belief Propagation", IEEE Trans. Commun, Vol. 48, No. 6, pp.931-937, June 2000. [5] M. Belkasmi, M. Lahmer, F. Ayoub Iterative Threshold Decoding of Product Codes Constructed From Majority Logic Decodable Codes , 2nd International Conf. on Information and Communication Technologies : From Theory to Applications, IEEE ICTTA06, Apr. 2006, Damascus, Syria, pp. 2376 2381.

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