SCHEME OF TEACHING AND EXAMINATION M.TECH.

- DIGITAL ELECTRONICS II SEMESTER Teaching hours/week Course Code Subject Code Name of the Subject Lecture Modern DSP Advanced Embedded Systems Advances in VLSI Design Synthesis & Optimization of Digital Circuits Elective-II (10LDE25x) Mini Project & Seminar 4 4 4 4 4 Practical 2 2 3 Tutorial 2 2 2 Duration of Exam in Hours 3 3 3 3 3 Marks for I.A. 50* 50
*

Exam 100 100 100 100 100 -

Total Marks

10LDE21 10LDE22 10LDE23 10LDE24 10LDE25 10LDE26

10EC123 10EC118 10EC009 10EC077 10EC25x 10EC921

150 150 150 150 150 50

50# 50# 50# 50$

Project Phase I (6 week Duration) should start between II Semester and III Semester, after availing a vacation of 2 weeks. This will be evaluated during III semester.
Total
* #

20

07

06

15

300

500

800

Practical will be evaluated 25 marks and internal assesment for 25 marks. Lab journals should be maintained. Assignments/seminar will be evaluated for 25 marks and internal assesment for 25 marks. Record of Assignments/seminar should be maintained. $ Mini projet should be done individually and is assessed for 25 marks. Seminar on Miniproject will be assessed for 25 marks.
ELECTIVE II 10LDE251 10EC030 10LDE252 10EC128

Digital Signal Compression Simulation Modeling and Analysis

10LDE253

10EC010

Algorithms for VLSI Design Automation

SECOND SEMESTER MODERN DSP Subject Code No. of Lecture Hours /week Total no. of Lecture Hours : 10EC123 : 04 : 52 IA Marks Exam Hours Exam Marks : 50 : 03 : 100

Goal of the course Advances in Digital Signal Processing involve variable sampling rates and thus the multirate signal processing and hence their applications in communication systems and signal processing. It is intended to introduce a basic course in multirate signal processing especially meant for students of branches eligible for M Tech courses in EC related disciplines. Review of Signals and Systems Discrete time processing of continuous signals - Structure of a digital filter; Frequency domain analysis of a digital filter; Quantization error; Sigma and Sigma Delta Modulation. Fourier Analysis DFT, DTFT, DFT as an estimate of the DTFT for Spectral estimation. DFT for convolution, DFT/DCT for compression, FFT. Ideal Vs non ideal filters, FIR and IIR Filters Digital Filter Implementation; Elementary Operations. Digital Filters , State Space realization, Robust implementation of Digital Filters, Robust implementation of equi ripple FIR digital filters Multirate Systems and Signal Processing. Fundamentals Problems and definitions; Upsampling and downsampling; Sampling rate conversion by a rational factor; Multistage implementation of digital filters; Efficient implementation of multirate systems.

DFT filter banks and Transmultiplexers DFT filter banks, Maximally Decimated DFT filter banks and Transmultiplexers. Application of transmultiplexers in communications Modulation. Maximally Decimated Filter banks Vector spaces, Two Channel Perfect Reconstruction conditions; Design of PR filters Lattice Implementations of Orthonormal Filter Banks, Applications of Maximally Decimated filter banks to an audio signal. Introduction to Time Frequency Expansion; The STFT; The Gabor Transform, The Wavelet Transform; The Wavelet transform; Recursive Multiresolution Decomposition. References: 1. Roberto Cristi, Modern Digital Signal Processing, Cengage Publishers, India, (erstwhile Thompson Publications), 2003. 2. S.K. Mitra, Digital Signal Processing: A Computer Based Approach, III Ed, Tata McGraw Hill, India, 2007. 3. E.C. Ifeachor and B W Jarvis, Digital Signal Processing, a practitioners approach, II Edition, Pearson Education, India, 2002 Reprint. 4. Proakis and Manolakis, Digital Signal Processing, Prentice Hall 1996 (third edition).

Laboratory Experiments: I. Modern Digital Signal Processing i. USING MATLAB 1 Question based on response of LTI systems to different inputs A LTI system is defined by the difference equation y[n]=x[n]+x[n-1]+x[n-2]. (a) Determine the impulse response of the system and sketch it. (b) Determine the output y[n] of the system when the input is x[n]=u[n]. (c) Determine the output of the system when the input is a complex exponential (Eg. x[n]=2e j0.2n). 2 Question on design of simple digital filter using the relationship between pole and zeros and the frequency response of the system Design a simple digital FIR filter with real co-efficients to remove a narrowband (i.e., sinusoidal) disturbance with frequency F 0=50 Hz. Let Fs=300 Hz be the sampling frequency. (a) Determine the desired zeros and poles of the filter. (b) Determine the filter coefficients with the gain K=1 (c) Sketch the magnitude of the frequency response. 3 Question on simple digital filtering using the relationship between pole and zeros and the frequency response of the system Design an IIR filter with real co-efficients with same specifications mentioned in Q2 and repeat the steps (a) to (c). 4 Question to understand the effect of time domain windowing Generate a signal with two frequencies x(t)=3cos(2F1t) + 2cos(2F2t) sampled at Fs=8 kHz. Let F1=1 kHz and F2=F1+ and the overall data length be N=256 points. (a) From theory, determine the minimum value of necessary to distinguish between the two frequencies. (b) Verify this result experimentally. Using the rectangular window, look at the DFT with several values of so that you verify the resolution. (c) Repeat part (b) using a Hamming window. How did the resolution change? 5 Comparison of DFT and DCT (in terms of energy compactness) Generate the sequence x[n]=n-64 for n=0,127. (a) Let X[k]=DFT{x[n]}. For various values of L, set to zero the high frequency coefficients X[64L]=.X[64]=.=X[64+L]=0 and take the inverse DFT. Plot the results.

(b) Let XDCT[k]=DCT(x[n]}. For the same values of L, set to zero the high frequency coefficients XDCT[127-L]=.XDCT[127]. Take the inverse DCT for each case and compare the reconstruction with the previous case. 6 Filter design Design a discrete time low pass filter with the specifications given below: Sampling frequency = 2 kHz. Pass band edge = 260 Hz Stop band edge = 340 Hz Max. pass band attenuation = 0.1 dB Minimum stop band attenuation = 30 dB Use the following design methodologies: Hamming windowing Kaiser windowing Applying bilinear transformation to a suitable, analog Butterworth filter. Compare the obtained filters in terms of performance (accuracy in meeting specifications) and computational complexity.

ii. Using DSP PROCESSOR 1 Write an ALP to obtain the response of a system using linear convolution whose input and impulse response are specified. 2. Write an ALP to obtain the impulse response of the given system, given the difference equation. . 1.Sampling of an Image. 2.Design of equiripple filters. 3.Application of frequency transformation in filter design. 4.Computation of FFT when N is not a power of 2. 5.Sampling rate conversion and plot of spectrum. 6.Analysis of signals by STFT and WT. 7.Delayed auditory feedback signal using 6713 processor. 8.Record of machinery noise like fan or blower or diesel generator and obtaining its spectrum. 11. Synthesis of select dual tone multi frequency signals using 6713 processor. 12. Fourier Transform & its inverse Fourier Transform of an image. Any other experiments can be added to supplement the theory.

ADVANCED EMBEDDED SYSTEMS Subject Code No. of Lecture Hours /week Total no. of Lecture Hours : 10EC118 : 04 : 52 IA Marks Exam Hours Exam Marks : 50 : 03 : 100

Typical Embedded System : Core of the Embedded System, Memory, Sensors and Actuators, Communication Interface, Embedded Firmware, Other System Components Characteristics and Quality Attributes of Embedded Systems Hardware Software Co-Design and Program Modelling: Fundamental Issues in Hardware Software CoDesign, Computational Models in Embedded Design, Introduction to Unified Modelling Language, Hardware Software Trade-offs Embedded Firmware Design and Development: Embedded Firmware Design Approaches, Embedded Firmware Development Languages Real-Time Operating System (RTOS) based Embedded System Design.

Operating System Basics, Types of OS, Tasks, Process and Threads, Multiprocessing and Multitasking, Task Scheduling, Threads, Processes and Scheduling: Putting them altogether, Task Communication, Task Synchronization, Device Drivers, How to Choose an RTOS The Embedded System Development Environment: The Integrated Development Environment (IDE), Types of Files Generated on Cross-compilation, Disassembler/Decompiler, Simulators, Emulators and Debugging, Target Hardware Debugging, Boundary Scan. Trends in the Embedded Industry : Processor Trends in Embedded System, Embedded OS Trends, Development Language Trends, Open Standards, Frameworks and Alliances, Bottlenecks. Reference Books: 1. Introduction to Embedded Systems, Shibu K V, Tata McGraw Hill Education Private Limited, 2009 2. Embedded Systems A contemporary Design Tool, James K Peckol, John Weily, 2008. -----------------------------------------------Advanced Embedded System Lab: Lab Experiments :I.Use the EDA (Electronic Design Automation) tools to learn the Embedded Hardware Design and for PCB design. II.Familiarize the different entities for the circuit diagram design. III.Familiarize with the layout design tool, building blocks, component placement, routings, design rule checking etc. Embedded Programming Concepts (RTOS): 1.Create n number of child threads. Each thread prints the message Im in thread number and sleeps for 50 ms and then quits. The main thread waits for complete execution of all the child threads and then quits. Compile and execute in Linux. 2.Implement the multithread application satisfying the following : i.Two child threads are crated with normal priority. ii.Thread 1 receives and prints its priority and sleeps for 50ms and then quits. iii.Thread 2 prints the priority of the thread 1 and rises its priority to above normal and retrieves the new priority of thread 1, prints it and then quits. iv.The main thread waits for the child thread to complete its job and quits. 3.Implement the usage of anonymous pipe with 512 bytes for data sharing between parent and child processes using handle inheritance mechanism. 4.Test the program below using multithread applicationi.The main thread creates a child thread with default stack size and name Child_Thread. ii.The main thread sends user defined messages and the message WM_QUIT randomly to the child thread. iii.The child thread processes the message posted by the main thread and quits when it receives the WM_QUIT messge. iv.The main thread checks the termination of the child thread and quits when the child thread complete its execution. v.The main thread continues sending the random messages to the child thread till the WM_QUIT message is sent to child thread. vi.The messaging mechanism between the main thread and child thread is synchronous. 5.Test the program application for creating an anonymous pipe with 512 bytes of size and pass the Read Handle of the pipe to a second process using memory mapped object. The first process writes a message Hi from Pipe Server. The 2nd process reads the data written by the pipe server to the pipe and displays it on the console. Use event object for indicating the availability of data on the pipe and mutex objects for synchronizing the access in the pipe. 6.Create a POSIX based message queue for communicating between two tasks as per the requirements given below:i.Use a named message queue with name MyQueue. ii.Create two tasks(Task1 & Task2) with stack size 4000 & priorities 99 & 100 respectively.

iii.Task 1 creates the specified message queue as Read Write and reads the message present, if any, from the message queue and prints it on the console. iv.Task2 open the message queue and posts the message Hi from Task2. v.Handle all possible error scenarios appropriately. Any other experiments can be included to support the theory.

ADVANCES IN VLSI DESIGN Subject Code No. of Lecture Hours/Week Total No. of Lecture Hours : 10EC009 : 04 : 52 IA Marks Exam Hrs Exam Marks : 50 : 03 : 100

Review of MOS Circuits: MOS and CMOS static plots, switches, comparison between CMOS and BI - CMOS. MESFETS: MESFET and MODFET operations, quantitative description of MESFETS. MIS Structures and MOSFETS: MIS systems in equilibrium, under bias, small signal operation of MESFETS and MOSFETS. Short channel effects and challenges to CMOS: Short channel effects, scaling theory, processing challenges to further CMOS miniaturization Beyond CMOS: Evolutionary advances beyond CMOS, carbon Nano tubes, conventional vs. tactile computing, computing, molecular and biological computing Mole electronics-molecular Diode and diode- diode logic .Defect tolerant computing, Super buffers, Bi-CMOS and Steering Logic: Introduction, RC delay lines, super buffers- An NMOS super buffer, tri state super buffer and pad drivers, CMOS super buffers, Dynamic ratio less inverters, large capacitive loads, pass logic, designing of transistor logic, General functional blocks - NMOS and CMOS functional blocks. Special Circuit Layouts and Technology Mapping: Introduction, Talley circuits, NAND-NAND, NORNOR, and AOI Logic, NMOS, CMOS Multiplexers, Barrel shifter, Wire routing and module lay out. System Design: CMOS design methods, structured design methods, Strategies encompassing hierarchy, regularity, modularity & locality, CMOS Chip design Options, programmable logic, Programmable inter connect, programmable structure, Gate arrays standard cell approach, Full custom Design. REFERENCE BOOKS: 1.Kevin F Brrnnan Introduction To Semi Conductor Device, Cambridge publications 2.Eugene D Fabricius Introduction to VLSI Design, McGraw-Hill International publications 3.D.A Pucknell Basic VLSI Design, PHI Publication 4.Wayne Wolf, Modern VLSI Design Pearson Education, Second Edition , 2002

SYNTHESIS AND OPTIMIZATION OF DIGITAL CIRCUITS Subject Code No. of Lecture Hours/Week Total No. of Lecture Hours : 10EC077 : 04 : 52 IA Marks Exam Hrs Exam Marks : 50 : 03 : 100

Introduction: Microelectronics, semiconductor technologies and circuit taxonomy, Microelectronic design styles, computer aided synthesis and optimization. Graphs: Notation, undirected graphs, directed graphs, combinatorial optimization, Algorithms, tractable and intractable problems, algorithms for linear and integer programs, graph optimization problems and algorithms, Boolean algebra and Applications. Hardware Modeling: Hardware Modeling Languages, distinctive features, structural hardware language, Behavioral hardware language, HDLs used in synthesis, abstract models, structures logic networks, state

diagrams, data flow and sequencing graphs, compilation and optimization techniques. Two Level Combinational Logic Optimization: Logic optimization, principles, operation on two level logic covers, algorithms for logic minimization, symbolic minimization and encoding property, minimization of Boolean relations. Multiple Level Combinational Optimizations: Models and transformations for combinational networks, algebraic model, Synthesis of testable network, algorithm for delay evaluation and optimization, rule based system for logic optimization. Sequential Circuit Optimization: Sequential circuit optimization using state based models, sequential circuit optimization using network models. Schedule Algorithms: A model for scheduling problems, Scheduling with resource and without resource constraints, Scheduling algorithms for extended sequencing models, Scheduling Pipe lined circuits. Cell Library Binding: Problem formulation and analysis, algorithms for library binding, specific problems and algorithms for library binding (lookup table F.P.G.As and Antifuse based F.P.G.As), rule based library binding.

Testing: Simulation, Types of simulators, basic components of a simulator, fault simulation Techniques, Automatic test pattern generation methods (ATPG), design for Testability (DFT) Techniques. REFERENCE BOOKS: 1.Giovanni De Micheli, Synthesis and Optimization of Digital Circuits," Tata McGraw-Hill, 2003. 2.Srinivas Devadas, Abhijit Ghosh, and Kurt Keutzer, Logic Synthesis, McGraw-Hill, USA, 1994. 3.Neil Weste and K. Eshragian, Principles of CMOS VLSI Design: A System Perspective , 2nd edition, Pearson Education (Asia) Pte. Ltd., 2000. 4.Kevin Skahill, VHDL for Programmable Logic, Pearson Education (Asia) Pte. Ltd., 2000.

ELECTIVE-II DIGITAL SIGNAL COMPRESSION Subject Code No. of Lecture Hours/Week Total No. of Lecture Hours : 10EC030 : 04 : 52 IA Marks Exam Hrs Exam Marks : 50 : 03 : 100

Introduction: Compression techniques, Modeling & coding, Distortion criteria, Differential Entropy, Rate Distortion Theory, Vector Spaces, Information theory, Models for sources, Coding uniquely decodable codes, Prefix codes, Kraft McMillan Inequality Quantization: Quantization problem, Uniform Quantizer, Adaptive Quantization, Non-uniform Quantization; Entropy coded Quantization, Vector Quantization, LBG algorithm, Tree structured VQ, Structured VQ, Variations of VQ Gain shape VQ, Mean removed VQ, Classified VQ, Multistage VQ, Adaptive VQ, Trellis coded quantization Differential Encoding: Basic algorithm, Prediction in DPCM, Adaptive DPCM, Delta Modulation, Speech coding G.726, Image coding. Transform Coding: Transforms KLT, DCT, DST, DWHT; Quantization and coding of transform coefficients, Application to Image compression JPEG, Application to audio compression. Sub-band Coding: Filters, Sub-band coding algorithm, Design of filter banks, Perfect reconstruction using two channel filter banks, M-band QMF filter banks, Poly-phase decomposition, Bit allocation, Speech coding G.722, Audio coding MPEG audio, Image compression. Wavelet Based Compression: Wavelets, Multiresolution analysis & scaling function, Implementation using filters, Image compression EZW, SPIHT, JPEG 2000.

Analysis/Synthesis Schemes: Speech compression LPC-10, CELP, MELP, Image Compression Fractal compression. Video Compression: Motion compensation, Video signal representation, Algorithms for video conferencing & videophones H.261, H. 263, Asymmetric applications MPEG 1, MPEG 2, MPEG 4, MPEG 7, Packet video.

Lossless Coding: Huffman coding, Adaptive Huffman coding, Golomb codes, Rice codes, Tunstall codes, Applications of Huffman coding, Arithmetic coding, Algorithm implementation, Applications of Arithmetic coding, Dictionary techniques LZ77, LZ78, Applications of LZ78 JBIG, JBIG2, Predictive coding Prediction with partial match, Burrows Wheeler Transform, Applications CALIC, JPEG-LS, Facsimile coding T.4, T.6. REFERENCE BOOKS: 1.K. Sayood, Introduction to Data Compression," Harcourt India Pvt. Ltd. & Morgan Kaufmann Publishers, 1996. 2.N. Jayant and P. Noll, Digital Coding of Waveforms: Principles and Applications to Speech and Video, Prentice Hall, USA, 1984. 3.D. Salomon, Data Compression: The Complete Reference, Springer, 2000. 4.Z. Li and M.S. Drew, Fundamentals of Multimedia, Pearson Education (Asia) Pte. Ltd., 2004.

Simulation Modeling and Analysis Subject Code No. of Lecture Hours/Week Total No. of Lecture Hours : 10EC128 : 04 : 70 IA Marks Exam Hours Exam Marks : 50 : 03 : 100

Basic simulation modeling: nature of simulation, system models, discrete event simulation, single server simulation, alternative approaches, other types of simulation. Building valid, credible and detailed simulation models. Techniques for increasing model validity and credibility, comparing real world observations. Selecting input probability distributions. Useful probability distributions, assessing sample independence, activity I, II and III. Models of arrival process. Random numbers generators: linear congruential, other kinds, testing random number generators. Random variate generation: approaches, continuous random variates, discrete random variates, correlated random variates. Output data analysis. Statistical analysis for terminating simulations, analysis for steady state parameters. Comparing alternative system configurations. Confidence intervals. Variance reduction techniques. Antithetic and Control variates. References: 1.Averill Law, Simulation modeling and analysis, MGH, 4th edition, 2007 2. Jerry Banks, Discrete event system simulation, Pearson, 2009. 3. Seila, Ceric, Tadikamalla, Applied simulation modeling, Cengage, 2009. 4. George S. Fishman, Discrete event simulation, Springer, 2001. 5. N. Viswanadham, Y. Narahari, Performance modeling of

6. 7.

automated manufacturing systems, PHI, 2000. Frank L. Severance, System modeling and simulation, Wiley, 2009 K. S. Trivedi, Probability and stastistics with reliability queuing and computer science applications, PHI, 2007.

ALGORITHMS FOR VLSI DESIGN AUTOMATION Subject Code No. of Lecture Hours/Week Total No. of Lecture Hours : 10EC010 : 04 : 52 IA Marks Exam Hrs Exam Marks : 50 : 03 : 100

Logic Synthesis & Verification: Introduction to combinational logic synthesis, Binary Decision Diagram, Hardware models for High-level synthesis. VLSI Automation Algorithms: Partitioning: problem formulation, classification of partitioning algorithms, Group migration algorithms, simulated annealing & evolution, other partitioning algorithms Placement, Floor Planning & Pin Assignment : problem formulation, simulation base placement algorithms, other placement algorithms, constraint based floor planning, floor planning algorithms for mixed block & cell design. General & channel pin assignment Global Routing: Problem formulation, classification of global routing algorithms, Maze routing algorithm, line probe algorithm, Steiner Tree based algorithms, ILP based approaches Detailed Routing: problem formulation, classification of routing algorithms, single layer routing algorithms, two layer channel routing algorithms, three layer channel routing algorithms, and switchbox routing algorithms Over the Cell Routing & Via Minimization: two layers over the cell routers, constrained & unconstrained via minimization Compaction: problem formulation, one-dimensional compaction, two dimension based compaction, hierarchical compaction REFERENCE BOOKS: 1.Naveed Shervani, Algorithms for VLSI Physical Design Automation, Kluwer Academic Publisher, Second edition. 2.Christophn Meinel & Thorsten Theobold, Algorithm and Data Structures for VLSI Design , KAP, 2002. 3.Rolf Drechsheler : Evolutionary Algorithm for VLSI, Second edition 4.Trimburger, Introduction to CAD for VLSI, Kluwer Academic publisher, 2002