By

Prof P P Ghadekar Vishwakarma Institute of Technology, Pune

Presentation Outline
Overview of VHDL VHDL Fundamentals Libraries and Packages Entities, Architectures, and Configurations Signals Data Types Operators Essential Language Statements Advanced Language Statements VHDL Examples Synthesis Vs. Simulation

Overview of VHDL
V ery High Speed Integrated Circuit H ardware D escription L anguage

VHDL language can be regarded as combination of following languages Sequential Language+ Concurrent Language+ Netlist Language+ Timing Specifications+ Waveform genration Language+ VHDL is a language that can be used to describe the structure and / or behaviour of hardware designs VHDL designs can be simulated and / or synthesized VHDL Hierarchical use of VHDL designs permits the rapid creation of complex hardware designs
3

History of VHDL
VHDL was developed by the VHSIC (Very High Speed Integrated Circuit) Program in the late 1970s and early 1980s VHDL was designed to be a documentation and simulation language VHDL is now used widely by industry and academia for both simulation and synthesis Two versions of VHDL have been standardized by the IEEE: VHDL87 - IEEE-1076-1987 VHDL93 - IEEE-1076-1993

Features of VHDL
VHDL has powerful constructs In VHDL, design may be decomposed hierarchically Each design elements has a well defined interface useful for connecting it to other elements. Test bench is available for Simulation VHDL handles asynchronous & synchronous sequential circuits. In VHDL, concurrency, timing and clocking can be modeled. In VHDL, design is target independent. VHDL support design library. The language is not case sensitive. A Formal Language for Specifying the Behavior and Structure of a Digital Circuit Allows Top-Down Design
5

Libraries and Packages

Libraries provide a set of hardware designs, components, and functions that simplify the task of designing Packages provide a collection of commonly used data types and subprograms used in a design The following is an example of the use of the IEEE library and its STD_LOGIC_1164 package: LIBRARY ieee; USE ieee.std_logic_1164.ALL;

Entities, Architectures, and Configurations

The structure of a VHDL design resembles the structure of a modern, object-oriented software design in the sense that every VHDL design describes both an external interface and an internal implementation A VHDL design consists of entities, architectures, and configurations

Entities
An Entity is something that has separate real existence. An entity is a specification of the designs external interface. Entity declarations specify the following: Name of the entity Set of port declarations defining the inputs and outputs to the hardware design The following is an example of an entity declaration: ENTITY andgate IS PORT ( a : IN b : IN c : OUT STD_LOGIC; STD_LOGIC; STD_LOGIC );

END andgate;
8

Architectures
An architecture is a specification of the designs internal implementation Multiple architectures can be created for a particular entity The following is an example of an architecture declaration: ARCHITECTURE r001 OF andgate IS BEGIN c <= a AND b; END r001;

Entity-Architecture Pair

entity name port names

port mode (direction) punctuation port type

reserved words
10

VHDL Program Structure

11

Ports
Port name choices: Consist of letters, digits, and/or underscores Always begin with a letter Case insensitive Port direction choices: IN Input port OUT Output port INOUT Bidirectional port BUFFER Buffered output port Port signal type (suggested) choices: STD_LOGIC STD_LOGIC_VECTOR(<max> DOWNTO <min>)

12

Configurations
A configuration is a specification of the mapping between an architecture and a particular instance of an entity A configuration exists for each entity The default configuration maps the most recently compiled architecture to the entity Configurations are often used to specify alternative simulation models for hardware designs

13

Signals
Signals represent wires and storage elements within a VHDL design Signals may only be defined inside architectures Signals are associated with a data type Signals have attributes It holds a list of values, which includes current value of the signal, and a set of possible future values that are to be appears on the signal. Future values can be assigned to a signal using a signal assignment statement i.e. <=

14

Process Statement
Process is a main concurrent statement in VHDL code. It describe the sequential behavior of the design. All statement within process executes sequentially in zero time. Only one driver is placed on a signal. The signal is updated with the last value assigned to it with in the process. Syntax begin process(sensitivity list) begin ----------end process Sensitivity List- List of signal on which process should execute after arranging its state. Every process must have either sensitivity list or wait statement.
15

Process Statements
-Assume that the following ports exist for this entity SIGNAL a, b, sel :IN STD_LOGIC; SIGNAL x, y :OUT STD_LOGIC; PROCESS (a, b, sel) -- a, b, and sel are in the sensitivity list to indicate -- that they are inputs to the process BEGIN IF (a = 0) THEN -- Only valid in a process x <= a OR b; ELSIF (b = 0) THEN x <= a XNOR b; ELSE x <= 0; END IF; CASE sel IS -- Only valid in a process WHEN 0 => y <= a AND b; WHEN OTHERS => y <= 1; END CASE; END PROCESS; 16

Built-In Data Types

VHDL supports a rich set of built-in data types as well as userdefined data types. Built-in data types work well for simulation but not so well for synthesis
Data Type BIT BIT_VECTOR INTEGER REAL Characteristics Binary, Unresolved Binary, Unresolved, Array Binary, Unresolved, Array Floating Point

Examples:
A: G: D: E: in bit; out boolean; in bit_vector(0 to 7); in bit_vector(7 downto 0);
17

STD_LOGIC_1164 Data Types

STD_LOGIC_1164 is a standardized package that implements a set of data types
Data Type STD_ULOGIC STD_ULOGIC_VECTOR STD_LOGIC STD_LOGIC_VECTOR Characteristics MVL 9, Unresolved MVL 9, Unresolved, Array MVL 9, Resolved MVL 9, Resolved, Array

IEEE recommends the use of the STD_LOGIC and STD_LOGIC_VECTOR data types

18

Logical Operators
VHDL supports the following logical operators: AND OR XOR XNOR NOT NAND NOR VHDL also supports the overloading of existing operators and the creation of new ones

19

Assignment Statements
SIGNAL x, y, z : STD_LOGIC; SIGNAL a, b, c : STD_LOGIC_VECTOR(7 DOWNTO 0); SIGNAL sel : STD_LOGIC_VECTOR(2 DOWNTO 0); -- Concurrent Signal Assignment Statements -- NOTE: Both x and a are produced concurrently x <= y AND z; a <= b OR c; -- Alternatively, signals may be assigned constants x <= 0; y <= 1; z <= Z; a <= "00111010"; -- Assigns 0x3A to a b <= X"3A"; -- Assigns 0x3A to b c <= X"3" & X"A"; -- Assigns 0x3A to c

20

Assignment Statements (cont.)

SIGNAL x, y, z :STD_LOGIC; SIGNAL a, b, c :STD_LOGIC_VECTOR( 7 DOWNTO 0); SIGNAL sel :STD_LOGIC_VECTOR( 2 DOWNTO 0); -- Conditional Assignment Statement -- NOTE: This implements a tree structure of logic gates x <= 0 WHEN sel = 000 ELSE y WHEN sel = 011 ELSE z WHEN x = 1 ELSE 1; -- Selected Signal Assignment Statement -- NOTE: The selection values must be constants WITH sel SELECT x <= 0 WHEN 000, y WHEN 011, z WHEN 100, 1 WHEN OTHERS; -- Selected signal assignments also work with vectors WITH x SELECT a <= 01010101 WHEN 1, b WHEN OTHERS;
21

AND-NAND Example

22

Different Modeling Styles

The architectural body between begin and end can have only one of the following modeling styles Behavioral Modeling Data flow Modeling Structural Modeling

23

Behavioral Style of Modeling

The behavioral style of modeling specifies the behavior of an entity as a set of statement that are executed sequentially in the specified order. A Process statement is a key element in the behavioral modeling. A process statement contains a set of sequential statements which specify the functionality of the model and not the exact structure of it. Process Statement is a concurrent statement which executes in parallel With other concurrent statement s and other processes.

24

Data flow style of Modeling

In this type of modeling , the flow of the data is expressed primarily using concurrent signal assignment statements. The structure of the entity is not explicitly specified in this type of modeling but it is inferred from the equation. The primary difference between Behavioral and Data flow modeling is that Behavioral modeling uses processes and other does not. Data flow description are used in the cases where we have simple design equations of the circuit.

25

Structural style of Modeling

An architecture that uses components is often called as Structural modeling. It defines the precise interconnection structure of signals and entities within that entity. A pure Structural description is equivalent to a schematic diagram or net list of the circuit.

26

Complete Example
Example 1 -- A Package with a procedure modeling the functionality of an OR gate package gate is procedure Or_gate(signal In1, In2 : bit; signal Out1 : out bit); end gate; package body gate is procedure Or_gate(signal In1, In2 : bit; signal Out1 : out bit) is begin Out1 <= In1 or In2; end Or_gate; end gate;

27

Half Adder
Example 2 -- Behavioral Description of a Half Adder entity Half_adder is generic ( AB_to_sum : TIME := 0 ns; AB_to_carry : TIME := 0 ns ); port ( A : in bit; B : in bit; Sum : out bit; Carry : out bit ); end Half_adder;

28

Half Adder (contd.)

architecture Behavioral of Half_adder is begin process begin Sum <= A xor B after AB_to_sum; Carry <= A and B after AB_to_carry; wait on A,B; end process; end Behavioral;

29

Full Adder
Example 2 -- Structural Description of a Full Adder that instantiates Half Adder and Uses procedure Or_gate from the package gate. use WORK.gate.all; -- use the Package gate entity Full_adder is port ( A : in bit; B : in bit; Carry_in : in bit; Sum : out bit; Carry_out : out bit ); end Full_adder;

30

Full Adder (contd.)

architecture structural of Full_adder is component Half_adder generic ( AB_to_sum : TIME := 0 ns; AB_to_carry : TIME := 0 ns ); port ( A : in bit; B : in bit; Sum : out bit; Carry : out bit ); end component; for all : Half_adder use entity work.Half_adder(behavioral);

31

Full Adder (contd.)

signal Temp_sum : bit; signal Temp_carry1 : bit; signal Temp_carry2 : bit; begin U0 : Half_adder generic map (5 ns, 5 ns) port map (A, B, Temp_sum, Temp_carry1); U1 : Half_adder generic map (5 ns, 5 ns) port map (A => Temp_sum, B => Carry_in, Sum => Sum, Carry => Temp_carry2); U3 : Or_gate ( Temp_carry1, Temp_carry2, Carry_out); end structural;

32

Test Bench
library STD; use STD.standard.all; use STD.textio.all; library testpackage; use testpackage.testpackage.all; entity fa_test is -- Entity for the test bench end fa_test; architecture bench of fa_test is component Full_adder -- Component declaration for Full Adder port ( A : in bit; B : in bit; Carry_in : in bit; Sum : out bit; Carry_out : out bit ); end component; for all : Half_adder use entity work.Full_adder(Structural

33

Test Bench (contd.)

signal A, B, Carry_in : bit; signal Sum, Carry_out : bit; signal temp : bit_vector(0 to 31); begin a1: Full_adder port map ( A, B, Carry_in, Sum, Carry_out); A <= temp(31); B <= temp(30); Carry_in <= temp(29); a2: process variable sttr : line; variable rando : integer; file dataout : text is out "data.out"; begin rando := 1;

34

Test Bench (contd.)

for i in 0 to 40 loop temp <= int2vec(rando); rando := (rando * 3)/2 +1; wait for 1 ms; write(sttr, string('(" A = ")); write(sttr, A); write(sttr, string('(" B = ")); write(sttr, B); write(sttr, string('(" Carry_in = ")); write(sttr, Carry_in); write(sttr, string('(" Sum = ")); write(sttr, Sum); write(sttr, string('(" Carry_out = ")); write(sttr, Carry_out); writeline (dataout, sttr); wait for 0 ns; end loop; wait; end process; end bench;

35

Basic VHDL Concepts

Interfaces Behavior Structure Test Benches Analysis, elaboration, simulation Synthesis

36

Modeling Interfaces
Entity declaration
describes the input/output ports of a module
entity name port names port mode (direction)

entity reg4 is port ( d0, d1, d2, d3, en, clk : in bit; q0, q1, q2, q3 : out bit ); end entity reg4;
reserved words port type

punctuation

37

VHDL-87
Omit entity at end of entity declaration

entity reg4 is port ( d0, d1, d2, d3, en, clk : in bit; q0, q1, q2, q3 : out bit ); end reg4;

38

Modeling Behavior
Architecture body
describes an implementation of an entity may be several per entity

Behavioral architecture
describes the algorithm performed by the module contains process statements, each containing sequential statements, including signal assignment statements and wait statements

39

Behavior Example
architecture behav of reg4 is begin storage : process is variable stored_d0, stored_d1, stored_d2, stored_d3 : bit; begin if en = '1' and clk = '1' then stored_d0 := d0; stored_d1 := d1; stored_d2 := d2; stored_d3 := d3; end if; q0 <= stored_d0 after 5 ns; q1 <= stored_d1 after 5 ns; q2 <= stored_d2 after 5 ns; q3 <= stored_d3 after 5 ns; wait on d0, d1, d2, d3, en, clk; end process storage; end architecture behav;
40

VHDL-87
Omit architecture at end of architecture body Omit is in process statement header
architecture behav of reg4 is begin storage : process ... begin ... end process storage; end behav;

41

Modeling Structure
Structural architecture
implements the module as a composition of subsystems contains signal declarations, for internal interconnections
the entity ports are also treated as signals

component instances
instances of previously declared entity/architecture pairs

port maps in component instances

connect signals to component ports

wait statements

42

Structure Example
d0 bit0 d_latch d q clk bit1 d_latch d q clk bit2 d_latch d q clk bit3 d_latch d q gate and2 a y b clk int_clk q0

d1

q1

d2

q2

d3

q3

en clk

43

Structure Example
First declare D-latch and and-gate entities and architectures
entity d_latch is port ( d, clk : in bit; q : out bit ); end entity d_latch; architecture basic of d_latch is begin latch_behavior : process is begin if clk = 1 then q <= d after 2 ns; end if; wait on clk, d; end process latch_behavior; end architecture basic; entity and2 is port ( a, b : in bit; y : out bit ); end entity and2; architecture basic of and2 is begin and2_behavior : process is begin y <= a and b after 2 ns; wait on a, b; end process and2_behavior; end architecture basic;

44

Structure Example
Now use them to implement a register
architecture struct of reg4 is signal int_clk : bit; begin bit0 : entity work.d_latch(basic) port map ( d0, int_clk, q0 ); bit1 : entity work.d_latch(basic) port map ( d1, int_clk, q1 ); bit2 : entity work.d_latch(basic) port map ( d2, int_clk, q2 ); bit3 : entity work.d_latch(basic) port map ( d3, int_clk, q3 ); gate : entity work.and2(basic) port map ( en, clk, int_clk ); end architecture struct;
45

VHDL-87
Cant directly instantiate entity/architecture pair Instead
include component declarations in structural architecture body templates for entity declarations instantiate components write a configuration declaration binds entity/architecture pair to each instantiated component

46

Structure Example in VHDL-87

First declare D-latch and and-gate entities and architectures
entity d_latch is port ( d, clk : in bit; q : out bit ); end d_latch; architecture basic of d_latch is begin latch_behavior : process begin if clk = 1 then q <= d after 2 ns; end if; wait on clk, d; end process latch_behavior; end basic; entity and2 is port ( a, b : in bit; y : out bit ); end and2; architecture basic of and2 is begin and2_behavior : process begin y <= a and b after 2 ns; wait on a, b; end process and2_behavior; end basic;

47

Structure Example in VHDL-87

Declare corresponding components in register architecture body
architecture struct of reg4 is component d_latch port ( d, clk : in bit; q : out bit ); end component; component and2 port ( a, b : in bit; y : out bit ); end component; signal int_clk : bit; ...

48

Structure Example in VHDL-87

Now use them to implement the register
... begin bit0 : d_latch port map ( d0, int_clk, q0 ); bit1 : d_latch port map ( d1, int_clk, q1 ); bit2 : d_latch port map ( d2, int_clk, q2 ); bit3 : d_latch port map ( d3, int_clk, q3 ); gate : and2 port map ( en, clk, int_clk ); end struct;

49

Structure Example in VHDL-87

Configure the register model
configuration basic_level of reg4 is for struct for all : d_latch use entity work.d_latch(basic); end for; for all : and2 use entity work.and2(basic) end for; end for; end basic_level;

50

Mixed Behavior and Structure

An architecture can contain both behavioral and structural parts
process statements and component instances collectively called concurrent statements processes can read and assign to signals

Example: register-transfer-level model

data path described structurally control section described behaviorally

51

Mixed Example
multiplier multiplicand

shift_reg

control_ section

shift_ adder

reg

product

52

Mixed Example
entity multiplier is port ( clk, reset : in bit; multiplicand, multiplier : in integer; product : out integer ); end entity multiplier; architecture mixed of mulitplier is signal partial_product, full_product : integer; signal arith_control, result_en, mult_bit, mult_load : bit; begin arith_unit : entity work.shift_adder(behavior) port map ( addend => multiplicand, augend => full_product, sum => partial_product, add_control => arith_control ); result : entity work.reg(behavior) port map ( d => partial_product, q => full_product, en => result_en, reset => reset ); ...
53

Mixed Example
multiplier_sr : entity work.shift_reg(behavior) port map ( d => multiplier, q => mult_bit, load => mult_load, clk => clk ); product <= full_product; control_section : process is -- variable declarations for control_section -- begin -- sequential statements to assign values to control signals -- wait on clk, reset; end process control_section; end architecture mixed;

54