The 80c196 Architecture

The 80c196 architecture 1.
1 The 80c196 family

The 80c196KB is an 16-bit microcontroller made by Intel using CHM ! technology" The 80c196KB integrates on a single chi# all inter$ace elements %hich are generally in the close en&ironment o$ a micro#rocessor" The 80c196KB'KC #ro&ide ( )*) internal byte registers + register-to-register architecture ,ynamically con$igurable 8-bit or 16-bit bus%idth ,M+ ca#ability + 16-16-bit )"* microsecond multi#ly .at 1)MH/0 + *)'16-bit 1"0 microsecond di&ide .at 1)MH/0 )8 interru#t sources %ith 16 &ectors 6 16-bit timers2 u#'do%n counters or so$t%are timers + high s#eed I' subsystem + serial #ort + 10-bit digital-to-analog con&erter %ith sam#le-and-hold 3 8-bit I' #orts + 16-bit %atchdog timer 4o%erdo%n and idle modes +dditional )36 bytes o$ on-chi# 5+M .KC only0 The 86c196KB'KC are e7ui&alent to the 80c196KB'KC %ith additional 88 on-chi# 945 M"
Intel 80c196 16-bit Microcontrollers
The 80c196 architecture 1.2 80c196 architecture
Block dia ram The 80c196 is mainly based on ( + C4: %hich is turn com#osed o$ a 16-bit +;: %ith tem#orary registers2 a )36byte 5+M used as )1 s#ecial registers and )*) general registers2 and a micro#rogrammed se7uencer" + memory controller %ith a 1-byte <I< 7ueue to #re$etch instructions and data $rom the #rogram memory" + set o$ I' inter$aces" The C4: gets his in$ormation only through the memory controller and the s#ecial registers also called !#ecial <unction 5egisters .!<5s0" The +;:2 is associated to a set o$ tem#orary registers .%ith shi$ter2 counter2 constants0 and thus called 5+;: .5egister +;:0" The 5+;: doesn=t use an accumulator but instead is ablt to directly %or8 %ith any o$ the )36 s#ecial or general registers +ll I' o#erations are controlled through the !<5s"
80c196 bloc8 diagram
Memory controller +ll o$ the #rogram memory and e-ternal data memory are trans$erred to the C4: through the memory controller" The memory controller consists o$ a sla&e #rogram counter2 an instruction 7ueue and a bus controller" The sla&e #rogram counter 8ee#s trac8 o$ the instructions $etched $rom the #rogram memory" Instructions $etched by the memory controller are stored in the 7ueue" The sla&e #rogram counter may be u# to $our bytes ahead o$ the main #rogram counter .%hich is located in the 5+;:02 because it is #re-$etching the instructions" The bus controller accesses #rogram memory .on-chi# 945 M0 and e-ternal data memory and arbitrates bet%een instruction $etches and data reads and %rites" The bus controller su##orts both 8-bit and 16-bit e-ternal bus modes" Memory access re7uests to the bus controller can come $rom either the 5+;: or the 7ueue2 %ith #riority gi&en to the 7ueue accesses" I$ the address se7uence changes because o$ a >um#2 interru#t2 call or return2 the sla&e 4C is loaded %ith a ne% &alue2 and the 7ueue is $lushed" 5eloading the sla&e 4C2 $lushing the 7ueue and $etching the the $irst byte o$ the ne% instruction stream ta8es 1 state times" This is re$lected in the conditional >um# ta8en'not-ta8en e-ecution times" The !"# The C4: is controlled by a microcode se7uencer and can #er$orm o#erations on any byte2 %ord or double-%ord in the )36-byte register s#ace" Instructions to the C4: are ta8en $rom the #re-$etch 7ueue and tem#orarily stored in the instruction register" The se7uencer decodes the instruction and generates the correct se7uence o$ e&ents to ha&e the 5+;: #er$orm the desired o#eration" The $%&# Most calculations #er$ormed by the 80c196 ta8e #lace in the 5+;:" The 5+;: contains a 16-bit +;: - +rithmetic and ;ogic :nit2 the $lag register also called 4!? 4rogram !tatus ?ord2 the main 4C - 4rogram Counter2 a loo# counter and three tem#orary registers" +ll registers are 16-bits or 16-bits %ide"
The 5egister +rithmetic and ;ogic :nit
The 4C has a se#arate incrementor as to access o#erands" Ho%e&er2 4C changes due to >um#s2 interru#ts2 calls and returns are handled through the +;:" T%o o$ the tem#orary registers ha&e their o%n shi$t logic" These registers are used $or the instructions %hich re7uire logical shi$ts2 including @ormali/e2 Multi#ly and ,i&ide" The u##er %ord and lo%er %ord registers are used together $or the *)-bit instructions and as tem#orary registers $or many other instuctions" 5e#etiti&e shi$ts are counted by the 6-bit loo# counter" + third tem#orary register stores the second o#erand o$ t%o-o#erand instructions" To #er$orm subtractions the out#ut o$ this register can be com#lemented be$ore being #laced into the in#ut o$ the +;:" The 5+;: also stores se&eral constants such as 021 and ) to s#eed u# certain o#erations li8e getting a )=s com#lement2 incrementing or decrementing"
+ll rights reser&ed <or more in$ormation #lease contact ,aniel Muller
;ast u#dated ( <ri ,ec 3 11(16(39 M9T 1996
The 80c196 architecture 1.' Memory s(ace

%ddressable s(ace The addressable memory s#ace o$ the 80c196 consists o$ 618 bytes" Ho%e&er2 not all these addresses are a&ailable to the user" +ddresses 0000H through 00FFH and 1FFEH through 207FH are reser&ed $or s#ecial #ur#oses" +ll other locations can be used $or either #rogram or data storage2 or $or memory-ma##ed I' "
FFFFH +-------------------------+ | | | External memory or I/O | | | 4000H +-------------------------+ | Internal ROM/EPROM or | | external memory or I/O | 2080H +-------------------------+ | Reserve | 2040H +-------------------------+ | 8 !nterr"#t ve$tors | 20%0H +-------------------------+ | ROM/EPROM se$"r!ty &ey | 2020H +-------------------------+ | Reserve | 201'H +-------------------------+ | ()!# (on*!+"rat!on ,yte | 2018H +-------------------------+ | Reserve | 2014H +-------------------------+ | 10 !nterr"#t ve$tors | 2000H +-------------------------+ | Port % an #ort 4 | 1FFEH +-------------------------+ | External memory or I/O | 0200H +-------------------------+ | 80$1'-.( !nternal R/M | 0100H +-------------------------+ | Re+!sters an 0FRs |
0000H +-------------------------+ 80c196 addressable s#ace
$e isters .internal 5+M0 ;ocations 00H through OFFH contain the )*) general registers and the )1 !<5s !#ecial <unction 5egisters" The 5+;: can o#erate on any o$ these )36 internal register locations2 but code cannot be e-ecuted $rom them" I$ attem#t is made to e-ecute instructions $rom locations 00H through OFFH2 the instructions %ill be $etched $rom e)ternal memory" This section o$ e-ternal memory is generally used by the Intel de&elo#ment tools" ;ocations 018H through OFFH are the general registers" These locations can be accessed as byte2 %ord ou double-%ord registers2 and can be essentially considered as )*) accumulators" ;ocations 018H and O1'H contain the stac8 #ointer" #erations to the stac8 cause it to be built do%n and the stac8 #ointer is #re-decremented2 so the stac8 must be initiali/ed by the user #rogram to ) bytes abo&e the highest stac8 location" The stac8 #ointer must #oint to a %ord .e&en0 address" *(ecial +unction $e isters .!<5s0 ;ocations 00H through O17H are the I' control registers or !<5s" +ll o$ the #eri#heral de&ices o$ the 80c196 e-ce#t #orts * and 1 are controlled through these registers" !<5 $unctions are controlled through * %indo%s" !%itching bet%een the %indo%s is done using the ?!5 - ?indo% !elect 5egister located at address 011H" !<5 %indo%s other than 10R 2 0 are out o$ the sco#e o$ this course" !ome o$ the !#ecial <untion 5egisters ha&e di$$erent meanings i$ read $rom or %ritten to" $eser,ed memory locations ;ocations 1FFEH and O1FFFH are used $or 4orts * and 1 res#ecti&ely" Many reser&ed and s#ecial locations are in the memory area bet%een 2000H and 2080H" The 18 interru#t &ectors2 the chi# con$iguration byte and the security 8ey are located in this area" +ll the addresses mar8ed Reserved in this area ha&e to be #rogrammed %ith &alue 0FFH"
2080H !s t)e normal #ro+ram start a t)e #ro+ram at a ress 2080H3 ress3 / reset !nterr"#t restarts
-)ternal memory There are se&eral modes o$ system bus o#eration on the 80c196" The standard bus mode uses a 16-bit multi#le-ed address'data bus" ther bus modes include an 8-bit mode and a mode in %hich the bus si/e can be dynamically s%itched bet%een 8-bits and 16-bits" In addition2 there are se&eral o#tions a&ailable on the ty#e o$ bus control signals %hich ma8e an e-ternal bus sim#le to design" In the standard mode2 e-ternal memory is addressed through lines /40-/415 %hich $orm a 16-bit multi#le-ed bus" The ideali/ed bus timings are re#resented belo% (
!tandard mode ideali/ed bus timings
The /6E - +ddress ;atch 9nable signal #ro&ides a strobe $or $li#-$lo#s .e"g" 61-*6*s0 to demulti#le- the bus by latching the address" ,emulti#le-ed address signals %ill be called M/0-M/15" The data returned $rom e-ternal memory must be on the bus and stable $or a s#eci$ied setu# time be$ore the rising edge o$ 7R4 .5ead0" The rising edge o$ 7R4 signals the end o$ the sam#ling %indo%" ?riting to e-ternal memory is controlled %ith the 71R .?rite0 #in" ,ata is &alid on /40-15 on the rising edge o$ 71R" +t this time data must be latched by the e-ternal system" In standard 16-bit mode2 the e-ternal memory is com#osed o$ t%o #arallel 8-bit memory ban8s" !ince a gi&en address selects one byte2 the 16-bit data bus has to be reconstructed $rom the lo%-order byte located at the e&en address2 and the high-order byte located at the odd address .see <igure0" The 78HE signal is #ro&ided $or 16-bit bus accesses" Together %ith M/02 this signal allo%s to select either the lo%-order byte2 the high order-byte2 or both bytes during a 16-bit bus access ( Memory bank selection .B/0 %0 0 selected bank high order A lo% order
0 1
1 0
high order only lo% order only
+ctually2 %hen a bloc8 o$ memory is decoded $or reads only2 %hich is ty#ically the case o$ 945 M!2 the system does not ha&e to decode 78HE and M/0 ( the 80c196 %ill discard the byte it does not need" But $or systems that %rite to e-ternal memory2 se#arate %rite strobes must be generated $or both the high and lo% bytes o$ memory"
16-bit system %ith e-ternal 945 M
The system abo&e adds 88-bytes o$ memory .e"g" a )6610 to a 86c196" This #rocessor already has 88 o$ internal 945 M2 seen at locations 2000H through %FFFH" The system abo&e decodes M/14 to select the e-ternal memories2 resulting in the microcontroller seeing them at locations 4000H through 7FFFH2 >ust a$ter the internal memory (
15 14 1% 12 11 10 9 1 - - - ' 8 7 5 4 % 2 1 0 -
To connect )61)8 .168-bytes0 e-ternal memories the system should select them %ith /15 9OR /14 to #lace them at locations 4000H through 08FFFH" To connect 945 M to a 80c1962 %ithout internal memory2 the system is e&en sim#ler" The memory chi#s can be connected %ithout decoding any address line" This means that an 88-bytes chi# %ill be seen at locations 0000H through 0%FFFH" Ho%e&er2 most o$ the locations $rom 0000H through 01FFFH are reser&ed $or internal registers and 5+M" This is hal$ o$ the address s#ace o$ the memories B The tric8 consists in normally #rogramming the u##er hal$ o$ the memories2 and #rogramming their lo%er hal$ .addresses 0000H through 01FFFH0 as corres#onding to locations 4000H through 05FFFH" !ince M/14 is not decoded2 %hen the #rocessor
accesses the cells 4000H through 05FFFH the memories are actually selected %ith an address corres#onding to their lo%er hal$ B
;ast u#dated ( <ri ,ec 3 11(31()0 M9T 1996
"ro rammin the 80c196 2.1 0(erands

The 80c196 su##orts a &ariety o$ data ty#es ( Bytes .8 bits0 1ords .16 bits0" ?ords must be aligned to an e&en a ddress" The 80c196 is little endian2 thus storing the lo%-order data byte o$ a %ord at the e&en location2 and the high order byte at the odd location" 2ouble-3ords .*) bits0" ,ouble-%ords are only used by shi$t o#erations2 as the di&idend o$ a di&ide instruction2 or as the result o$ a multi#ly" <or these o#erations2 the double-%ord must reside on the on-chi# register $ile .locations 00H through 100H02 and be aligned at an address e&enly di&isible by 1"
;ast u#dated ( <ri ,ec 3 11(31(*6 M9T 1996
"ro rammin the 80c196 2.2 %ddressin modes

#erands are accessed %ithin the address s#ace o$ the 80c196 %ith one o$ 6 basic addressing modes" !ome o$ the details o$ ho% these addressing modes %or8 are hidden by the assembler language" Throughout this cha#ter short sections o$ code are used to illustrate the described o#erations" +ll o$ these assume that $ollo%ing symbols ha&e been de$ined ( %45 B45 !45 24 are 16-bit registers %&5 %/ are the lo%er byte and the higher byte o$ %4 res#ecti&ely B&5 B/ are the lo%er byte and the higher byte o$ B4 res#ecti&ely !&5 !/ are the lo%er byte and the higher byte o$ !4 res#ecti&ely 2&5 2/ are the lo%er byte and the higher byte o$ 24 res#ecti&ely These are the same as the names $or the general data registers used in the 8086" It is im#ortant to understand that in the 80c196 these are not dedicated registers2 but merely the symbolic name assigned by the #rogrammer to $our %ords %ithin the on-chi# )*) general registers" 2irect addressin The register-direct mode is used to directly access a register2 selected by an 8-bit $ield %ithin the instruction" The register address must con$orm to the o#erand=s ty#e alignment rules" -)am(les
/44 I?(8 /9:89:(9 (6 ; </9=1- >-- <89=1- + <(9=1; <(6=8 >-- <(6=8 + 1
Im(ortant note 6 +n instruction can contain only one non-direct o#erand re$erence"
+ll other o#erands o$ the instruction must be register-direct re$erences" Indirect addressin The indirect mode is used to access an o#erand ha&ing its address in a %ord register" The indirect address may #oint any%here into the address s#ace2 but must con$orm to the o#erand=s ty#e alignment rules" The register %hich contains the indirect address is selected by an 8-bit $ield %ithin the instruction" -)am(les
64 /448 POP 89:@/9A /6:86:@(9A @/9A ; ; ; ; <89=1- >-- <</9=1-=1</6=8 >-- <86=8 + <<(9=1-=8 <</9=1-=1- >-- <<0P=1-=1<0P=1- >-- <0P=1- + 2
Indirect addressin 3ith (ost-increment This addressing mode is the same as the indirect mode e-ce#t that the %ord %hich contains the address is incremented after it is used to address the o#erand" I$ the o#erand is a byte the address %ill be incremented by 12 i$ it is a %ord the address %ill be incremented by )" -)am(les
64 /448 PB0H /9:@89A+ /6:86:@(9A+ @/9A+ ; ; ; ; ; ; ; </9=1- >-- <<89=1-=1<89=1- >-- <89=1- + 2 </6=8 >-- <86=8 + <<(9=1-=8 <(9=1- >-- <(9=1- + 2 <0P=1- >-- <0P=1- - 2 <<0P=1-=1- >-- <</9=1-=1</9=1- >-- </9=1- + 2
Immediate addressin This addressing mode allo%s an o#erand to ta8en directly $rom a $ield in the instruction" <or o#erations on bytes this $ield is 8-bit %ide2 $or o#erations on %ords it is 16-bit %ide" -)am(les
/44 PB0H 4ID8 /9:C%40 C12%4H /9:C10 ; ; ; ; ; </9=1- >-- </9=1- + %40 <0P=1- >-- <0P=1- - 2 <<0P=1-=1- >-- 12%4H </6=8 >-- </9=1- / 10 </H=8 >-- </9=1- E 10
*hort inde)ed addressin In this addressing mode an 8-bit $ield in the instruction selects a %ord register %hich contains an address" + second 8-bit $ield in the instruction stream .dis#lacement0 is sign-e-tended and summed %ith the register &alue to $orm the address o$ the o#erand" !ince the dis#lacement is sign-e-tended2 the e$$ecti&e address can be u# to 1)8 bytes be$ore the address in the register2 or u# to 1)6 bytes a$ter it" -)am(les
64 MB68 /9:12@89A /9:86:%@(9A ; </9=1- >-- <<89=1- + 12=1; </9=1- >-- <86=8 F <<(9=1- + %=8
&on inde)ed addressin This addressing mode is li8e short inde-ed addressing e-ce#t that the dis#lacement is a 16-bit $ield ta8en $rom the instruction stream to $orm the address o$ the o#erand" @o sign e-tension is necessary" -)am(les
<(9=1-=1</9=1<(9=1-=8 /?4 0G /448 /9:89:G/86E@(9A ; </9=1- >-- <89=1- 3 <G/86E1- + /9:G/86E@89A ; </9=1- >-- <G/86E1- + <89=1-=1- >--
/6:86:G/86E@(9A ; </6=8 >-- <86=8 + <G/86E1- +
These are the si- basic address modes the 80c196 uses $or accessing o#erands" Ho%e&er2 se&eral other use$ul addressing o#erations can be achie&ed by combining these basic modes %ith s#eci$ic registers such as C95 or the stac8 #ointer ( Memory direct addressin This mode o$ addressing is obtained by inde-ing !<5 C95 2 located at address 0 %hich is $i-ed to &alue 0" In addition to #ro&iding a $i-ed source o$ the constant 0 $or calculations and com#arisons2 this register can be used as the inde- in a long-inde-ed re$erence" This combination o$ register selection and address mode allo%s any location in memory to be addressed directly" -)am(les
/44 POP /9:12%4@0A 5-78@0A ; </9=1- >-- </9=1- + <12%4=1; <5-78=1- >-- <<0P=1-=1; <0P=1- >-- <0P=1- + 2
%ccessin the stack
The system stac8 #ointer is accessed as register 18H o$ the !<5s" In addition to #ro&iding $or con&enient mani#ulation o$ the stac8 #ointer2 this also $acilitates accessing o#erands in the stac8" The to# o$ the stac82 $or e-am#le2 can be accessed by using the stac8 #ointer as the register in an indirect re$erence" In a similar $ashion2 the stac8 #ointer can be used in the sort inde-ed mode to access data %ithin te stac8" -)am(les
64 PB0H 64 !nto 89 /9:@0PA @0PA 89:2@0PA ; ; ; ; ; ; $o#y to# o* sta$& !nto /9 </9=1- >-- <<0P=1-=1"#l!$ate to# o* sta$& <0P=1- >-- <0P=1- - 2 <<0P=1-=1- >-- <<0P=1- + 2=1- >-$o#y next to last ata on sta$& <<0P=1- + 2=1-
; <89=1- >--
!ome o$ the details o$ these addressing modes are hidden by the assembler language2 %hich sim#li$ies the choice o$ the correct mode in se&eral as#ects ( The assembler %ill automatically choose bet%een register-direct addressing and longinde-ed addressing %ith regster C95 2 de#ending on %here the o#erand is located in memory" The #rogrammer can sim#ly re$er to the o#erand by its symbolic name" I$ the o#erand is %ithin the )36 registers a register-direct re$erence %ill be used2 i$ the o#erand is else%here in memory a long-inde-ed re$erence %ill be generated" The assembler %ill choose bet%een short and long inde-ing de#ending on the &alue o$ the dis#lacement" I$ the &alue can be e-#ressed in 8 bits then short inde-ing %ill be used2 i$ cannot then long inde-ing %ill be generated"
;ast u#dated ( <ri ,ec 3 06(18(0) M9T 1996
"ro rammin the 80c196 2.' "ro ram *tatus 1ord

The 4!? - 4rogram !tatus ?ord is a collection o$ boolean $lags %hich retain in$ormation concerning the state o$ the #rogram" The 8 status bits %hich $orm the most signi$icant byte o$ the 4!? cannot be accessed directly2 since there is no !<5 $or the 4!?" The only %ay o$ accessing them indirectly %ould be to use the 4:!H< instruction to #ush them to the stac82 and to #o# them bac8 into a register" The 8 status bits are (
!onditions fla s
7 ( The Cero $lag is set to indicate that the o#eration generated a result e7ual to /ero" <or the add-%ith-carry .+,,C0 and subtract-%ith-borro% .!:BB0 o#erations the 7 $lag is cleared i$ the result is not /ero2 but is ne&er set" These t%o instructions are normally used on con>unction %ith the +,, and !:B instructions to #er$orm multi#le #recision arithmetic" Theo#eration o$ the 7 $lag $or these o#erations lea&es it indicating the #ro#er result $or the entire multi#le #recision calculation" 8 ( The @egati&e $lag is set to indicate that the o#eration generated a negati&e result" The 8 $lag %ill be in the algebraically correct state e&en i$ an o&er$lo% occurs" <or shi$t o#erations the 8 $lag %ill be set to the same &alue as the most signi$icant bit o$ the result" This is true e&en i$ the shi$t count is 0" 9 ( The oDer$lo% $lag is set to indicate that the o#eration generated a result %hich is outside the range $or the destination data ty#e" <or the le$t shi$t o#erations the 9 $lag %ill be set i$ the most signi$icant bit changes at any time during the shi$t" 9T ( The oDer$lo% Tra# $lag is set %hen the 9 $lag is set2 but is only cleared by the C;5DT2 EDT and E@DT instructions" The o#eration o$ the 9T $lag allo%s testing $or a #ossible o&er$lo% condition at the end o$ a se7uence o$ related arithmetic o#erations" This is generally more e$$icient than testing the 9T $lag a$ter each instruction" ! ( The Carry $lag is set to indicate the state o$ the arithmetic carry $rom the most signi$icant bit o$ the +;: $or arithmetic o#erations2 or the state o$ the last bit shi$ted out o$ an o#erand $or shi$t o#erations" +rithmetic borro% a$ter a subtract o#eration is the com#lement o$ the ! $lag .i"e" i$ the o#eration generated a borro% the ! $lag is
cleared0" 4 ( 5eser&ed" !hould al%ays be cleared %hen %riting to the 4!? .c$" 4 4< instruction0" I ( The global Interru#t disable bit disables all interru#ts e-ce#t 8MI %hen cleared" *T ( The !Tic8y bit $lag is set to indicate that during a shi$t a 1 has $irst been shi$ted into the ! $lag2 and then shi$ted out" The *T $lag is unde$ined a$ter a multi#ly o#eration" The *T $lag can be used along %ith the ! $lag to control rounding a$ter a right shi$t" Consider multi#lying to 8-bit 7uantities and then scaling the result do%n to 1) bits (
MB6B8 0HR /9:(6:46 /9:C4 ; /9 >-- (6F46 ; s)!*t r!+)t 4 #la$es
I$ the ! $lag is set a$ter the shi$t2 it indicates that the bits shi$ted o$$ the end o$ the o#erand %ere greater-than or e7ual-to hal$ the ;!B o$ the result" ?ithout the *T $lag2 the rounding decision must be made on the basis o$ the ! $lag alone" The *T $lag allo%s a $iner resolution in the rounding decision ( ! *T 9alue of the bits shifted off 0 0 1 1 0 1 0 1 &alue F 0 0 G &alue 1') ;!B &alue F 1') ;!B &alue H 1') ;!B
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Muller
"ro rammin the 80c196 2.: Instruction set

)"1"1 Initiali/ations )"1") ,ata trans$er )"1"* !tac8 o#erations )"1"1 +rithmetic o#erations )"1"3 ;ogical o#erations )"1"6 !hi$ts )"1"6 Com#arisons )"1"8 Eum#s and calls )"1"9 Conditional >um#s )"1"10 Control
"ro rammin the 80c196 2.:.1 Initiali;in
!&$ - Clear ?ord !&$B - Clear Byte !&$! - Clear Carry <lag !&$9T - Clear &er$lo% Tra# *-T! - !et Carry <lag
;ast u#dated ( <ri ,ec 3 06(16(** M9T 1996
"ro rammin the 80c196 2.:.2 2ata transfer

BM09- - Bloc8 Mo&e .80c196KB only0
&2 - ;oad ?ord &2B - ;oad Byte &2B*- - ;oad Integer %ith !hort-Integer &2B7- - ;oad ?ord %ith Byte *T - !tore ?ord *TB - !tore Byte
"ro rammin the 80c196 2.:.' *tack o(erations

"0" - 4o# ?ord "0"% - 4o# +ll .80c196KB only0 "0"+ - 4o# <lags "#*/ - 4ush ?ord "#*/% - 4ush +ll .80c196KB only0
"#*/+ - 4ush <lags
"ro rammin the 80c196 2.:.: %rithmetic o(erations

%22 - +dd ?ords %22B - +dd Bytes %22! - +dd ?ords %ith Carry %22!B - +dd Bytes %ith Carry 2-! - ,ecrement ?ord 2-!B - ,ecrement Byte 2I9 - ,i&ide Integers .signed0 2I9B - ,i&ide !hort Integers .signed0 2I9# - ,i&ide ?ords .unsigned0 2I9#B - ,i&ide Bytes .unsigned0
-4T - !ign 9-tend Integer into ;ong-Integer -4TB - !ign 9-tend !hort-Integer into Integer I8! - Increment ?ord I8!B - Increment Byte M#& - Multi#ly Integers .signed0 M#&B - Multi#ly !hort Integers .signed0 M#&# - Multi#ly ?ords .unsigned M#&#B - Multi#ly Bytes .unsigned 8-< - @egate Integer 8-<B - @egate !hort-Integer 80$M& - @ormali/e ;ong-Integer *#B - !ubtract ?ords *#BB - !ubtract Bytes *#B! - !ubtract ?ords ?ith Borro% *#B!B - !ubtract ?ords ?ith Borro%
"ro rammin the 80c196 2.:.= &o ical o(erations

%82 - Bit%ise ;ogical +@, ?ords %82B - Bit%ise ;ogical +@, Bytes 80T - Com#lement ?ord 80TB - Com#lement Byte 0$ - Bit%ise ;ogical 5 ?ords 0$B - Bit%ise ;ogical 5 Bytes 40$ - Bit%ise ;ogical I 5 ?ords 40$B - Bit%ise ;ogical I 5 Bytes
;ast u#dated ( <ri ,ec 3 06(16()) M9T 1996
"ro rammin the 80c196
2.:.6 *hifts
*/& - ;e$t !hi$t ?ord */&B - ;e$t !hi$t Byte */&& - ;e$t !hi$t ,ouble-?ord */$ - ;ogical 5ight !hi$t ?ord */$% - +rithmetic 5ight !hi$t ?ord */$%B - +rithmetic 5ight !hi$t Byte */$%& - +rithmetic 5ight !hi$t ,ouble-?ord */$B - ;ogical 5ight !hi$t Byte */$& - ;ogical 5ight !hi$t ,ouble-?ord
;ast u#dated ( <ri ,ec 3 06(16(1* M9T 1996
"ro rammin the 80c196 2.:.> !om(arisons

!M" - Com#are ?ords
!M"B - Com#are Bytes !M"& - Com#are ;ong .80c196KB only0
"ro rammin the 80c196 2.:.8 #nconditional ?um(s and calls

B$ - Branch Indirect &!%&& - ;ong Call &@M" - ;ong Eum# $-T - 5eturn $rom !ubroutine *!%&& - !hort Call *@M" - !hort Eum#
;ast u#dated ( <ri ,ec 3 06(16()6 M9T 1996
"ro rammin the 80c196 2.:.9 !onditional ?um(s

2@87 - ,ecrement and Eum# i$ not Cero 2@871 - ,ecrement and Eum# i$ @ot Cero ?ord .80c196KB only0 @B! - Eum# i$ Bit Clear @B* - Eum# i$ Bit !et @! - Eum# i$ Carry @- - Eum# i$ 97ual @<- - Eum# i$ Jreater or 97ual .signed0 @<T - Eum# i$ Jreater than .signed0 @/ - Eum# i$ Higher .unsigned0 @&- - Eum# i$ ;ess or 97ual .signed0 @&T - Eum# i$ ;ess than .signed0 @8! - Eum# i$ @o Carry @8- - Eum# i$ @ot 97ual @8/ - Eum# i$ @ot Higher .unsigned0
@8*T - Eum# i$ @o !tic8y bit @89 - Eum# i$ @o &er$lo% @89T - Eum# i$ @o &er$lo% Tra# @*T - Eum# i$ !tic8y bit @9 - Eum# i$ &er$lo% @9T - Eum# i$ &er$lo% Tra#
"ro rammin the 80c196 2.:.10 !ontrol

2I - ,isable Interru#ts -I - 9nable Interru#ts I2&"2 - Idle ' 4o%erdo%n .80c196KB only0 80" - @o #eration $*T - 5eset !ystem
*AI" - T%o-byte @ 4 T$%" - !o$t%are Tra#
;ast u#dated ( <ri ,ec 3 06(16(1* M9T 1996
"ro rammin the 80c196 2.= <eneric ?um(s and calls

The conditional >um#s o$ the 80c196 are all relati&e >um#s using an 8-bit $ield %ithin the instruction stream to s#eci$y the destination address" The destination can thus be u# to 1)8 bytes be$ore the current address or u# to 1)6 bytes a$ter it" Ho%e&er2 the assembler $or the 80c196 $amily #ro&ides $or generic >um#s and calls %hich can >um# any%here in memory" <or all the conditional >um# instructions2 B can be substituted $or the @ and the assembler %ill generate a code se7uence %hich is logically e7ui&alent but can reach any%here in the memory" + @/ can only >um# about 1)8 locations $rom the current #rogram counterK a B/ can >um# any%here in memory" The algorithm used by the assembler to con&ert these generic instructions into actual machine instructions is sho%n belo%" -)am(le 6
8( J( J?( 0JMP myHla,el myHla,el K+4 myHla,el ; +ener!$ *orm: re#la$e ,y I ; !* myHla,el nearer t)an 128 ,ytes ; !* myHla,el nearer t)an 1& ,ytes ;
J?( 6JMP
K+5 myHla,el
; !* myHla,el *art)er t)an 1& ,ytes ;
In a li8e manner 2 a B$ %ill cause a *@M" or &@M" to be generated as a##ro#riate2 and a !%&& %ill cause a *!%&& or a &!%&& to be generated"
+ll rights reser&ed <or more in$ormation #lease contact ,aniel

Muller

The 80c196 Architecture

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The 80c196 Architecture

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The 80c196 architecture 1.

1 The 80c196 family

Intel 80c196 16-bit Microcontrollers