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International Journal of Engineering and Innovative Technology (IJEIT) Volume 2, Issue 10, April 2013

PIC Based Seven-Level Cascaded H-Bridge Multilevel Inverter

R.M.Sekar, Baladhandapani.R
Abstract- This paper presents a multilevel inverter topology in which a low switching frequency is made use taking up the advantages of the low frequency, such as low thermal stress and high conversion efficiency. Standard cascaded multilevel inverter requires n number of DC sources for 2n+1 levels. In actual practice to obtain seven- levels we need three Hbridges to be cascaded. Instead we make use of only two Hbridges in cascaded to derive seven- level output. This project proposes a reduced switch inverter topology which produces seven-level output. The inverter is operated under fundamental frequency switching strategy. The proposed topology provides high quality output power due to its high number of output levels, high conversion efficiency and low thermal stress. Keywords Inverter, multilevel inverter, fundamental frequency, hybrid cascaded multilevel inverter.

Fig. 1 Proposed Multilevel Inverter Topology

II. WORKING PRINCIPLE The block diagram depicting the working principle of the proposed topology is as given below in Fig.2.

I. INTRODUCTION The Multilevel inverter is a promising power electronics topology for high-power applications because of its low electromagnetic interference (EMI) and high efficiency with low-switching-frequency control method. Traditionally, each phase of a cascaded multilevel inverter requires n dc sources [1-5] for 2n + 1 levels. For many applications, obtaining so many separate dc sources may preclude the use of such an inverter. To reduce the number of dc sources required when the cascaded Hbridge multilevel inverter is applied to a motor drive, a scheme is proposed in this paper that allows the use of a single dc source (such as battery or fuel cell). Previous works has shown that Pulse Width Modulation (PWM) control can be used on HCMLI. Compared to the traditional cascaded H-bridge multilevel inverter, the proposed HCMLI has a low number of dc sources and retains the low switching-frequency advantage In a multilevel converter the output of each phase leg can attain more than two levels leading to improved quality of the output voltage and current. The circuit comprising each leg and its proper operation ensure that voltage blocked by the switches reduces as the number of levels is increased. In addition, multilevel converters are modular to some extent, thereby making it easy to scale voltage ratings by increasing the number of cells. There are three types of multilevel inverters used in general (1) diode-clamped inverter, (2) capacitor-clamped inverter, and (3) cascade inverter. The type of multilevel inverter made use here is cascaded.

Fig. 2 Block Diagram

The AC power supply is converted into DC power using any of the known bridge rectifier configurations. Two levels of DC voltages (say 24 Volts and 12 Volts) are obtained with proper arrangements. The DC voltages are given as input to the H-Bridge inverters designed using MOSFETs. These MOSFETs are driven by individual driver circuits. The required Gate pulses are given through the output port of the PIC controller. The two inverters are cascaded or connected in series to form the obtained arrangement. Driver performs the operations of Buffering, Isolation and Amplification. For buffering purpose ICs are incorporated. For amplification and isolation purposes, optocouplers are used. The cascaded inverter provides output voltages at different levels for the gate pulses given to the MOSFETs through the Microcontroller unit. The output voltage obtained from the cascaded inverter bridge is the summation of the output voltages of the different outputs of the inverters (say +V, 0, -V).

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International Journal of Engineering and Innovative Technology (IJEIT) Volume 2, Issue 10, April 2013 -V2 -V2 III. SWITCHING STRATEGY The fundamental frequency switching strategy is made use to get better results [6]. Another method of switching V2 -V1+V2 the inverter bridge is the PWM or Pulse Width Modulation technique. The Pulse Width Modulation -V1 0 -V1 technique is a high frequency switching method. In the fundamental frequency switching method, the frequency -V2 -V1-V2 of switching is 50 Hz or 60 Hz. Fundamental frequency switching technique is utilized in our thesis, and the phase angle being calculated using the formula, By choosing different combinations we can obtain Phase angle = / (360*f) different levels of outputs. The comparison of the Where: f= fundamental frequency multilevel outputs is given below. Table II represents how = angle different output voltage can be obtained by varying the The above equation is used to calculate the phase input voltages. Both input voltages maybe the same, or angle of the pulse generator. Instead of using any discrete different. The Table II gives output voltage when the two pulse generator circuits we use Microcontrollers to input voltages are different. Two combinations are taken. generate pulses for the inverter bridges. First one being one input voltage is half or 50% of the other input voltage. And the second combination being IV. OUTPUT VOLTAGE LEVELS the sum of the input voltages equals 100% of the input The output voltage of the entire arrangement is the voltage. The former combination gives us seven level summation of the output voltages of the individual output voltage, and the latter provides nine level output inverter bridges. The output voltages of an inverter bridge voltage Thus the theoretical analysis shows modified usage of the inverter bridges for 2n+1 levels employing are +V, 0 and V. The outputs of the bridge H1 are + V1, 0 less than n number of bridges. and V1. The outputs of the bridge H2 are +V2, 0 and Table II Different Voltage Level Combinations of the V2. For better understanding let us assume V1 = Vdc, V2 = Proposed Level Multilevel Inverter Vc and Vc = Vdc /2. The expected output voltages for the proposed topology is 3 Vdc /2, Vdc, Vdc /2, 0, -Vdc /2, -Vdc , V1+V2 3 Vdc /2. V. THEORETICAL ANALYSIS By opening and closing the switches of inverter bridge H1 appropriately, the output voltage v1 can be made equal to Vdc, 0, or Vdc, while similarly the output voltage of inverter bridge H2 can be made equal to Vc, 0, or Vc by opening and closing its switches appropriately. Therefore, the output voltage of the inverter can have the values (Vdc + Vc ), Vdc, ( Vdc Vc ), Vc, 0, Vc , (Vdc Vc ), Vdc, and (Vdc + Vc ), which constitute nine possible output levels. The given table I represents the different output voltages as the sum of the different possible voltages.
Table I Different Voltage Levels Of the Proposed Multilevel Inverter V1 V2 V1+V2 V2 V1 0 -V2 V2 0 0 0 V1+V2 V2 V1 -V1 V1-V2 -V2 V2 -V1-V2 - 3 Vdc /2 0 -V1 - Vdc -V1+V2 - Vdc /2 V1 V2 V1+V2 (V1= Vdc V2= Vdc /2) V2 V1 0 -V2 V2 0 0 -V2 V1+V2 V1 V1-V2 V2 0 -V2 3 Vdc /2 Vdc Vdc /2 Vdc /2 0 - Vdc /2

The comparison is given for both seven level and nine level output levels, for the same topology of the multilevel inverter. The possibilities of the different output voltage levels are given. The variation is due to the

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International Journal of Engineering and Innovative Technology (IJEIT) Volume 2, Issue 10, April 2013 Table III Different Voltage Levels of the Seven Levels change in the input voltages of the inverter bridges H1 Multilevel Inverter with Different Modes and H2 being V1 and V2 respectively. When V1 and V2 are equal then it results in a five level inverter. With a V1+V2 condition such that V1= Vdc and V2= Vdc /2, the resulting output voltage is of seven levels. To obtain nine level output voltage, we consider V1 and V2 not to be equal (V1= Vdc V1 V2 V1+V2 MODE and also a condition different from that for the seven level voltage is to be considered. Hence we opt for a condition V2= Vdc /2) that V1=0.6V and V2=0.4V. The table given below is a simplified representation of the previous table, V2 V1+V2 3 Vdc /2 1 considering the seven level output alone. For ease of calculation of the phase delay and other considerations, V1 0 V1 Vdc 2 we can now divide the above said seven levels into different modes. In general, an AC voltage follows a sine wave pattern, i.e., starts from zero when t=0, then follows -V2 V1-V2 Vdc /2 3 the positive half cycle thus attaining the peak value and decreases to zero, completing the positive half cycle. V2 V2 Vdc /2 3 Similarly once it reaches zero, it starts increasing, but in the negative side, hence completion of the negative half 0 0 0 0 4 cycle occurs. The same pattern is considered to differentiate the modes of output voltages. The modes of -V2 -V2 - Vdc /2 5 operation starts with the output voltages of both the inverter bridges equals zero. Thus the order of output voltage is given as 0, Vdc /2, Vdc, 3 Vdc /2, Vdc, Vdc /2, 0 for V2 -V1+V2 - Vdc /2 5 positive half cycle. Similarly for the negative half cycle the voltages follows the sequence as 0, - Vdc /2, - Vdc, -3 -V1 0 -V1 - Vdc 6 Vdc /2, - Vdc, - Vdc /2, 0. As mentioned, the entire operation is divided into 7 modes. The modes are arranged as -V2 -V1-V2 - 3 Vdc /2 7 shown in the table given below according to the combination of the input voltages. The output voltage is said to be starting from 0v, so the first mode being mode 5. For positive half cycle of output the sequence being 54-3-2-1-2-3-4-5 and that for negative half cycle being 56-7-8-9-8-7-6-5. For ease of calculation of the phase delay and other considerations, we can now divide the above said seven levels into different modes. In general, an AC voltage follows a sine wave pattern, i.e., starts from zero when t=0, then follows the positive half cycle thus attaining the peak value and decreases to zero, completing the positive half cycle. Similarly once it reaches zero, it starts increasing, but in the negative side, hence completion of the negative half cycle occurs. The same pattern is considered to differentiate the modes of output voltages. The modes of operation starts with the Fig.3 Typical Output Voltages output voltages of both the inverter bridges equals zero. Thus the order of output voltage is given as 0, Vdc /2, Vdc, 3 Vdc /2, Vdc, Vdc /2, 0 for positive half cycle. Similarly for the negative half cycle the voltages follows the sequence as 0, - Vdc /2, - Vdc, -3 Vdc /2, - Vdc, - Vdc /2, 0. Thus, as said above, the transition of output voltages would start from zero voltage, i.e., mode 5. Hence we can now define the positive and negative half cycle voltage transitions of the seven level output voltages through the modes declared above. For the positive cycle voltages, the modes followed are 4, 3, 2, 1, 2, 3, 4. Similarly the modes followed for the negative cycle is given by the following sequence 4, 5, 6, 7, 6, 5, 4. The table given below shows the different conducting modes with the Fig.4 Typical Output Voltages with different modes conduction period for each mode.

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International Journal of Engineering and Innovative Technology (IJEIT) Volume 2, Issue 10, April 2013 VI. SWITCHING PATTERN AND PHASE DELAY The switching pattern evaluation is an important step in the implementation of the proposed inverter configuration either through hardware or simulation. Here the switching frequency considered for calculation of the phase delay is the fundamental frequency namely 50Hz. Both the inverter bridges are considered for the evaluation purposes. The entire waveform is analysed in detail with the help of the modes of operation, the inverter output voltages. The typical voltage waveform is taken into Fig.6 H2 Bridge Output Waveform consideration and compared with the output of individual bridges. The inverter bridges are similar in operation, the only difference being the voltage level namely Vdc and Vdc/2. Considering the output voltage of an individual inverter as V, we can conclude that the switches s1, s4 accounts for the positive voltage and for the negative voltage the switches responsible being s2,s3.
Table IV Switching Strategy for the Overall Bridge Configuration INVERTE R SWITCHES ON OUTPUT VOLTAGE 0 +Vdc -Vdc 0 +Vdc/2 -Vdc/2 Fig.7 Seven Level Output Voltage Waveform

0 H1 1 2 0 H2 5 6

0 4 3 0 8 7

VII. SIMULATION RESULTS Simulation of the proposed topology of multilevel inverter is performed using matlab. The output waveforms of H1 inverter bridge, H2 Inverter Bridge and the overall output of cascaded multilevel inverter are given.

Fig.8 Seven Level Output Current Waveform

VIII. CONCLUSION This paper proposes a Cascaded Multilevel Inverter that uses reduced number of bridges and hence reduced power source while producing desired multilevel voltage. A fundamental frequency switching control algorithm was developed. Simulation using MATLAB software was performed to show the proposed methodology. The fundamental frequency considered as 50 Hertz and the simulation was successfully completed. REFERENCES
[1] L. M. Tolbert, F. Z. Peng, T. G. Habetler, Multilevel converters for large electric drives, IEEE Transactions on Industry Applications, vol.35, no. 1, Jan./Feb. 1999, pp. 36-44. [2] J. S. Lai and F. Z. Peng, Multilevel converters A new breed of power converters, IEEE Transactions on Industry Applications, vol. 32, no.3, May. /June 1996, pp. 509-517.

Fig.5 H1 Bridge Output Waveform

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International Journal of Engineering and Innovative Technology (IJEIT) Volume 2, Issue 10, April 2013
[3] J. Rodrguez, J. Lai, and F. Peng, Multilevel inverters: a survey of topologies, controls and applications, IEEE Transactions on Industry Applications, vol. 49, no. 4, Aug. 2002, pp. 724-738 [4] S. Khomfoi, L. M. Tolbert, Multilevel Power Converters, Power Electronics Handbook, 2nd Edition Elsevier, 2007, ISBN 978-0-12-088479-7, Chapter 17, pp. 451-482. [5] J. Liao, K. Corzine, M. Ferdowsi, A new control method for single-DCsource cascaded H-Bridge multilevel converters using phase-shift modulation, IEEE Applied Power Electronics Conference and Exposition, Feb. 2008, pp.886-890. [6] Zhong Du, Leon M. Tolbert, Burak Ozpineci,and John N. Chiasson, Fundamental Frequency Switching Strategies of a Seven-Level Hybrid Cascaded H-Bridge Multilevel Inverter IEEE Transactions On Power Electronics, vol. 24, no. 1, Jan 2009 [7] Haiwen Liu, Leon M. Tolbert , Burak Ozpineci, Zhong Du Comparison of Fundamental Frequency and PWM Methods applied on a Hybrid Cascaded Multilevel Inverter [8] J.Laio, K.Corzine, M.Ferdowsi, A New control method for single DC source cascaded H-Bridge multilevel converters using phase-shift modulation, IEEE Applied Power Electronics Conference and Exposition, Feb. 2008, pp 886-890.

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