IT2354 EMBEDDED SYSTEMS

UNIT-I

UNIT-I EMBEDDED COMPUTING Challenges of Embedded Systems Embedded system design process. Embedded processors 8051 Microcontroller, ARM processor Architecture, Instruction sets and programming. INTRODUCTION Embedded system: An embedded system is a special-purpose computer system designed to perform a dedicated function Unlike a general-purpose computer, such as a personal computer, an embedded system performs one or a few pre-defined tasks, usually with very specific requirements, and often includes task-specific hardware and mechanical parts not usually found in a general-purpose computer. Embedded computer System: Any device that includes a programmable computer but is not itself intended to be a general-purpose computer is called embedded computer system. Embedding Computers Computers have been embedded into applications since the earliest days of computing.Eg) Whirlwind. a computer designed at MIT in the late 1940s and early 1950s. Whirlwind was also the first computer designed to support real-time operation and was originally conceived as a mechanism for controlling an aircraft simulator. Microprocessor: A microprocessor is a single-chip CPU. The first microprocessor, the Intel 4004, was designed for an embedded application, namely, a calculator. Microprocessors come in many different levels of sophistication; they are usually classified by their word size. Microprocessors execute programs very efficiently. An 8-bit microcontroller is designed for low-cost applications and includes on-board memory and I/O devices; A 16-bit microcontroller is often used for more sophisticated applications that may require either longer word lengths or off-chip I/O and memory; A 32-bit RISC microprocessor offers very high performance for computation-intensive applications.
DEPARTMENT OF IT/SVSCE 1

IT2354 EMBEDDED SYSTEMS

UNIT-I

Why use microprocessors? Microprocessors are a very efficient way to implement digital systems. Microprocessors make it easier to design families of products that can be built to provide various feature sets at different price points and can be extended to provide new features to keep up with rapidly changing markets.

Characteristics of Embedded Computing Applications Embedded computing is in many ways much more demanding than the sort of programs that you may have written for PCs or workstations. On the one hand, embedded computing systems have to provide sophisticated functionality: Complex algorithms: The operations performed by the microprocessor may be very sophisticated. For example, the microprocessor that controls an automobile engine must perform complicated filtering functions to optimize the performance of the car while minimizing pollution and fuel utilization. User interface: Microprocessors are frequently used to control complex user interfaces that may include multiple menus and many options. The moving maps in Global Positioning System (GPS) navigation are good examples of sophisticated user interfaces.

Deadlines involve: Real time: Many embedded computing systems have to perform in real time if the data is not ready by a certain deadline, the system breaks. In some cases, failure to meet a deadline is unsafe and can even endanger lives. In other cases, missing a deadline does not create safety problems but does create unhappy customersmissed deadlines in printers, can result in scrambled pages. Multirate: Many embedded computing systems have several real-time activities going on at the same time. They may simultaneously control some operations that run at slow rates and others that run at high rates. Multimedia applications are prime examples of multirate behavior. The audio and video portions of a multimedia stream run at very different rates, but they must remain closely synchronized. Costs of various sorts are also very important: Manufacturing cost: The total cost of building the system is very important in many cases. Manufacturing cost is determined by many factors, including the type of microprocessor used, the amount of memory required, and the types of I/O devices.
DEPARTMENT OF IT/SVSCE 2

IT2354 EMBEDDED SYSTEMS

UNIT-I

Power and energy: Power consumption directly affects the cost of the hardware, since a larger power supply may be necessary. Energy consumption affects battery life, which is important in many applications,as well as heat consumption, which can be important even in desktop applications.

CHALLENGES IN EMBEDDED COMPUTING SYSTEM DESIGN The following external constraints are one important source of difficulty in embedded system Design.

How much hardware do we need?

We have a great deal of control over the amount of computing power we apply to our problem. We cannot only select the type of microprocessor used, but also select the amount of memory, the peripheral devices, and more. If too little hardware and the system fails to meet its deadlines, too much hardware and it becomes too expensive. How do we meet deadlines? It is entirely possible that increasing the CPU clock rate may not make enough difference to execution time, since the programs speed may be limited by the memory system. How do we minimize power consumption? In battery-powered applications, power consumption is extremely important. Even in non- battery applications, excessive power consumption can increase heat dissipation. One way to make a digital system consume less power is to make it run more slowly, but naively slowing down the system can obviously lead to missed deadlines. How do we design for upgradability? The hardware platform may be used over several product generations or for several different versions of a product in the same generation, with few or no changes. Does it really work? Reliability is always important when selling productscustomers rightly expect that products they buy will work. The sources that make the design so difficult are: Complex testing: Exercising an embedded system is generally more difficult than typing in some data. The timing of data is often important, meaning that we cannot separate the testing of an embedded computer from the machine in which it is embedded.
DEPARTMENT OF IT/SVSCE 3

IT2354 EMBEDDED SYSTEMS

UNIT-I

Limited observability and controllability: Embedded computing systems usually do not come with keyboards and screens. This makes it more difficult to see what is going on and to affect the systems operation. We may be forced to watch the values of electrical signals on the microprocessor bus, for example, to know what is going on inside the system. Moreover, in realtime applications we may not be able to easily stop the system to see what is going on inside. Restricted development environments: The development environments for embedded systems (the tools used to develop software and hardware) are often much more limited than those available for PCs and workstations.

THE EMBEDDED SYSTEM DESIGN PROCESS

Overview of the embedded system design process aimed at two objectives. First,it will give us an introduction to the various steps in embedded system design before we delve into them in more detail. Second, it will allow us to consider the design methodology itself.Figure 1.1 summarizes the major steps in the embedded system design process.In this topdown view,we start with the system requirements in the next step comes Specification.

Fig 1.1Embedded system design process Topdown Designwe will begin with the most abstract description of the system and conclude with concrete details. The alternative is a bottomup view in which we start with components to build a system. Bottomup design steps are shown in the figure as dashed-line
DEPARTMENT OF IT/SVSCE 4

IT2354 EMBEDDED SYSTEMS

UNIT-I

arrows. We need bottomup design because we do not have perfect insight into how later stages of the design process will turn out. During the design process we have to consider the major goals of the design such as manufacturing cost; performance (both overall speed and deadlines); and power consumption. Design steps are detailed below:

A.Requirements:
Requirements may be functional or nonfunctional. We must capture the basic functions of the embedded system, but functional description is often not sufficient. Typical nonfunctional requirements include: 1. Performance: The speed of the system is often a major consideration both for the usability of the system and for its ultimate cost. Performance may be a combination of soft performance metrics such as approximate time to perform a user-level function and hard deadlines by which a particular operation must be completed. 2. Cost: The target cost or purchase price for the system is almost always a consideration. Cost typically has two major components: o Manufacturing cost includes the cost of components and assembly; o NonRecurring engineering (NRE) costs include the personnel and other costs of designing the system. 3. Physical size and weight: The physical aspects of the final system can vary greatly depending upon the application. e.g) An industrial control system for an assembly line may be designed to fit into a standard-size rack with no strict limitations on weight. But a handheld device typically has tight requirements on both size and weight that can ripple through the entire system design. 4. Power consumption: Power, of course, is important in battery-powered systems and is often important in other applications as well. Power can be specified in the requirements stage in terms of battery life. mock-up. The mock-up may use canned data to simulate functionality in a restricted demonstration, and it may be executed on a PC or a workstation. But it should give the
DEPARTMENT OF IT/SVSCE 5

IT2354 EMBEDDED SYSTEMS

UNIT-I

customer a good idea of how the system will be used and how the user can react to it. Physical,nonfunctional models of devices can also give customers a better idea of characteristics such as size and weight. e.g) Requirements analysis of a GPS moving map The moving map is a handheld device that displays for the user a map of the terrain around the users current position; the map display changes as the user and the map device change position. The moving map obtains its position from the GPS, a satellite-based navigation system.

The moving map display might look something like the following figure

Fig.1.2 G.P.S Moving map Functionality: This system is designed for highway driving and similar uses, not nautical or aviation uses that require more specialized databases and functions. The system should show major roads and other landmarks available in standard topographic databases. User interface: The screen should have at least 400_600 pixel resolution. The device should be controlled by no more than three buttons. Performance: The map should scroll smoothly. Upon power-up, a display should take no more than one second to appear, and the system should be able to verify its position and display the current map within 15 s. Cost: The selling cost (street price) of the unit should be no more than $100. Physical size and weight: The device should fit comfortably in the palm of the hand. Power consumption: The device should run for at least eight hours on four AA batteries.

DEPARTMENT OF IT/SVSCE

IT2354 EMBEDDED SYSTEMS

UNIT-I

Fig.1.3Requirements form for GPS Moving map B.Specification The specification is more preciseit serves as the contract between the customer and the architects. The specification should be understandable enough so that someone can verify that it meets system requirements and overall expectations of the customer. It should also be unambiguous. the specification must be carefully written so that it accurately reflects the customers requirements and does so in a way that can be clearly followed during design. A specification of the GPS system would include several components: Data received from the GPS satellite constellation. Map Data User Interface

Operations that must be performed to satisfy customer requests. Background actions required to keep the system running, such as operating the GPS receiver. UML, a language for describing specifications C.Architecture Design The specification does not say how the system does things, only what the system does. Describing how the system implements those functions is the purpose of the architecture. Figure 1.3 shows a sample system architecture in the form of a block diagram that shows major operations and data flows among them.

DEPARTMENT OF IT/SVSCE

IT2354 EMBEDDED SYSTEMS

UNIT-I

Fig 1.3:Block diagram of the moving map

Many implementation details should we refine that system block diagram into two block diagrams: one for hardware and another for software. These two more refined block diagrams are shown in Figure 1.4.The hardware block diagram clearly shows that we have one central CPU surrounded by memory and I/O devices. In particular, we have chosen to use two memories: a frame buffer for the pixels to be displayed and a separate program/data memory for general use by the CPU .

Fig 1.4:Hardware design

Fig 1.5:Software design

D. Designing Hardware and Software Components The component design effort builds those components in conformance to the architecture and specification. The components will in general include both hardwareFPGAs, boards, and so onand software modules. Some of the components will be ready-made. In the moving map, the GPS receiver is a good example of a specialized component that will nonetheless be a predesigned, standard component. We can also make use of standard software modules. One good example is the topographic database.

DEPARTMENT OF IT/SVSCE

IT2354 EMBEDDED SYSTEMS

UNIT-I

E. System Integration The components built are put together and see how the system works. If we debug only a few modules at a time, we are more likely to uncover the simple bugs and able to easily recognize them. Only by fixing the simple bugs early will we be able to uncover the more complex or obscure bugs.

EMBEDDED PROCESSORS
Embedded processors can be broken into two broad categories: ordinary microprocessors (P) and microcontrollers (C), which have many more peripherals on chip, reducing cost and size. Contrasting to the personal computer and server markets, a fairly large number of basic CPU architectures are used; there are Von Neumann as well as various degrees of Harvard architectures, RISC as well as non-RISC and VLIW; word lengths vary from 4-bit to 64-bits and beyond (mainly in DSP processors) although the most typical remain 8/16-bit. Most architecture comes in a large number of different variants and shapes, many of which are also manufactured by several different companies. e.g ARM

8051 MICROCONTROLLER
8051 is an excellent device for building many embedded systems. One important factor is that the 8051 requires a minimum number of external components in order to operate. It is a well-tested design; introduced in its original form by Intel in 1980 the development costs of this device now start at less than US $1.00. At this price, you get a performance of around 1 million instructions per second, and 256 bytes (not megabytes!) of on-chip RAM, 32 port pins and a serial interface.

Features of 8051:
The main features of 8051 microcontroller are: RAM 128 Bytes (Data memory) ROM 4Kbytes . Serial Port Using UART makes it simpler to interface for serial communication. Two 16 bit Timer/ Counter, Input/output Pins 4 Ports of 8 bits each on a single chip. 6 Interrupt Sources 8 bit ALU (Arithmetic Logic Unit)
9

DEPARTMENT OF IT/SVSCE

IT2354 EMBEDDED SYSTEMS

UNIT-I

Harvard Memory Architecture It has 16 bit Address bus (each of RAM and ROM) and 8 bit Data Bus.

8051 can execute 1 million one-cycle instructions per second with a clock frequency of 12MHz. This microcontroller is also called as System on a chip because it has all the features on

a single chip. The Block Diagram of 8051 Microcontroller is as shown in Figure

8051 Microcontroller Block diagram

Pin configuration of 8051

The following is the Pin diagram of 8051 microcontroller.

DEPARTMENT OF IT/SVSCE

10

IT2354 EMBEDDED SYSTEMS

UNIT-I

A) BASIC PINS PIN 9: PIN 9 is the reset pin which is used to reset the microcontrollers internal registers and ports upon starting up. (Pin should be held high for 2 machine cycles.) PINS 18 & 19: The 8051 has a built-in oscillator amplifier hence we need to only connect a crystal at these pins to provide clock pulses to the circuit. PIN 40 and 20: Pins 40 and 20 are VCC and ground respectively. The 8051 chip needs +5V 500mA to function properly, although there are lower powered versions like the Atmel 2051 which is a scaled down version of the 8051 which runs on +3V. PINS 29, 30 & 31: As described in the features of the 8051, this chip contains a built-in flash memory. In order to program this we need to supply a voltage of +12V at pin 31. If external memory is connected then PIN 31, also called EA/VPP, should be connected to ground to indicate the presence of external memory. PIN 30 is called ALE (address latch enable), which is used when multiple memory chips are connected to the controller and only one of them needs to be selected. PIN 29 is called PSEN. This is "program store enable". In order to use the external memory it is required to provide the low voltage (0) on both PSEN and EA pins. B) PORTS There are 4 8-bit ports: P0, P1, P2 and P3. PORT P1 (Pins 1 to 8): The port P1 is a general purpose input/output port which can be used for a variety of interfacing tasks. The other ports P0, P2 and P3 have dual roles or additional functions associated with them based upon the context of their usage. PORT P3 (Pins 10 to 17): PORT P3 acts as a normal IO port, but Port P3 has additional functions such as, serial transmit and receive pins, 2 external interrupt pins, 2 external counter inputs, read and write pins for memory access. PORT P2 (pins 21 to 28): PORT P2 can also be used as a general purpose 8 bit port when no external memory is present, but if external memory access is required then PORT P2 will act as an address bus in conjunction with PORT P0 to access external memory. PORT P2 acts as A8A15, as can be seen from fig 1.1 PORT P0 (pins 32 to 39) PORT P0 can be used as a general purpose 8 bit port when no external memory is present, but if external memory access is required then PORT P0 acts as multiplexed
DEPARTMENT OF IT/SVSCE 11

IT2354 EMBEDDED SYSTEMS

UNIT-I

address and data bus that can be used to access external memory in conjunction with PORT P2. P0 acts as AD0-AD7. C) OSCILLATOR CIRCUITS The 8051 requires the existence of an external oscillator circuit. The oscillator circuit usually runs around 12MHz, although the 8051 (depending on which specific model) is capable of running at a maximum of 40MHz. Each machine cycle in the 8051 is 12 clock cycles, giving an effective cycle rate at 1MHz (for a 12MHz clock) to 3.33MHz (for the maximum 40MHz clock). The oscillator circuit generates the clock pulses so that all internal operations are synchronized.

The external interface of the Standard 8051

Small 8051

Low-cost members of the 8051 family with reduced number of port pins, and no support for offchip memory. Typical application: Low-cost consumer goods. Standard 8051: The Small 8051s and the Extended 8051s are derived Extended 8051:Members of the 8051 family with extended range of no-chip facilities (e.g. CAN controllers, ADC, DAC,etc), large numbers of port pins, and - in recent

devices - support for large amounts of off-chip memory. Typical applications: Industrial and automotive systems.

Reset requirements
Reset routine must be run to place hardware into an appropriate state before it can begin executing the user program. Running this reset routine takes time, and requires that the microcontrollers oscillator is operating. Where system is supplied by a robust power supply, which rapidly reaches its specified output voltage when switched on, rapidly decreases to 0V when switched off, and while switched on cannot brown out (drop in voltage), then we can safely use low-cost reset hardware based on a capacitor and a resistor to ensure that system will be reset correctly: this form of reset circuit is shown in Figure

DEPARTMENT OF IT/SVSCE

12

IT2354 EMBEDDED SYSTEMS

UNIT-I

Figure:Reset requirements

Clock frequency and performance

All digital computer systems are driven by some form of oscillator circuit: the 8051 is certainly no exception. If the oscillator fails, the system will not function at all; if the oscillator runs irregularly, any timing calculations performed by the system will be inaccurate.

Fig: Clock frequency and performance

Memory Issues A.
Types of memory

Dynamic RAM (DRAM) Static RAM (SRAM) Mask Read-Only Memory (ROM) Programmable Read-Only Memory (PROM) UV Erasable Programmable Read-Only Memory (UV EPROM) EEPROM and Flash ROM

DEPARTMENT OF IT/SVSCE

13

IT2354 EMBEDDED SYSTEMS Dynamic RAM Vs Static RAM

UNIT-I

Dynamic RAM Dynamic RAM is a read-write memory technology that uses a small capacitor to store information. It must be frequently refreshed to maintain the required information Less complex and least cost

Static RAM Static RAM is a read-write memory technology that uses a form of electronic flip-flop to store the information No refreshing is required

More complex and costs can be several times that of the corresponding size of DRAM Access time is large compared to Access times may be one-third those of SRAM
Mask Read-Only Memory (ROM):

DRAM

Mask ROM is from the software developers perspective read only; A mask is provided by the company for which the chips are being produced. Such devices are therefore sometimes referred to as factory programmed.
Programmable Read-Only Memory (PROM)

PROM is a form of Write-Once, Read-Many (WORM) or One-Time Programmable (OTP) memory. Basically, we use a PROM programmer to blow tiny fuses in the device. UV Erasable Programmable Read-Only Memory (UV EPROM) : UV EPROMs are programmed electrically. Unlike PROMs, they also have a quartz window which allows the memory to be erased by exposing the internals of the device to UV light.
EEPROM and Flash ROM

Electrically-Erasable Programmable Read-Only Memory (EEPROMs) and Flash ROMs are a more user-friendly form of ROM that can be both programmed and erased electrically. EEPROM and Flash ROM are very similar. EEPROMs can usually be reprogrammed on a byte-by-byte basis, and are often used to store passwords or other persistent user data. Flash ROMs generally require a block-sized erase operation before they can be programmed.

DEPARTMENT OF IT/SVSCE

14

IT2354 EMBEDDED SYSTEMS

UNIT-I

b) Memory organization and hex

All data items are represented in computer memory as binary codes, each containing a certain number of bits. To simplify the storage and retrieval of data items, these memory bits are organized into memory locations, each with a unique memory address. The other Memory representations are shown

Fig: Memory Organization and Hex representation

C) The 8051 memory architecture

There are two distinct memory regions in an 8051 device: the DATA area and the CODE area. DATA memory : DATA memory is used to store variables and the program stack while the program is running. The DATA area will be implemented using some form of RAM. Most of the DATA area has a byte-oriented memory organization. However, within the DATA area is a 16-byte BDATA area which can also be accessed using bit addresses.

The compiler avoids confusion if 0x24 in bit address and byte address. CODE memory :CODE area is used to store the program code, usually in some form of ROM. The CODE area may also contain read-only variables (constants), such as filter co-efficients or data for speech playback.

D) 8-bit family, 16-bit address space

An 8-bit microcontroller refers to the size of the registers and data bus. This means that the family will handle 8-bit data very quickly and process 16-bit or 32-bit data rather less
DEPARTMENT OF IT/SVSCE 15

IT2354 EMBEDDED SYSTEMS

UNIT-I

efficiently. The 16-bit address space means that the device can directly address 216 bytes of memory: that is, 64 kbytes. E) I/O pins Most 8051s have four 8-bit ports, giving a total of 32 pins you can individually read from or control. All of the ports are bidirectional: that is, they may be used for both input and output F) Timers All members of the 8051 family have at least two timer/counters, known as Timer 0 and Timer 1: most also have an additional timer (Timer 2). These are 16-bit timers, they can hold values from 0 to 65535 (decimal).There are many things we can do with such a timer: It used to measure intervals of time. It can measure the duration of a function by noting the value of a timer at the beginning and end of the function call, and comparing the two results. Use it to generate precise hardware delays. Use it to generate time out facilities: this is a key requirement in systems with real-time constraints. Most important of all, we can use it to generate regular ticks, and drive an operating system G. Interrupts An interrupt is a hardware mechanism used to notify a processor that an event has taken place: such events may be internal events (such as the overflow of a timer) or external events (such as the arrival of a character through a serial interface).The original 8051 (8052) architecture supported seven interrupt sources: Two or three timer/counter interrupts Two UART-related Two external interrupts The power-on reset (POR) interrupt. In Figure

the system executes two (background) functions, Function 1 and Function 2 . During the execution of Function 1, an interrupt is raised, and an interrupt service routine (ISR1) deals with this event. After the execution of ISR1 is complete, Function 1
DEPARTMENT OF IT/SVSCE 16

IT2354 EMBEDDED SYSTEMS

UNIT-I

resumes its operation. During the execution of Function 2, another interrupt is raised, this time dealt with by ISR2.

H. Serial interface Such an interface is common in embedded processors, and is widely used. Here are some examples: The serial port may be used to debug embedded applications, using a desktop PC. The serial port may be used to load code into flash memory for in circuit programming The serial port may be used to transfer data from embedded data acquisition systems to a PC, or to other embedded processors I .Power consumption All modern implementations of 8051 processors have at least three operating modes: Normal mode. Idle Mode. Power-Down Mode.

The Idle and Power Down modes are intended to be used to save power at times when no processing is required .We generally aim for an average power consumption of less than 10 mA. Idle mode: In the idle mode the oscillator of the C501 continues to run, but the CPU is gated off from the clock signal. Rhe interrupt system, the serial port and all timers are connected to the clock. The idle mode is entered by setting the flag bit IDLE (PCON.0). The easiest way is: PCON |= 0x01; // Enter idle mode There are two ways as activating any enabled interrupt and Perform a hardware reset. Power-down mode: The power-down mode is entered by setting the flag bit PDE (PCON.1). This is done in C as follows: PCON |= 0x02; // Enter power-down mode The only exit from power-down mode is a hardware reset.

DEPARTMENT OF IT/SVSCE

17

IT2354 EMBEDDED SYSTEMS

UNIT-I

ARM PROCESSOR
The ARM processor is widely used in cell phones and many other systems. INTRODUCTION: complex instruction set computers (CISC).

These machines provided a variety of instructions that may perform very complex tasks, such as string searching; they also generally used a number of different instruction formats of varying lengths. Reduced instruction set computers (RISC)

These computers tended to provide somewhat fewer and simpler instructions it. Streaming data.

Data sets that arrive continuously and periodically are called Streaming data. Assembly language: One instruction appears per line. Labels, which give names to memory locations, start in the first column. Instructions must start in the second column or after to distinguish them from labels. Comments run from some designated comment character (; in the case of ARM) to the end of the line Assemblers must also provide some pseudo-ops to help programmers create complete assembly language programs.An example of a pseudo-op is one that allows data values to be loaded into memory locations.These allow constants,for example, to be set into memory. TheARM % pseudo-op allocates a block of memory of the size specified by the operand and initializes locations to zero. e.g) label1 ADR r4,c LDR r0,[r4] ; a comment ADR r4,d LDR r1,[r4] SUB r0,r0,r1 ; another comment

Assembly language has the following features:

DEPARTMENT OF IT/SVSCE

18

IT2354 EMBEDDED SYSTEMS

UNIT-I

ARM PROCESSOR: ARM is actually a family of RISC architectures that have been developed over many years. ARM does not manufacture its own VLSI devices; rather, it licenses its architecture to companies who either manufacture the CPU itself or integrate the ARM processor into a larger system. The textual description of instructions, as opposed to their binary representation, is called an assembly language. ARM instructions are written one per line, starting after the first column. Comments begin with a semicolon and continue to the end of the line. A label, which gives a name to a memory location, comes at the beginning of the line, starting in the first column
e.g) LDR r0,[r8]; a comment label ADD r4,r0,r1 1. Processor and Memory Organization

TheARM architecture supports two basic types of data: The standardARM word is 32 bits long. The word may be divided into four 8-bit bytes ARM7 allows addresses up to 32 bits long.An address refers to a byte,not a word.Therefore, the word 0 in the ARM address space is at location 0, the word 1 is at 4, the word 2 is at 8,and so on.

The ARM processor can be configured at power-up to address the bytes in a word in either little-endian mode (with the lowest-order byte residing in the low-order bits of the word) big-endian mode (the lowest-order byte stored in the highest bits of the word),

Fig: Byte organizations within an ARM word.

DEPARTMENT OF IT/SVSCE

19

IT2354 EMBEDDED SYSTEMS

UNIT-I

Data Operations: Arithmetic and logical operations in C are performed in variables. Variables are implemented as memory locations. Sample fragment of C code with data declarations and several assignment statements. The variables a, b, c, x, y, and z all become data locations in memory. In most cases data are kept relatively separate from instructions in the programs memory image. In the ARM processor, arithmetic and logical operations cannot be performed directly on memory locations. While some processors allow such operations to directly reference main memory, ARM is a load-store architecturedata operands must first be loaded into the CPU and then stored back to main memory to save the results.
e.g)C Fragment code

int a, b, c, x, y, z; x_(a_b)_c; y_a*(b_c); z_(a << 2) | (b & 15);

Following Fig shows the registers in the basic ARM programming model. ARM has 16 generalpurpose registers, r0 through r15. Except for r15, they are identicalany operation that can be done on one of them can be done on the other one also. The r15 register has the same capabilities as the other registers, but it is also used as the program counter

The other important basic register in the programming model is the current program status register (CPSR). This register is set automatically during every arithmetic, logical, or shifting operation. The top four bits of the CPSR hold the following useful information about the results of that arithmetic/logical operation: The negative (N) bit is set when the result is negative in twos-complement arithmetic.
DEPARTMENT OF IT/SVSCE 20

IT2354 EMBEDDED SYSTEMS

UNIT-I

The zero (Z) bit is set when every bit of the result is zero. The carry (C) bit is set when there is a carry out of the operation. The overflow(V) bit is set when an arithmetic operation results in an overflow.

Instruction Sets in ARM

Following figure summarizes the ARM move instructions. The instruction MOV r0, r1 sets the value of r0 to the current value of r1. The MVN instruction complements the operand bits (ones complement) during the move.

Fig: ARM data Instructions

LDRB and STRB load and store bytes rather than whole words,while LDRH and SDRH operate on half-words and LDRSH extends the sign bit on loading. An ARM address may be 32 bits long. .The ARM load and store instructions do not directly refer to main memory addresses, since a 32-bit address would not fit into an instruction that included an opcode and operands. Instead, the ARM uses register-indirect addressing.

DEPARTMENT OF IT/SVSCE

21

IT2354 EMBEDDED SYSTEMS

UNIT-I

C assignments in ARM instructions We will use the assignments of Figure 2.7. The semicolon (;) begins a comment after an instruction, which continues to the end of that line. The statement x = (a +b) _ c; can be implemented by using r0 for a, r1 for b, r2 for c, and r3 for x . We also need registers for indirect addressing. In this case, we will reuse the same indirect addressing register, r4, for each variable load. The code must load the values of a, b, and c into these registers before performing the arithmetic, and it must store the value of x back to memory when it is done. This code performs the following necessary steps: ADR r4,a ; get address for a LDR r0,[r4] ; get value of a ADR r4,b ; get address for b, reusing r4 LDR r1,[r4] ; load value of b ADD r3,r0,r1 ; set intermediate result for x to a + b ADR r4,c ; get address for c LDR r2,[r4] ; get value of c SUB r3,r3,r2 ; complete computation of x ADR r4,x ; get address for x STR r3,[r4] ; store x at proper location

Flow of Control The B (branch) instruction is the basic mechanism inARM for changing the flow of control. The address that is the destination of the branch is often called the branch target. Branches are PC-relativethe branch specifies the offset from the current PC value to the branch target. The offset is in words, but because the ARM is byteaddressable, the offset is multiplied by four (shifted left two bits, actually) to form a byte address. Thus, the instruction B #100 will add 400 to the current PC value.

DEPARTMENT OF IT/SVSCE

22

IT2354 EMBEDDED SYSTEMS

UNIT-I

Implementing an if statement in ARM

We will use the following if statement as an example: if (a < b) { x = 5; y = c + d; } else x = c d; The implementation uses two blocks of code, one for the true case and another for the false case. A branch may either fall through to the true case or branch to the false case: ; compute and test the condition ADR r4,a ; get address for a LDR r0,[r4] ; get value of a ADR r4,b ; get address for b LDR r1,[r4] ; get value of b CMP r0, r1 ; compare a < b BGE fblock ; if a >= b, take branch ; the true block follows MOV r0,#5 ; generate value for x ADR r4,x ; get address for x STR r0,[r4] ; store value of x
DEPARTMENT OF IT/SVSCE 23

IT2354 EMBEDDED SYSTEMS

UNIT-I

ADR r4,c ; get address for c LDR r0,[r4] ; get value of c ADR r4,d ; get address for d LDR r1,[r4] ; get value of d ADD r0,r0,r1 ; compute c + d ADR r4,y ; get address for y STR r0,[r4] ; store value of y B after ; branch around the false block ; the false block follows fblock ADR r4,c ; get address for c LDR r0,[r4] ; get value of c ADR r4,d ; get address for d LDR r1,[r4] ; get value of d SUB r0,r0,r1 ; compute c d ADR r4,x ; get address for x STR r0,[r4] ; store value of x after ... ; code after the if statement

DEPARTMENT OF IT/SVSCE

24