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main memory
• memory technology (DRAM)
• interleaving
• special DRAMs
• processor/memory integration
HJ+S
• chapter 6 introduction
• Clark+Emer, “Performance of the VAX-11/780 Translation
Buffer: Simulation and Measurement”
- Maurice Wilkes
CPU registers
I$ D$
L2 SRAM
main memory
DRAM
magnetic/
disk mechanical
– 64-bit bus
– wide buses (especially off-chip) are hard
– electrical problems
– larger expansion size
– error-correction is harder (more writes to sub-blocks)
Address
Byte in Word
Word in Doubleword
Bank
Doubleword in Bank
0 0
mux/select
mux/select
latch latch
to bus
to bus
M-1 M-1
latch latch
control status control status
address div M select address div M select
superbank
• collection of banks that make up a cache line
+ multiple superbanks, good for multiple line accesses
how many banks to “eliminate” conflicts?
• r.o.t. answer = 2 * banks required for b/w purposes
CAS
Data
N N+1 N+2 N+3
clock
RAS
CAS
Data ETC.
N N+1 N+2 N+3
+
+
Data Pages
VPN Next
page table entry
main
memory
process model
• “virtual” user processes
• must access memory through address translation
• can’t “see” address translation mechanism itself (its own page table)
• OS kernel: a process with special privileges
• can access memory directly (using physical addresses)
• hence, can mess with the page tables (someone should be able to)
primitives
• at least one privileged mode
• some bit(s) somewhere in the processor
• certain resources readable/writable only if processor in this mode
• a safe facility for switching into this mode (SYSCALL)
• can’t “call” OS (OS is another process with its own VA space)
• user process: specifies what it wants done & return address
• SYSCALL: user process abdicates, OS starts in privileged mode
• return to process (switch back to unprivileged mode) not a big deal