IEEE Transactions on Power Delivery, Vol. 13, No.

1, January 1998

241

SSSC - Static Synchronous Series Compensator: Theory, Modeling, and Applications

Kalyan K. Sen, Member, IEEE
Westinghouse Electric Corporation

13 10 Beulah Road
Pittsburgh, PA 15235, USA

Abstract This paper describes the theory and the modeling technique of a Flexilile Alternating Current Transmission Systems (FACTS) device, namely, Static Synchronous Series Compensator (SSSC) using an Electromagnetic Transient Program (EMTP) simullation package. The SSSC, a solid-state voltage source inverter coupled with a transformer, is connected in series with a transmission Line. A0 SSSC injects an almost sinusoidal voltage, of variable magnitude, in series with a transmission line. This injected voltage is almost in quadrature with the line current, thereby emulating an inductive or a capacitive reactance in series with the transmission line. This emulated variable reactance, inserted by the injected voltage source, influences the electric power flow in the transmissioni line. Keywords - AC transinission, FACTS, power flow controller, power converter, inverter, thyristor, GTO, etc.
I. INTRODUCTION

Electric power flow h o u g h an altemating current transmission line is a function of the line impedance, the magnitudes of the sending-end and receiving-end voltages, and the phase angle between these voltages. The power flow can be decreased by inserting an additional inductive reactance in series with the transmission line, therehy increasing the effective reactance of the transmission line between its two ends. Also, the power flow can be increased by inserting an additional capacitive reactance in series with the transmission line, thereby decreasing the effective reactance of the transmission line between its two ends. Traditionally, in order to control the power flow of the transmission line, the effective line reactance is controlled by using fixed or thyristor-controlled series capacitors or inductors. Recently, a new power flow controller entitled Transmission Line Dynamic Impedance Compensation System [13, which uses solidstate switching converters has been proposed. With the use of the impedance compensaticm controller, a Static Synchronous Series Compensator (SSSC), which is a solid-state voltage source inverter, injects an almost sinusoidal voltage, of variable magnitude, in series with a transmission line. This injected voltage is almost in quadrature with the line current. A small part of the injected voltage which is in phase with the line current provides the losses in the inverter. Most of the injected voltage which is in quadrature with the line current emulates an inductive or a capacitive reactance in series with the transmission line. This emulated variable real3ance, inserted by the injected voltage source, influences the electric power flow in the transmission line.
PE-862-MD-0-04-1907 A paper recommended and approved by the IEEE Transmission ;and Distribution Committee of the IEEE Power Engineering Society for publication in the IEEE Transactions on Power Delivery. Manuscript sutimitted December 27, 1996; made available for printing April 17, 1997.

An impedance compensation controller can compensate for the transmission line resistance if an SSSC is operated with an energy storage system [2]. An impedance compensation controller, when used with an SSSC and no energy storage system, is essentially a reactance compensation controller. The reactance compensation controller is used to operate the inverter in such a way that the injected altemating voltage in series with the transmission line is proportional to the line current with the emulated reactance being the constant of propoftionality. When an SSSC injects an alternating voltage leading the line current, it emulates an inductive reactance in series with the transmission line causing the power flow as well as the line current to decrease as the level of compensation increases and the SSSC is considered to be operating in an inductive mode. When an SSSC injects an altemating voltage lagging the line current, it emulates a capacitive reactance in series with the transmission line causing the power flow as well as the line current to increase as the level of compensation increases and the SSSC is considered to be operating in a capacitive mode. FACTS devices consist of a solid-state voltage source inverter with several Gate Turn Off (GTO) thyristor switch-based valves and a DC link capacitor, a magnetic circuit, and a controller. The number of valves and the various configurations of the magnetic circuit depend on the desired quality of AC waveforms generated by the FACTS devices. The objective in this paper is to describe the fundamentals of an SSSC and to implement the operation of an SSSC using an Electromagnetic Transients Program (EMTP) simulation package. The inverter configuration described in this paper is one of many different possible configurations that can be used to build a voltage source inverter. The digital simulation includes the injection of a 24-pulse harmonic neutralized voltage source of variable magnitude in series with a 3-phase transmission line connecting a 3-phase voltage source at each end. The simulation results show the basic functions of an SSSC in terms of controlling the power flow in the transmission line.

TI. THEORY
Fig. 1 shows a single line diagram of a simple transmission line , ,connecting a sending-end voltage with an inductive reactance, X source, ,and a receiving-end voltage source, ,respectively.

vs

vr

"L

Fig. 1 An Elementary Power Transmission System

The real and reactive power (P and Q) flow at the receiving-end voltage source are given by the expressions

p = -VsVr sin(6, - 6 , )
XL

VL
=-

sin6
0

XL

and

e=-VsVr
XL

(1

c o s ( 6 s - 6 r ) ) =(1 XL

VL

0885-8977/98/$10.00 0 1997 IEEE

Authorized licensed use limited to: Isfahan University of Technology. Downloaded on January 3, 2010 at 07:55 from IEEE Xplore. Restrictions apply.

242 where V, and Vr are the magnitudes and 6 phase angles of the voltage sources

vs and vr,respectively. For

, and

are the

simplicity,the voltage magnitudes are chosen such that V, = Vr =V and the difference between the phase angles is 6 = 6 - 6 . An SSSC, limited by its voltage and current ratings, is capable of emulating a compensating reactance, Xq, (both inductive and capacitive) in series with the transmission line inductive reactance, X,. Therefore, the expressions for power flow given in equation (1) become

p =4 and

V2

sin 6 =

V2
sin 6 XLU- Xq / X L ) V2 (2a)

transmission line with an XLIR ratio of 3.7 and no reactance compensation of any kind, i.e., Xq=O, delivering power from voltage source Vs to voltage source Fr through a transmission line. In order to increase the power flow, Pq and Qq, through the transmission line, an SSSC must emulate a capacitive reactance in series with the transmission line. The trajectory of line current from 70% with no reactance compensation to 750% with 50% capacitive reactance compensation, (XJ& = 0 . 5 ) , is shown in Fig. 4. As the capacitive reactance compensation further increases, the line current and the power flow increase as indicated by the dashed line. The trajectory of line current from 70% with no reactance
-

%ff
V2

(1 - COS 6 ) (2b) XL(1- X q I X L ) where Xef is the effective reactance of the transmission line between its two ends, including the emulated variable reactance inserted by the injected voltage source of the SSSC. The compensating reactance, Xq, is defined to be negative when the SSSC is operated in an inductive mode and positive when the SSSC is operated in a capacitive mode. Fig. 2 shows an example of a simple power transmission system with an SSSC operated both in inductive and in capacitive modes and the related phasor diagrams. The line current decreases to 1-100%, when the inductive reactance from fo% compensation, -Xq/XL, increases from - 0% to 100%. The line current increases from 70% to 133%, when the capacitive reactance compensation, XdXL, increases from 0% to 33%.
Q4 =-

(1 - cos 6 ) =

%ff

compensation to 1-100% with 100% inductive reactance compensation, (Xq/XL= -1.O$, is also shown in Fig. 4. As the inductive reactance compensation further increases, the line current and the power flow decrease towards a minimum value. The implementation of the reactance emulation technique using an SSSC is described in the next section.
II e?j90

inductive region

capacitive region

vqt

Xq= V 3

1 /capacitive
1

inductive

1- X q l X L

xs -1 01 1 XL Fig. 3 Effect of CompensatingReactance on Power Flow and Effective

~

Reactance v, = v,

Fig. 2 A Static Synchronous Series Compensator Operated in Inductive and Capacitive Modes and the Related Phasor Diagrams From equations ( 1 ) and (2), the expressions for the normalized power flow in the transmission line and the normalized effective reactance of the transmission line can be written as P41P
=

Qq/Q=lI(l-X4/XL)
3

(3)
(4)

Xe8 /

xr,

1- Xq /

x,

The effects of the compensating reactance, Xq, on the normalized power flow in the transmission line and the normalized effective reactance of the transmission line are shown in Fig. 3. When the emulated reactance is inductive, the power flow, Pq and Qq, decrease and the effective reactance, X , increases as the reactance compensation, -XJXL, increases. When the emulated reactance is capacitive, the power flow, Pq and Qq, increase and the effective reactance, Xeg, decreases as the reactance compensation, Xq/XL, increases. Fig. 4 shows a single line diagram of a power transmission system with an SSSC emulating a reactance in series with the transmission line and the related phasor diagrams. Consider a

Fig. 4 Reactance Compensation of a Lossy Transmission Line

III. A STATIC SYNCHRONOUS SERIES COMPENSATOR Fig. 5 shows an SSSC connected in series with a simple transmission line between BUS 1 and BUS 2. The transmission line has an inductive reactance, X,, and a voltage source, ,at the

vs

sending-end and an inductive reactance, Xr, and a voltage source, Vr , at the receiving-end, respectively. The SSSC consists of a 24-

243 pulse harmonic neutralized voltage source inverter, VSZ2, a magnetic circuit, MC2, a coupling transformer, T2, a mechanical switch, MS2, two electronic switches, ES2 and ES22, current and voltage sensors, and a controller. The power circuit which consists of a voltage source inverter and a magnetic circuit and the controller are described below.
SSSC

Fig. 5 A Static Synchroiious Series Compensator Model in EMTP

A. Poier circuit

inverters are phase shifted by -7.5", +7.5", and +22.5", respectively in the positive direction, irrespective of their sequence. When the time shifted pole voltage sets from two 6-pulse inverters (AlBlCl and DlElFl), shown in Fig. 7, with a phase displacement of 30' between them are fed to two Y-windings and the output voltages (after properly phase shifted) are combined by connecting the corresponding phases in series, a 12-pulse harmonic neutralized waveform is obtained. Similarly, when the time shifted pole voltage sets from the remaining two 6-pulse inverters (A2B2C2 and D2E2F2), shown in Fig. 7, with a phase displacement of 30" between them are fed to two Y-windings and the output voltages (after properly phase shifted) are combined by connecting the corresponding phases in series, a second 12-pulse harmonic neutralized waveform is obtained whose harmonic components (n = 12k f 1 for k = 1, 2, 3, etc.) have the same magnitudes as the corresponding harmonic components of the first 12-pulse harmonic neutralized waveform. However, the harmonic components (n = 12k f 1 for k = 1, 3, 5, etc.) are in opposite phases while the harmonic components (n = 12k & 1 for k = 2, 4, 6, etc.) are in phases with the corresponding harmonic components of the first 12-pulse harmonic neutralized waveform. Therefore, if all the outputs from each 6-pulse inverter are combined, as shown in Fig. 7, by connecting the corresponding phases in series, a 24-pulse harmonic neutralized waveform is obtained. The resulting output voltage exhibits a fundamental component of amplitude (2/n)v, m is the DC link capacitor voltage and any odd harmonic where v component (n) whose normalized amplitude to the fundamental component is (lln) where n = 24k f 1 for k = 1,2,3, etc.
I .

InwrterA1BlC1,

+22.5'

lnverterAZBZC2,

+7 5'

. Fig. 6 A 24-Pulse Hannonic Neutralized Inverter Configuration Fig. 6 shows a 24-pdse harmonic neutralized voltage source inverter configuration. The pole voltages from four 6-pulse inverters (AlBlCl, AZB2C2, D l E l F l , and D2E2F2) are combined by a magnetic circuit whose output is connected to a 3phase load. The poles A l , B1, C1, A2,B2, C2, D1, E l , F1, D2, voltage E2, and F2 are operated in such a way that the pole fundamental phasors in a group, for example Vm,l, and
-

& $ .< I

-.

%A

I\

I 2-Pulse Inverter I 2

Va,l of A l B l C l inverttx,
inverter,
-

FDl,l, VE1,l, and

VAT

vAl,l,

VB2, ,and

Vcs

of A2B2C2

vm,lof D l E l F l inverter, and VD2, ,

V,,,, and of lD2E2F2 inverter, are 120" apart. The displacement angle betwc:en two consecutive 6-pulse inverters in a multipulse inverter configuration is 2d6m (= 15") where m (= 4) is the total number of 6-pulse inverters used. The fundamental voltage phasor set of the A l B l C l inverter is time shifted by an angle of +22.5". The fundamental voltage phasor set of the A2B2C2 inverter is time shifted by an angle of +7.5". The fundamental voltage phiisor set of the D l E l F l inverter is time shifted by an angle of -7.5'. The fundamental voltage phasor set of the D2E2F2 inverter is time shifted by an angle of -22.5". The configuration of the magnetic circuit is such that all the time shifted pole voltages (fundamental and harmonic components) of the AlBlCl inverter are phase shifted by an angle of -22.5' in the positive direction, irrespcctive of their sequence. Similarly, all the time shifted pole voltages of the A2B2C2, D l E l F l , and D2E2F2

vF,,

Fig. 7 A Magnetic Circuit for a 24-Pulse Harmonic Neutralized Inverter

B. Controller Fig. 8 shows the control block diagram of an SSSC. An instantaneous 3-phase set of line voltages, v,, at BUS 1 is used to calculate the reference angle, 0, which is phaselocked to the phase a of the line voltage, via. An instantaneous 3-phase set of measured

Authorized licensed use limited to: Isfahan University of Technology. Downloaded on January 3, 2010 at 07:55 from IEEE Xplore. Restrictions apply.

244
line currents, i, is first decomposed into its real or direct component, Id, and reactive or quadrature component, I,, and then the amplitude, I, and the relative angle, e,, of the line current with respect to the phase-lock-loop angle, 0, are calculated. The phase angle, a,,of the line current is calculated by adding the relative angle, O,, of the line current and the phase-lock-loop angle, 0.The calculated amplitude, I, of the l$e current multiplied by the compensating refctance demand, X, , is the insertion voltage amplitude demand, V, . The phase angle, O,, of this insertion voltage demand is either OJ+900 if the demanding compensating reactance is inductive or OJ-900if the demanding compensating reactance is capacitive. The DC link capacitor voltage is dynamically regulated in relationship with the insertion voitage amplitude demand. The insertion voltage ampQtude demand, V, , and the DC link capacitor voltage demand, V, , are related by the inverter DC-to-fundamental AC amplitude g$n factor, (Kim = 2h). The DC link capacitor voltage demand, VDc, and the measured DC voltage, vm,are compared and the error is passed through an error amplifier which produces an angle, p. The phase angle, 02, of the inverter voltage is calculated by adding the angle, p, of the DC voltage regulator and the phase angle, O,, of th: insertion voltage demand. The compensating reactance demand, Xq , is either negative ifthe SSSC is emulating an inductive reactance or positive if it is emulating a capacitive reactance. In another application, the insertion voltage amplitude demand, Vq* may directly be specified and the SSSC will inject the desired voltage almost in quadrature with the line current.
Controller

power flow always increases if the emulated reactance is capacitive.

Fig. 9 Performance of a Static Synchronous Series Compensator with a 24Pulse HarmonicNeutralized Inverter Operating in Inductive and Capacitive Modes Fig. 10 shows the expanded view of the two sections of Fig. 9. The inverter voltage show the presence of 24-pulse harmonic components.
1 - V,AtX,P
lOU\

P"

-1 -

V I
1-

L__________________________________________------~

Fig. 8 Control Block Diagram of a Static SynchronousSeries Compensator

I V .RESULTS
Fig. 9 shows the digital simulation results when an SSSC emulates a reactance in series with the transmission line. At the beginning of the operation, the mechanical switch, MS2, and the electronic switch, ES22, are open and the electronic switch, ES2, is closed. The inverter, VSI2, injects no voltage. The DC link capacitor voltage, vDc, is zero. At 50 ms, an inductive reactance compensation of 0.15 per unit is requested. The inverter output 24-pulse voltage, ea, of phase a leads the line current, i,, by almost 90". At 175 ms, the inductive reactance demand is increased to 0.3 per unit. As the inductive reactance demand increases, the line current, i , and the power flow, P, and Q,, in the transmission line decrease. At 300 ms, a capacitive reactance compensation of 0.1 per unit is requested. The inverter voltage, ek, lags the line current, i,, by almost 90". At 450 ms, the capacitive reactance demand is increased to 0.15 per unit. As the capacitive reactance demand increases, the line current, i,, and the power flow, P, and Qq, in the transmission line increase. In reality, the SSSC would encounter power losses in the valves and in the magnetic circuit. Therefore, there will always be a small part of real current component, I , , flowing into the inverter and the inverter voltage will be ahnost 90" out of phase with the line current. The instantaneous DC link capacitor voltage is proportional to the amplitude of the inverter voltage. Therefore, when an SSSC emulates a reactance in series with the transmission line, the power flow in the transmission line always decreases if the emulated reactance is inductive. Also, the

Fig 10 Waveforms from a Static Synchronous Series Compensator with a 24-Pulse Harmonic Neutralized Inverter Operatmg in Inductive and Capacitive Modes V. USEFULNESS OF THE MODEL The EMTP SSSC model and accompanying descriptions are powerful tools that provide the fundamentals of how a voltage source inverter is used in a FACTS application, such as a series compensator. The model is self-contained and includes all the necessary components - a voltage source inverter with a DC link capacitor, a magnetic circuit, and a realizable controller. The control system in the model has been implemented using a per unit system. Therefore, it is easy to integrate the model in a power system network of any voltage and current level. The model can be quite beneficial for utility system planners to use in an integrated fashion with their existing EMTP network model. The model can be used to highlight the SSSC's capability to inject an AC voltage in series with a transmission line in order to control the power flow of the line. One can study the faults in the line and also the effects of voltage and current unbalances on an SSSC. The model can also be used to showcase the performance of the SSSC technology over its conventional series compensator counterpart. VI. CONCLUSION
An SSSC has been modeled using an EMIT' simulation package. The SSSC which is a voltage source inverter injects an almost sinusoidal voltage in series with the transmission line. This injected voltage is almost in quadrature with the line current,

245
thereby emulating an inductive reactance or a capacitive reactance in series with the transmission line. The power flow in the transmission line always decreases when the injected voltage by the SSSC emulates an inductive reactance i n series with the transmission lime and the power flow in the transmission line always increases when the injected voltage by the SSSC emulates a capacitive reactance in series with the transmission line. The transition from one mode of operation to the other mode takes place in a sub-cycle time. The operation of the model is verified by connecting the model in series with a simple transmission line which can easily be replaced by the utilitys existing more complex power system network.
W. ACKNOWLEDGMENT I would like to acknclwledge my colleagues at Westinghouse Electric Corporation and Dr. A. J. F. Keri of American Electric Power for their comments in preparing this document. I would also like to show my special gratitude to D r .L. Gyugyi for his valuable suggestions in many technical discussions.
99icpu = ic / Ibasei 99ids = iapu 99iqs = -(iapu t 2.0 * icpu) / SQRT(3) 99id = ids * COSPLL t iqs * SINPLL 99iq = -ids SINPLL t iqs * COSPLL 99iampl = SQRT(id * id t iq * iq) 99thetaa = ATAN( iq / (id t 1.lE-10) ) 99thetab =thetaa + PI*((id .LT. 0 . 0 ) .AND. (iq .GE. 0 . 0 ) ) 99thetir =thetab - PI*((id .LT. 0 . 0 ) .AND. (iq .LT. 0 . 0 ) ) C Series inverter current computation 99i2a = INV02A 99i2b = INV02B = INV02C 99i2c 99i2apu = i2a / Ibasei 99i2bpu = i2b / Ibasei 99i2cpu = i2c / Ibasei C Setting the SSSC reactance demand 99Xqcml = 0.15 * (TIMEX .GE. 0.05) 99Xqcm2 = 0.15 * (TIMEX .GE. 0.175) 99Xqcm3 = 0.4 * (TIMEX .GE. 0.30) 99Xqcm4 = 0.05 * (TIMEX .GE. 0.45) 99Xqcmd = -Xqcml - Xqcm2 t Xqcm3 t Xqcm4 lXqref +Xqcmd

1.0 1.0

0.0020

VIE. APPENDIX
BEGIN NEW DATA CASE C FILE NAME = 24PSSSC.IIAT (24-Pulse harmonic neutralized C SSSC). This SSSC Power Flow Controller was implemented C by K. K. Sen at Westjnghouse, STC, Pittsburgh, PA 15235. 16.666-6600.00-3 40 10 1 TACS HYBRID 99CRD = 180 / PI 99CDR = 1 / CRD 99TWOPI = 2.0 * PI 99Kll = SIN(97.5 * CDR) / SIN(60 * CDR) / 4 99K12 = SIN(22.5 * CDR) / SIN(60 * CDR) / 4 99K21 = SIN(112.5 CDR) / SIN(60 * CDR) / 4 99K22 = SIN(7.5 * CDR) / SIN(60 * CDR) / 4 = 10 99KpseV 99KiseV = 100 99Kinv = 2 / PI 99KPLLp = 100000.0 99KPLLi = 250000.0 99MS2 = 0 99Cap = 42.03-6 C Inverter base 99Vbasei = 112676.528 99Ibasei = 946.662704 C Inputs from the measuring switches 9OBUS0 1A 90BUSOlB 90BUSOlC 9o m 90VRB 9OVRC 91INV02A 91INVO2B 91INV02C 91BUS03A 91BUS03B 91BUS03C C BUS1 voltage computation 99vla = BUSOlA = BUSOlB 99vlb 99vlc = BUSOlC 99vlapu = vla / Vbasisi 99vlbpu = vlb / Vbasci = vlc / Vbasei 99vlcpu = vlapu 99vlds 99Vlqs = -(vlapu + 2 . 0 * vlcpu) / SQRT(3) = vlds * COl3PLL t vlas * SINPLL 99vld = -vlds * SIIJPLL t vlqs * COSPLL 99vlq C Phase-Lock-Loop (locked to phase a voltage of BUS1) 99PLLerr = vlqs * COS(PLLi) - vlds * SIN(PLLi) 99PLLint = PLLini t P:;Lerr * DELTAT 99PLLdot = KPLLi * PL:;int t KPLLp * PLLerr PLLini tPLLint 99PLL = PLLi + PLLdot * DELTAT PLLi tPLL = PLL - TWOPC * TRUNC(PLL/TWOPI) 99theta 99COSPLL = COS(theta) 99SINPLL = SIN(theta) C Receiving-end voltag,?computation 99vrapu = VRA / Vbascai

99vrbpu

99vrcpu = VRC / Vbastsi C Line current computation 99ia = BUS03A 99ib = BUS03B 99ic = BUS03C 99iapu = ia / Ibasei = ib / Ibasei 99ibpu

VRB / Vbasei

C Inverter angle calculation 99Vqcmd = Xqref * iampl 99VDCcmd = ABS(Vqcmd / Kinv) 99VDCsgn = SIGN(Vqcmd) 99VDCerr = (VDCcmd - vDCpu) * ES2 99VDCint = VDCini + VDCerr * DELTAT WCini +VDCint 99beta = VDCsgn * (KpseV * VDCerr + KiseV * VDCint) 99thetai = theta + thetir 99thetav = thetai - W C s g n * PI / 2 99tha2 = thetav t PI / 2 + beta C This addition of PI/2 is because the gating signals are C sine reference and the Phase-Lock-Loop signals are C cosine reference. 99theta2 = tha2 t TWOPI (tha2 .LT. 0 . 0 ) - TWOPI * (tha2 .GE. TWOPI) C Inverter Pole Voltages 99an2A1 = theta2 t 22.5 * CDR 99ang2A1 = an2Al t TWOPI * (an2Al .LT. 0 . 0 ) - TWOPI * (an2Al .GE. TWOPI) 99a12A1 = (ang2Al .GE. 0 ) .AND. ((ang2Al - PI) .LT. 0 ) 99be2A1 = ( (ang2Al - PI) .GE. 0 ) .AND. ( (ang2Al - TWOPI) .LT. 0 ) 99v2A1 = vDC / 2 * a12A1 - vDC / 2 * be2Al 99an2B1 = theta2 t (-120.0 + 22.5) * CDR 99ang2B1 = an2Bl + TWOPI * (an2B1 .LT. 0 . 0 ) - TWOPI * (an2B1 .GE. TWOPI) 99a12B1 = (ang2B1 .GE. 0 ) .AND. ((ang2B1 - PI) .LT. 0 ) 99be2B1 = ((ang2B1 - PI) .GE. 0 ) .AND. ((ang2B1 - TWOPI) .LT. 0 ) 99v2B1 = vDC / 2 * a12B1 - vDC / 2 * be2Bl 99an2C1 = theta2 + (-240.0 t 22.5) * CDR 99ana2C1 = anPC1 t TWOPI * (anPC1 .LT. 0.0) - TWOPI * (an2h .GE. TWOPI) 99a12C1 = (ang2C1 .GE. 0 ) .AND. ((ang2C1 - PI) .LT. 0 ) 99be2C1 = ((ang2C1 - PI) .GE. 0 ) .AND. ((ang2C1 - TWOPI) .LT. 0 ) 99v2C1 = vDC / 2 * a12C1 - vDC / 2 * beZCl 99an2A2 = theta2 + 7.5 * CDR 99ang2A2 = an2A2 t TWOPI * (an2A2 .LT. 0 . 0 ) - TWOPI * (an2A2 .GE. TWOPI) 99a12A2 = (ang2A2 .GE. 0 ) .AND. ((ang2A2 - PI) .LT. 0 ) 99be2A2 = ((ang2A2 - PI) .GE. 0 ) .AND. ((ang2A2 - TWOPI) .LT. 0 ) 99v2A2 = vDC / 2 * a12A2 - vDC / 2 * be2A2 99an2B2 = theta2 t (-120.0 + 7.5) * CDR 99ang2B2 = an2B2 + TWOPI * (an2B2 .LT. 0 . 0 ) - TWOPI * (an2B2 .GE. TWOPI) = (ang2B2 .GE. 0 ) .AND. ((ang2B2 - PI) .LT. 0 ) 99a12B2 99be2B2 = ((ang2B2 - PI) .GE. 0 ) .AND. ((ang2B2 - TWOPI) .LT. 0 ) 99v2B2 = vDC / 2 * a12B2 - vDC / 2 * be2B2 99an2C2 = theta2 t (-240.0 + 7.5) * CDR 99ang2C2 = an2C2 t TWOPI * (an2C2 .LT. 0 . 0 ) - TWOPI * (an2C2 .GE. TWOPI) = (ang2C2 .GE. 0 ) .AND. ((ang2C2 - PI) .LT. 0 ) 99a12C2 99be2C2 = ((ang2C2 - PI) .GE. 0 ) .AND. ((ang2C2 - TWOPI) .LT. 0 ) 99v2C2 = vDC / 2 * a12C2 - vDC / 2 * be2C2 99an2D1 = theta2 + (-30.0 + 22.5) * CDR 99ang2D1 = an2D1 t TWOPI * (an2D1 .LT. 0 . 0 ) - TWOPI * (an2D1 .GE. TWOPI) 99a12D1 = (ang2D1 .GE. 0 ) .AND. ((ang2D1 - PI) .LT. 0 ) 99be2D1 = ((ang2D1 - PI) .GE. 0 ) .AND. ((ang2D1 - TWOPI) .LT. 0 ) QQv2D1 = vDC / 2 * a12D1 - vDC / 2 * b e 2 D l 99an2E1 = theta2 + (-150.0 t 22.5) * CDR 99ana2E1 = an2El + TWOPI * (an2El .LT. 0 . 0 ) - TWOPI * ( a 4 1 .GE. TWOPI) 99a12E1 = (ang2El .GE. 0 ) .AND. ((ang2El - PI) .LT. 0) 99be2E1 = ((ang2El - PI) .GE. 0 ) .AND. ((ang2El - TWOPI) .LT. 0 ) 99v2E1 = vDC / 2 * a12E1 - vDC / 2 * be2El
~

Authorized licensed use limited to: Isfahan University of Technology. Downloaded on January 3, 2010 at 07:55 from IEEE Xplore. Restrictions apply.

246
99an2F1 = theta2 + (-270.0 + 22.5) * CDR 99ang2F1 = an2F1 + TWOPI * (an2F1 .LT. 0.0) - TWOPI * (an2F1 .GE. TWOPI) 99a12F1 = (ang2F1 .GE. 0) .AND. ((ang2F1 - PI) .LT. 0) 99be2F1 = ((ang2F1 - PI) .GE. 0) .AND. ((ang2F1 - TWOPI) .LT. 0) 99v2F1 = vDC / 2 * a12F1 - vDC / 2 * be2F1 = theta2 + (-30.0 + 7.5) * CDR 99an2D2 99ang2D2 = an2D2 + TWOPI * (an2D2 .LT. 0.0) - TWOPI * (an2D2 .GE. TWOPI) 99a12D2 = (ang2D2 .GE. 0) .AND. ((ang2D2 - PI) .LT. 0) 99be2D2 = ((ang2D2 - PI) .GE. 0) .AND. ((ang2D2 - TWOPI) .LT. 0) 99v2D2 = vDC / 2 * a12D2 - vDC / 2 * be2D2 99an2E2 = theta2 + (-150.0 + 7.5) * CDR 99ana2E2 = an2E2 + TWOPI * (an2E2 .LT. 0.0) - TWOPI * (an2E2 .GE. TWOPI) = (ang2E2 .GE. 0) .AND. ((ang2E2 - PI) .LT. 0) 99a12E2 99be2E2 = ((ang2E2 - PI) .GE. 0) .AND. ((ang2E2 - TWOPI) 99v2E2 = vDC / 2 * a12E2 - vDC / 2 * be2E2 99anZF2 = theta2 + (-270.0 + 7.5) * CDR 99ang2F2 = an2F2 + TWOPI * (an2F2 .LT. 0.0) - TWOPI * (an2F2 .GE. TWOPI) 99a12F2 = (ang2F2 .GE. 0) .AND. ((ang2F2 - PI) .LT. 0) 99be2F2 = ((ana2F2 - PI) .GE. 0) .AND. ((ans2F2 - TWOPI) .LT. 0) 99v2F2 = vDC / 2 * a12F2 - vDC / 2 * be2F2 C Magnetic Circuit C Note: The signals vX, VY and VZ in Fig. 7 are renamed as C e2a, e2b and e2c, respectively. 99v2Nll = (v2A1 + v2B1 + v2C1) / 3 99v2AlN = v2A1 - v2Nll 99v2BlN = v2B1 - v2Nll 99v2ClN = v2C1 - v2Nll 99v2N12 = (v2A2 + v2B2 + v2C2) / 3 99v2A2N = v2A2 - v2N12 99v2B2N = v2B2 - v 2 N 3 . 2 99v2C2N v2C2 - v2N12 99v2N21 = (v2D1 + v2E1 + v2F1) / 3 99v2DlN = v2D1 - v2N21 99v2ElN = v2E1 - v2N21 99v2FlN = v2F1 - v2N21 99v2N22 = (v2D2 + v2E2 + v2F2) / 3 99v2D2N = v2D2 - v2N22 99v2E2N v2E2 - v2N22 99v2F2N = v2F2 - v2N22 99e2al = K11 * v2AlN + K12 * v2BlN = K11 * v2BlN + K12 * v2ClN 99e2bl 99e2cl = K11 * v2ClN + K12 * v2AlN 99e2a2 = K21 * v2A2N + K22 * v2B2N 99e2b2 = K21 * v2B2N + K22 * v2C2N 99e2c2 = K21 * v2C2N + K22 * v2A2N 99e2a3 = K21 * v2DlN + K22 * v2FlN 99e2b3 = K21 * v2ElN + K22 * v2DlN 99e2c3 = K21 * v2FlN + K22 * v2ElN 99e2a4 = K11 * v2D2N + K12 * v2F2N 99e2b4 = K11 * v2E2N + K12 * v2D2N 99e2c4 = K11 * v2F2N + K12 * v2E2N 99vX1 = e2al + e2a3 99vY1 = e2bl + e2b3 99vZ1 = e2cl + e2c3 C VSI2 output voltage 99e2a = e2al + e2a2 + e2a3 + e2a4 = e2bl + e2b2 + e2b3 + e2b4 99e2b 99e2c = e2cl + e2c2 + e2c3 + e2c4 99e2apu = e2a / Vbasei 99e2bpu = e2b / Vbasei 99e2cpu = e2c / Vbasei C DC link capacitor voltage calculation 99Pin2 = e2a * 12a + e2b * i2b + e2c * 12c 99iDC2 = (Pin2 / (vDCpu + 1.OE-8) / Vbasei) * ES2 99DvDCpu = iDC2 / Cap / Vbasei lvDCpu +DvDCpu 1.0 0.0001 1.00 1.0 99vDC = vDCpu * Vbasei C Receiveing-end power calculation 99Pqpu = (vrapu*iapu + vrbpu*ibpu + vrcpu*icpu) / 1.5 99Qqpu = (vrapu*icpu - vrcpu*iapu) * SQRT(3) / 1.5 C Setting up the electronic switches 99ES22 = 0 99ES2 = .NOT. ES22 C TACS output 33vDCpu e2apu iapu Xqref Pqpu Qqpu BLANK RECORD ENDING TACS VSA BUSOlA 1.0053 19.73 VSB BUSOlBVSA BUSOlA VSC BUSOlCVSA BUSOlA 3.0159 59.19 BUS03AVRA BUS03BVRB BUS03AVRA BUS03CVRC BUS03AVRA e2a e22a 1.00+8 e2b e22b 1.00+8 1.00+8 e2c e22c 1.00+8 e22a 1.00+8 e22b
1.0 0.0
.Ll. U )

I."

e22c 1.00+8 T2A TRANSFORMER 9999 1.0 0.892723.679 1INV02A 2BUSOlABUS02A 0.892723.679 1.0 TRANSFORMER T2B 9999 0.892723.679 1.0 1INV02B 0.892723.679 1.0 2BUSOlBBUS02B T2C TRANSFORMER 9999 1.0 0.892723.679 1INV02C 2BUSOlCBUS02C 0.892723.679 1.0 BLANK RECORD ENDING BRANCHES BUS02ABUS03A MEASURING BUS02BBUS03B MEASURING BUS02CBUS03C MEASURING INVO2Ae22 a MEASURING INV02Be22b MEASURING INV02Ce22c MEASURING 13e2a e22a ES2 13e2b e22b
ES2

13e2c e22c ES2 13e22a CLOSED e522 13e22b CLOSED e522 13e22c CLOSED e522 13BUSOlABUS02A MS 2 13BUSOlBBUS02B MS 2 13BUSOlCBUS02C MS2 BLANK RECORD ENDING SWITCHES 60e2a 60e2b 60e2c 0.00 l4VSA 112676.528 60.00 -1.OE-03 9999. 14VSB 112676.528 60.00 -120.00 -1.OE-03 9999. 120.00 l4VSC 112676.528 60.00 -1.OE-03 9999. l4VRA 112676.528 60.00 -30.00 -1.OE-03 9999. l4VRB 112676.528 60.00 -150.00 -1.OE-03 9999. l4VRC 112676.528 60.00 90.00 -1.OE-03 9999. B b K RECORD ENDING SOURCES BLANK RECORD ENDING NODE VOLTAGE OUTPUT BLANK RECORD ENDING PLOT BEGIN NEW DATA CASE BLANK RECORD ENDING ALL DATA CASES

KREFERENCES
[11 Transmission Line Dynamic Impedance Compensation System, L. Gyugyi and C. D. Schauder, US Patent No. 5,198,746.

[2] Static Synchronous Series Compensator: A Solid-state Approach to the Series Compensation of Transmission Lines, L. Gyugyi, C. D. Schauder and K. K. Sen, 96 WM 120-6 PWRD, IEEE PES Winter Meeting, 1996.
Kalyan K. Sen (S' 1983, M' 1988) received aB.E.E(1982), aM.S.E.E(1983), andaPh.D (1987) degrees, all in Electrical Engineering, from Jadavpur University, Calcutta, India, Tuskegee University, Tuskegee, USA, and Worcester Polytechnic Institute, Worcester, USA, respectively. He held a tenure track assistant professor level position at Prairie ViewRexas A&M University for 3 years before joining Westinghouse Electric Corporation's Science & Technology Center in Pittsburgh, USA in 1990. He is a member of the control design team of world's first UniJed Power Flow Controller. His interests are in Power Converter Topologies, Electrical Machines, Numerical Computations, and Microprocessor-based hardware implementations.