Stellaris ARM Cortex-M4F Training

Peripheral Overview

Agenda
Stellaris LM4F General Specifications Features of ARM Cortex-M4F Other System Features
Low Power Features Watchdog Timers

Timers and GPIOs Analog Peripherals Connectivity Motion Control Peripherals

Stellaris LM4F Devices

Stellaris ARM Cortex-M4F

Stellaris LM4Fx MCU ARM Cortex-M4F
80 MHz
JTAG NVIC SWD/T MPU ETM FPU 256 KB Flash 32 KB SRAM ROM 2KB EEPROM

Analog
LDO Voltage Regulator 3 Analog Comparators 2 x 12-bit ADC Up to 24 channel 1 MSPS Temp Sensor

Connectivity features:
CAN, USB H/D/OTG, SPI, I2C, UARTs

High-performance analog integration

Two 1 MSPS 12-bit ADCs Three analog comparators

Serial Interfaces
8 UARTs 4 SSI/SPI USB Full Speed Host / Device / OTG 2 CAN 6 I2 C

Motion Control
2 Quadrature Encoder Inputs 16 PWM Outputs
Timer Comparators

System
Clocks, Reset System Control Systick Timer 12 Timer/PWM/CCP
6 each 32-bit or 2x16-bit 6 each 64-bit or 2x32-bit

Best-in-class power consumption

As low as 370 uA/MHz 500s wakeup from low-power modes RTC currents as low as 1.7uA

2 Watchdog Timers
PWM Generator PWM Generator

Solid roadmap
Higher speeds Larger memory Ultra-low power

GPIOs 32ch DMA Precision Oscillator

R T C

Dead-Band Generator

Battery-Backed Hibernate

Internal Memory
256 KB single-cycle Flash memory up to 40 MHz; a prefetch buffer improves performance above 40 MHz 32 KB single-cycle SRAM with bit-banding Internal ROM loaded with StellarisWare software:
Stellaris Peripheral Driver Library Stellaris Boot Loader Advanced Encryption Standard (AES) cryptography tables Cyclic Redundancy Check (CRC) error detection functionality

2KB EEPROM

Stellaris architecture
JTAG/SWD ARM Cortextm-M4F (80 MHz) FPU DCode bus NVIC MPU ROM System Control and Clocks (W/ Precls. Osc.) Flash (256 KB)

LM4F232H5QD

ICode bus System Bus SRAM BUS Matrix (32KB)

DMA Advanced High-Performance Bus (AHB) EEPROM (2K) GPIOs (105) USB OTG (FS PHY) Ssi (4)

Watchdog Timers (2) Hibernation Module Advanced Peripheral Bus (APB) General- Purpose Timers (12) UART (8) I2C (6) CAN Controllers (2) ADC Channels (24) ANALOG PERIPHERALS SERIAL PERIPHERALS SYSTEM PERIPHERALS

Analog Comparators (3)

Analog Comparators (3)

QEI (2)

MOTION CONTROL PERIPHERALS

Stellaris LM4F System Features

Direct Memory Access, Hibernate Module, Watchdog Timers

Direct Memory Access

32 channel configurable DMA controller Dedicated channels for supported peripherals
One channel each for receive and transmit path for bidirectional peripherals Multiple data sizes, two levels of priority, maskable device request

Interrupt on transfer completion, with a separate interrupt per channel Main processer is always given priority for bus access Multiple transfer modes:
Basic Auto Ping-pong, for continuous data flow to/from peripherals Scatter-gather, from a programmable list of arbitrary transfers initiated from a single request

DMA requests supported by:

UART, Timer, USB, ADC, SSI, External Peripherals I/F, GPIO
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DMA Basic Transfer and Auto Transfer

PrimaryControl Struct Source: A Destination: B Control word: Basic Location A 0x8F45 Data Copied Location B 0x8F45

DMA Request

Basic Transfers move data from one location to another as long as the request remains active, and there is still data to transfer. This works well for peripherals which normally keep their requests active for the duration of the transfer. Auto Transfers work similarly, but finish the transfer, even if the request is removed. This is typically used for software requests, so the request does not have to remain active for the entire duration.
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DMA Ping-Pong Transfers

1
Primary Ctrl Struct A Periph

2
Buffers A B C D
Primary Ctrl Struct A Periph

Buffers A B C D Complete

Alternate Ctrl Struct B Periph

Periph

Alternate Ctrl Struct B Periph

Periph

Primary control struct performs its transfer while alternate struct is idle (or being loaded with the next transfer).

Primary control struct sends an interrupt to the processor to declare its transfer complete.

3
Primary Ctrl Struct C Periph

4
Buffers A B C D
Primary Ctrl Struct C Periph

Buffers A B C D Complete

Alternate Ctrl Struct B Periph

Periph

Alternate Ctrl Struct B Periph

Periph

Alternate control struct performs its transfer, while primary control struct is loaded with the next transfer.

Alternate control struct sends an interrupt to the processor to declare its transfer complete, and the cycle starts over from step 1.
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Scatter-Gather
S/G Struct Source: A Destination: F 1 Primary Ctrl Struct Source: S/G Dest: Ctrl Struct 2 Control: S/G
B

1 2 Source: B Destination: F 3 Source: C Destination: F Source: D Destination: F Source: E Destination: F 4 Alternate Ctrl Struct Source: Destination: Control: S/G
F

4 3
C

5
E

The primary control structure performs DMA transfers to put DMA tasks from the task list into the Alternate control structure in sequence. The alternate control structure then performs each DMA task one by one. This allows many transfers to happen together, even if the relevant memory is not contiguous.

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Hibernation and Low Power States

Stellaris family devices offer the following three low power states: Sleep Mode Deep-Sleep Mode Hibernation

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Sleep Mode and Deep Sleep Mode

Sleep Mode Turns off the clock for the main processor Will wake up when a high enough priority interrupt is received

Deep Sleep Turns off the system clock, PLL, and flash memory Enables a Wake-up Interrupt Controller (WIC), which will bring the processor out of deep sleep if an interrupt is received

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Hibernation Module
The Hibernation module manages removal and restoration of power as a means for reducing power consumption. It can completely remove power from all parts of the chip except itself. Includes a 32-bit real-time seconds counter with 1/32,768 second resolution for timed wake up Dedicated pin for an external wakeup trigger GPIO pin state may be retained, and 16 32-bit words of non volatile memory may store the system state during hibernation Programmable interrupts for RTC match, external wake, and low battery events Runs on a separate clock and power source
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Normal Operation

Peripherals

Processor WIC

Hibernation Module

Processor and peripherals are powered; sleep, deep sleep, and hibernate-related features are turned off.
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Sleep Mode

Peripherals

Processor WIC

Hibernation Module

The processor enters a low-power state, and stops executing instructions until a sufficiently important interrupt is received.
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Deep Sleep Mode

Peripherals

Processor WIC

Hibernation Module

Processor enters a very low-power state, and some features (such as Systick) are shut off completely. The Wakeup Interrupt Controller (WIC) intercepts important interrupts, and wakes the processor if necessary.

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Hibernate

Peripherals

Processor WIC

Hibernation Module

Power to the majority of the chip, including the processor and all peripherals, is shut off. The Hibernation module continues to operate using its own power source and clock until the wakeup condition is met.

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Watchdog Timers
Two 32-bit countdown timers, capable of generating maskable or nonmaskable interrupts on roll-over. One Watchdog timer is clocked by the system clock. The other runs from the PIOSC Configuration may be locked to prevent inadvertent changes to the watchdog settings. User-enabled stalling for software debugging. May be used to generate a system reset when the processor fails to clear the interrupt Possible uses:
Recovering from software errors Recover from external devices failing or not behaving as expected. Reset and continue operation if the main crystal is damaged or removed.

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Stellaris LM4F Low Power Details

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Run Mode

IDD_RUN= 32mA

This mode provides normal operation of the processor and currently enabled peripherals (i.e. the ones that are enabled in RCGC registers). The microcontroller actively executes code with maximum performance. The system clock can be any of the available clock sources including the PLL.

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Sleep Mode

IDD_SLEEP= 10mA

Sleep mode is used to lower the overall power consumption by turning off the clock to the processor and memory (Flash & SRAM). The active peripherals (i.e. the ones that are enabled in SCGC/ RCGC registers) are clocked at the same frequency as the system clock. The system clock has the same clock source & frequency as that during run mode. Application: This mode is used in applications where processor neednt be running code, but peripherals are still required to function at system clock speed.

2 sys clks. (when PPL is not used)

SLEEP MODE

Processor executes a Wait for Interrupt (WFI), or Wait for Event (WFE) or Sleepon-Exit (upon completing execution of exception handler if SLEEPEXIT bit in SYSCTRL register is set)

Processor (NVIC) detects an interrupt, or depending upon the mechanism that caused it to enter the sleep mode i.e. WFI/WFE/Sleep-on-Exit.

Code execution begins

Entering into Sleep Mode and waking up from Sleep Mode

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Deep Sleep Mode

Deep Sleep mode is used to further reduce the overall power consumption by turning off the clock to the processor and memory (Flash & SRAM) along with the following:
Main osc. (MOSC, 4 to 25MHz) can be powered off. PLL is powered off (if active in Run Mode). The active peripherals (enabled in DCGC register) can be clocked using internal oscillator (IOSC, 30kHz).

Application: This mode is used in applications where processor neednt be running code, and peripherals are required to function at a speed lower than run-mode system speed.

1.25 to 350 s

DEEP SLEEP MODE

If SLEEPDEEP bit in SYSCTRL & processor executes a Wait for Interrupt (WFI)/ Wait for Event (WFE) or Sleep-on-Exit (upon completing execution of exception handler if SLEEPEXIT bit in SYSCTRL register is set)

Wake-Up Interrupt Controller (WIC) wakes up the processor upon detecting an interrupt if DEEPSLEEP bit SCR register is set.

Code execution begins

Entering into Deep Sleep Mode and waking up from Deep Sleep Mode
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Hibernation Mode

IHIB= 1.6 A

Hibernation mode provides the lowest power configuration available on Stellaris microcontrollers. This mode allows users to completely power down the core and peripherals while only maintaining power to the Hibernation module. Hibernation module is a dedicated hardware that: Allows managing removal and restoration of power to the processor. Can be independently powered by an external battery or an aux. power supply. Allows power to be restored upon assertion of an external signal, or at a certain time (using RTC). Application: Used in battery-powered/ hand-held applications where the system can be put into a lowest-power state while saving some state information.

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Power Mode Comparision

Mode Run Mode Sleep Mode Parameter IDD VDD VBAT
32 mA 10 mA

Deep Sleep Hibernate Hibernate Hibernate Mode (VDD3ON) (RTC) (no RTC)

TBD

5 A

1.7 A

1.6 A

3.3 V

3.3 V

3.3 V

3.3 V

0V

0V

N.A.

N.A.

N.A. 30 kHz

3V Off Off

3V Off Off

3V Off Off

System 40 MHz with 40 MHz with PLL PLL Clock Core

Clocked Peripherals All On while{1}

Powered On Powered On Powered On

Not Clocked Not Clocked Not Clocked Not Clocked Not Clocked All Off N.A. All Off N.A. All Off N.A. All Off N.A. All Off N.A.
Current Consumption in Different Power Modes
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TBD

Code

Hibernation Module Key Features

32 bit real time seconds counter (Real time clock) with 15-bit sub seconds & add-in trim capability Dedicated pin for waking using an external signal RTC operational and hibernation memory valid as long as VBAT is valid GPIO pins state retention (VDD3ON Mode) Two mechanisms for power control System Power Control On-chip Power Control Low-battery detection, signaling, and interrupt generation, with optional wake on low battery Clock source from a 32.768-kHz external crystal or external oscillator 16 32-bit words of battery-backed memory to save state during hibernation Programmable interrupts for RTC match, external wake, and low battery events.

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Hibernation Module Block Diagram & Signal Description

32.768 kHz crystal, or a single ended clock source Buffered version of 32.768 kHz clock

External input that brings the processor out of hibernation mode Power source for Hibernation module, can be an external power supply or a battery

Battery Backed Memory 16 Words

Output that indicates processor is in hibernation mode

Functional Block Diagram of Hibernation Module

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Hibernation Module Functional Description

The device enters hibernation mode in following cases:
When HIBREQ bit in HIBCTL register is set, or When VDD is removed with a valid VBAT (if properly configured).

When the device is in hibernation mode, HIB signal is asserted. The device wakes-up from hibernation in following cases:
When WAKE pin is asserted, or When RTC match occurs, or When low battery is detected.

Upon wake up, HIB signal is de-asserted and an internal POR signal is issued. tWAKE_TO_HIB
HIBERNATION

tLDO_RAMP

TTPOR

~500 s
HIBREQ=1, or VDD removal RTC match/ WAKE assertion/ HIB signal is de-asserted Low battery detection
Entering into hibernation and waking up from hibernation
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Code execution begins

Power Control
Dynamic power source determination
Supply voltage of Hibernation module is the higher of VDD or VBAT.

2 mechanisms for power control (based on VDD3ON bit in HIBCTL register)

Controls the power to the MCU with a control signal, HIB is connected to EN signal of an external LDO VDD3ON Mode: Uses internal switches to control power to MCU while retaining power to I/O pins

32.768 kHz

32.768 kHz

GNDX

GNDX

Power control* using an External LDO

*simplified diagram to explain the concept. See datasheet for more details.

Power Control* using VDD3ON Mode

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Hibernation Clock Source

Hibernation module requires an external clock source that is independent from the main system clock. An independent clock source is required to maintain RTC/ preserve the contents of battery-backed memory when the main system clock is powered down due to removal of VDD. A 32.768-kHz crystal or an external clock source can be used to provide clock to the Hibernation module. If the application does not require hibernation, XOSC1 pin can remain unconnected, XOSC0 can be connected to ground, and VBAT pin should be connected to VDD.

32.768 kHz

Clock Source (fEXT_OSC) 32.768 kHz GNDX

NC

Hibernation Clock Source: External Crystal

Hibernation Clock Source: External Oscillator

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Battery Management
Low Battery Detection
Optionally, hibernation can be prevented during low battery condition i.e. the module can be configured so that it does not go into hibernation mode if the battery voltage drops below this threshold. The module can monitor the voltage level of the external battery and detect when the voltage drops below VLOWBAT (1.9V, 2.1V, 2.3V or 2.5V). VLOWBAT threshold is configured using VBATSEL bit in HIBCTL register. Battery voltage is monitored while in hibernation, and the microcontroller can also be configured to wake from hibernation if the battery voltage goes below the threshold using the BATWKEN bit in the HIBCTL register.

The Hibernation module draws power from whichever source, VBAT or VDD, has the higher voltage.

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Stellaris LM4F Timers and GPIOs

32

One-Shot/Periodic Timer Mode

Timer Use Individual 16/32 bit GPTM Block 32/64 bit GPTM Block
16-bit Timer
8-bit Prescaler

Concatenated
8-bit Prescaler

16-bit Timer

32-bit Timer

32-bit Timer
16-bit Prescaler

32-bit Timer
16-bit Prescaler

64-bit Timer

Count up or down Wait-for-Trigger mode DMA trigger One-Shot timer mode

The timer stops counting and clears the bit

Periodic timer mode

Count up from 0x0 to loaded value & reloads with 0x0 Count down from its preloaded value & reloads with the preloaded value Snap-shot mode- the actual free-running value of the timer at the time-out event is loaded and the free-running value of the prescaler is loaded
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Real-Time Clock Timer Mode

Timer Use Individual 16/32 bit GPTM Block 32/64 bit GPTM Block N/A N/A Concatenated
32-bit Timer

64-bit Timer

Count up only After reset, the counter is loaded with a value of 0x1 Input clock is required to be 32.768 KHz & it is then divided down to a 1-Hz When count value matches the preloaded value, GPTM asserts and continues counting until either a hardware reset, or it is disabled by software. When the timer value reaches the terminal count, the timer rolls over and continues counting up from 0x0.

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Input Edge-Count Mode

Timer Use Individual 16/32 bit GPTM Block 32/64 bit GPTM Block
24-bit Timer 48-bit Timer
Optional Prescaler

Concatenated N/A N/A

Optional Prescaler

The maximum input frequency is of the system frequency The timer is configured as a 24-bit or 48-bit up- or down-counting including the optional prescaler with upper count value Counting down: start value is initialized Counting up : start value is 0x0 Capable of capturing three types of events
Rising edge Falling edge Both

Interrupts, ADC and/or a DMA trigger can be generated

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How Input Edge-Count mode works

Count Count Count Start Value 0x000A 0x0009 0x0008 0x0007 Match Value 0x0006 Timer stops, Flags asserted Timer reload on next cycle Count Count Ignored Ignored

Input Signal

After the match value is reached in down-count mode, the counter is then reloaded using the start value, and stopped

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Input Edge-Time Mode

Timer Use Individual 16/32 bit GPTM Block 32/64 bit GPTM Block
24-bit Timer 48-bit Timer
Optional Prescaler

Concatenated N/A N/A

Optional Prescaler

The maximum input frequency is of the system frequency The timer is configured as a 24-bit or 48-bit up- or down-counting including the optional prescaler with upper count value Counting down: start value is initialized Counting up : start value is 0x0 Capable of capturing three types of events
Rising edge Falling edge Both

Interrupts, ADC and/or a DMA trigger can be generated After the event has been captured, the timer doesnt stop counting
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How Input Edge-Time Mode works

Count Start Value 0xFFFF Z Count value loaded Count value Count value loaded loaded

Y Time

Input Signal

Configured to capture rising edge events Each time a rising event is detected, the count value is loaded
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PWM Mode
Timer Use Individual 16/32 bit GPTM Block 32/64 bit GPTM Block
24-bit Timer 48-bit Timer

Concatenated N/A N/A

The timer is configured as a 34-bit or 48-bit down-counter with a start value (and thus period) PWM frequency and period are synchronous events and therefore guaranteed to be glitch free Counting down until it reaches the 0x0 state Wait-for-Trigger mode On the next counter cycle in periodic mode, the counter reloads its start value Capable of generating interrupts based on
Rising edge Falling edge Both
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How PWM Mode works

PWM Signal Asserts Count Start Value PWM Signal PWM Signal Deasserts Asserts PWM Signal PWM Signal Deasserts Asserts

Match value

0x0

Time

Output Signal

The output PWM signal asserts when the counter is at its start state The output PWM signal deasserts when the counter value equals the mach value Capability of inverting the output PWM signal

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Synchronizing GP Timer Blocks

Synchronize selected Timers to begin counting at the same time. No interruption when the Timers are synchronized. In concatenated mode, only the bit for Timer A must be set.
Mode 32-bit One Shot 32-bit periodic Count Dir Down Up 32-bit RTC 16-bit One Shot 16-bit Periodic Up Down Up 16-bit Edge-Count Down Up 16-bit Edge-Time Down Up 16-bit PWM Down Time Out Action N/A Count value = ILR Count value = 0 Count value = 0 N/A Count value = ILR Count value = 0 Count value = ILR Count value = 0 Count value = ILR Count value = 0 Count value = ILR

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General Purpose IO
Programmable pad configuration through GPIO module Any GPIO can be an external interrupt source
GPIO banks P and Q can have individual interrupts for each pin (larger packages)

Toggle rate up to the CPU clock speed on the Advanced High-Performance Bus 5-V-tolerant input/outputs Programmable Drive Strength
2, 4, 8 mA or 8 mA with slew rate control, several pins have 18-mA drive strength

Programmable weak pull-up, pull-down, and open drain Digital input enables

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Stellaris LM4F Analog Features

43

Analog-to-Digital Converter
Stellaris LM4F MCUs feature 2 ADC modules (ADC0 and ADC1) that can be used to convert continuous analog voltages to discrete digital values Each ADC module has 12-bit resolution Each ADC module operates independently and can therefore:
Execute different sample sequences Sample any of the 24 analog input channels Generate different interrupts & triggers
t ADC VIN VOUT

24 Input Channels

VOUT

ADC0

Interrupts/ Triggers

Triggers

ADC1

Interrupts/ Triggers

VIN 101 100 011 010 001 000 t Analog-to-Digital converter

44

ADC Implementation in Stellaris LM4F MCUs

ADC Key Features

12-bit precision ADC 24 shared analog input channels Single ended & differential input configurations On-chip internal temperature sensor Maximum sample rate of one million samples/second (1MSPS). Selectable reference signals (VDDA, GNDA or two external voltages*) 4 programmable sample conversion sequencers Flexible trigger control
Controller/ software Timers Analog comparators PWM GPIO

Hardware averaging of up to 64 samples for improved accuracy 8 Digital comparators/ per ADC Efficient transfers using DMA Optional phase shift in sample time, programmable from 22.5 to 337.5

*except on 64 pin packages

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ADC Block Diagram

Analog in

ADC

Digital readings

Trigger Ref. voltage Analog Comparator

The analog comparators may also be used as ADC trigger sources: Allows the user to monitor a sensor value after it passes some threshold voltage. Conversions will only be triggered when the voltage is inside the range of interest

46

Block Diagram & Signal Description

Reference voltages to specify the voltages at which ADC converts to a min/max value Analog Inputs to ADC

Functional Block Diagram of an ADC Module

47

Sample Sequencers
ADCs on Stellaris LM4F devices collect and sample data using a programmable sequence-based approach. Each sample sequence is a fully programmable series of consecutive (back-to-back) samples that allows the ADC module to collect data from multiple input sources without having to be re-configured. Each ADC module has 4 sample sequencers that control sampling and data capture. All sample sequencers are identical except for the number of samples they can capture and the depth of the FIFO. To configure a sample sequencer, the following information is required:
Input source Mode (single-ended, or differential) Interrupt generation on sample completion Indicator for the last sample in the sequence

Sequencer

Number of Samples

Depth of FIFO

DMA Operation: There is a dedicated DMA channel for each ADC sample sequencer. Each sample sequencer can transfer data independently.

SS 3 SS 2 SS 1 SS 0

1 4 4 8
ADC Sample Sequencers

1 4 4 8
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ADC Voltage Reference

Internal

ADC uses ADCVREFA+ and ADCVREFA- reference voltages to produce a conversion value. Internal/ external reference voltages for ADC can be selected using VREF bit in ADCCTL register. Resolution (in single-ended mode):

VDDA GNDA

ADCVREFA+

External

VREFA+ CREF VREFAADCVREFA-

Conversion Result

0xC00 0x800 0x400

ADC saturates in under-voltage and over-voltage cases ( shaded region).

0x000 ADCVREFA-

Saturation Region VIN [ADCVREFA- + ADCVREFA+ ] ADCVREFA+ 2

49

Range:

0xFFF

ADC Voltage Reference & Conversion Range

Differential Sampling
ADC also allows differential sampling of two analog input channels. Differential input pair can be configured in ADCSSMUXn register. Differential sampling can be enabled by setting Dn bit in ADCSSCTL0. Differential input pair n samples the voltage difference (VIN) between consecutive even and odd analog inputs channels.

Conversion Result

For conversion accuracy:

0xC00 0x800 0x400

Resolution:

Saturation Region VIN 0 VADCVREF

50

0xFFF

0x000 -VADCVREF

ADC conversions saturate in under-voltage and over-voltage cases (shaded region).

Where, VADCVREF = ADCVREFA+ - ADCVREFA-

ADC Conversion Range in Differential Mode

Sample Phase Control

ADC Sample Phases shifts
ADC0 and ADC1 can be operated from the same trigger source. If they are sampling data at the same frequency, then start of conversion can be delayed in 15 discrete increments of 22.5from 0up to 337.5 .
ADC Sample Clock PH 0x0 (0) PH 0x1 (22.5) PH 0x1F (337.5) ADC Sample Phases
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

Skewed Sampling
ADC0 & ADC1 can be used out of phase of each other. The sampled data can be combined in the software. This effectively doubles the conversion bandwidth upto 2MSPS.
Analog Input

t ADC0 ADC1 S1 S1 S2 S2 S3 S3 S4 S4 S5 S5 S6 S6 S7 S7 S8
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S8

Skewed Sampling

Hardware Sample Averaging Circuit

Hardware sample averaging circuit can be used to generate higher precision results.
Samples D C B A B A C D t

Up to 64 samples can be accumulated and averaged to form a single data entry in the sequencer FIFO. By default, hardware sample averaging circuit is off. All the data from the converter passes through the sequencer FIFO. Averaging is controlled by ADCSAC register. All channels are averaged equally irrespective of their configuration (single ended or differential). Example: if AVG value in ADCSAC register is0x02, then 4x averaging will be done. If IE bit in ADCSSCTL0 register is set, then an interrupt will be generated when FIFO gets second data entry. Tradeoff: Throughput is decreased proportionally to the number of samples in the averaging calculation.

A+B+C+D 4 A+B+C+D 4

INT

FIFO Sample Averaging Example

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Internal Temperature Sensor

Reference Voltage (V)

Internal temperature sensor module consists of: Band gap reference circuit that provides reference voltage to various analog peripherals.

2.7

1.633

On-chip internal temperature sensor.

0.3 Temperature( C) -55 25 125

147.5

Internal temperature sensor serves following key purposes:

Senses die temperature for reliable system operation. Provides temperature measurements in order to calibrate hibernation modules RTC trim value.

Temperature ( C)

91.2 34.9 -21.3 -77 ADC Output

The temperature can be sampled by setting TSn bit in ADCSSCTLn register.

0x0

0x400

0x800

0xC00

0xFFF
53

Internal Temperature Sensor Characteristics

Digital Comparator Unit

Each ADC module contains 8 digital comparators. Operational Modes: Always Mode Once Mode Hysteresis Mode Hysteresis Always Mode Modes can be selected using CIM or CTM bit in ADCCTLn register. Functional Ranges: Low Band Mid Band High Band Functional Ranges can be selected using COMP0 and COMP1 bits in ADCDCCMPn register. Always, COMP1 COMP0.

COMP1

COMP0

Low Band

Mid Band

High Band

A digital comparator compares the ADC modules output with user programmable limits. Depending on the result of the comparison, a processor interrupt or a trigger to the PWM module can be generated.

VIN

t
Digital Comparator Functional Ranges
54

Analog Comparator Key Features

Analog comparator compares two analog voltages and provides a logical output depending upon the result of the comparison. 3 analog comparators integrated in Stellaris MCUs can be independently used to: Compare two analog signals and replace an external/discrete analog comparator to save board space and system cost. Drive an external pin Trigger an ADC Signal an application using interrupts
Any Signal Trigger an ADC Generate an interrupt VIN- (external) VIN+ (internal ref. or external) VOUT

VINVIN+

1 VOUT 0 0

0 t

Using Analog Comparators Independently Analog Comparator: Inputs & Output

55

Block Diagram & Signal Description

C2o

Analog Comparator Ns negative input

C1o

Analog Comparator Ns output

Analog Comparator Ns positive input

C1o

Output to trigger an ADC

C0o

Functional Block Diagram of Analog Comparator Module

56

Stellaris LM4F Communications

57

Synchronous Serial Interface (SSI)

Up to 4 SSI modules Programmable interface operation for Freescale SPI, MICROWIRE, and Texas Instruments synchronous serial interfaces Programmable clock bit rate and prescaler with SSI slave clock frequencies up to 1/6th of the system clock Separate transmit and receive FIFOs, 16 bits wide, 8 locations deep Programmable data frame size from 4 to 16 bits Internal loopback test mode for diagnostic/debug testing Efficient transfers using Micro Direct Memory Access Controller (DMA)
Separate channels for transmit and receive Receive single request asserted when data is in the FIFO; burst request asserted when FIFO contains 4 entries Transmit single request asserted when there is space in the FIFO; burst request asserted when FIFO contains 4 entries
58

Inter-Integrated Circuit (I2C)

Up to 6 I2C Modules Master and slave modes supported Simultaneous master and slave operation Master arbitration, clock synchronization, multi-master support, and 7-bit addressing modes There are a total of four I2C modes:
Master Transmit, Master Receive Slave Transmit, Slave Receive

Standard (100 Kbps), Fast (400 Kbps), and High (3.4 Mbps) speeds supported Master and slave interrupts support
I2C master generates interrupts when a transmit or receive operation completes (or aborts). I2C slave generates interrupts when data has been sent or requested by a master.
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Universal Asynchronous Receiver/Transmitter (UART)

Up to 8 UARTs Each UART has:
Separate transmit and receive FIFOs Programmable FIFO length FIFO trigger levels of 1/8, 1/4, 1/2, 3/4, and 7/8 Programmable baud-rate generator allowing rates up to speeds up to 10Mbps Standard asynchronous communication bits for start, stop and parity False start bit detection Line-break generation and detection

Fully programmable serial interface characteristics:

5, 6, 7, or 8 data bits Even, odd, stick, or no-parity bit generation/detection 1 or 2 stop bit generation

IrDA serial-IR (SIR) encoder/decoder providing:

Programmable use of IrDA Serial InfraRed (SIR) or UART input/output Support of IrDA SIR encoder/decoder functions for data rates up to 115.2 Kbps half-duplex Support of normal 3/16 and low-power (1.41-2.23 s) bit durations Programmable internal clock generator enabling division of reference clock by 1 to 256 for lowpower mode bit duration

ISO 7816 Support

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Universal Asynchronous Receiver/Transmitter (UART)

LIN protocol support EIA-485 9-bit support Standard FIFO-level and End-of-Transmission interrupts Efficient transfers using Micro Direct Memory Access Controller (DMA)
Separate channels for transmit and receive Receive single request asserted when data is in the FIFO; burst request asserted at programmed FIFO level Transmit single request asserted when there is space in the FIFO; burst request asserted at programmed FIFO level

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Universal Serial Bus (USB)

Integrated controller and PHY
USB 2.0 Full Speed (12 Mbps) operation Devices with OTG/Host/Device Transfer: Control, Interrupt, Bulk and Isochronous 16 Endpoints
0 and 1 hardwired for control transfers (one in, one out) Remaining 14 may be configured by software.

2 KB Dedicated Endpoint Memory

Direct Memory Access One endpoint may be defined for double-buffered 1023-byte isochronous packet size.

USB-IF Compliance
TI is a member of the USB Implementers Forum. Complies with USB-IF certification standards TIs Stellaris VID available for sublicense (with assigned PIDs).
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Controller Area Network (CAN)

2CAN controllers Each supports CAN protocol version 2.0 part A/B Bit rates up to 1Mb/s 32 message objects, each with own identifier mask Maskable interrupt Disable automatic retransmission mode for TTCAN Programmable loop-back mode for self test operation

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Stellaris LM4F Motion Control

64

Pulse Width Modulation (PWM)

2 PWM modules with 4 generators each. Each generator contains: One 16-bit counter
Runs in down or up/down mode Output frequency controlled by a 16-bit load value Load value updates can be synchronized Produces output signals at zero and load value

Two comparators
Comparator value updates can be synchronized Produces output signals on match

PWM generator
Output constructed based on actions taken as a result of the counter and comparator output signals Produces two independent PWM signals

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Pulse Width Modulation (PWM) cont.

Dead band generator
Produces two PWM signals with programmable dead band delays suitable for driving a half-H bridge Can be bypassed, leaving input PWM signals unmodified

Output control block

PWM output enable of each PWM signal Optional output inversion of each PWM signal Optional fault handling for each PWM signal Synchronization of timers in the PWM generator blocks Synchronization of timer/comparator updates across the PWM generator blocks Interrupt status summary of the PWM generator blocks

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PWM Block Diagram

Timer

Compare Timer match events

Signal Generation Preliminary PWM

Dead-band Generation

Output Logic PWM pair with Dead-band

To PWM pins

The PWM module essentially consists of a timer, a configurable comparison module, and three stages of signal generation and conditioning logic.

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PWM Compare Event Waveforms

CMPA CMPB

.. ..
Count Down Mode

..

Asymmetrical Waveform

Match events produce signals, which can be used to drive positive or negative edges of a PWM. Each counter may generate up to two PWMs using different combinations of compare events.
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PWM Compare Event Waveforms

CMPA CMPB

. . . . . . . .
Count Up and Down Mode

Symmetrical Waveform

Up-down mode is well suited to symmetrical, center-aligned waveforms.

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PWM Dead bands and Output Logic

PWM waveforms from the counters may be used as is, or the dead band and output logic can produce a complement waveform to one of them. No dead band Original wave The complement waveform may optionally have dead bands inserted, which are convenient for some motor control applications.

Dead band

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Fault-condition Interrupts
A fault condition is one in which the controller must be signaled to stop normal PWM function and then sets the outputs to a safe state.

There are two basic situations where this becomes necessary:

The controller is stalled and cannot perform the necessary computation in the time required for motion control (Stall signal from internal debugger) An external error or event is detected (FAULTn pin)

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Quadrature Encoder Interface (QEI)

Also known as a 2-channel incremental encoder, a quadrature encoder interface converts angular displacement into a pulse signal. It is typically used in motion control applications, and can track the position, velocity, and direction of a motor

Stellaris QEI features: Includes two quadrature encoder interface (QEI) modules Position integrator that tracks the encoder position Programmable noise filter on the inputs Velocity capture using built-in timer Interrupt generation on:
Index pulse Velocity-timer expiration Direction change Quadrature error detection
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Quadrature Encoder Interface (QEI)

A digital (angular) position sensor
photo sensors spaced /4 deg. apart slots spaced deg. apart light source (LED)

/4
Ch. A Ch. B

shaft rotation Incremental Optical Encoder Quadrature Output from Photo Sensors
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Quadrature Encoder Interface (QEI)

Position resolution is /4 degrees
(00) (11) (10) (01)

increment counter

10

decrement counter

(A,B) =

00 Ch. A Ch. B

Illegal Transitions; generate phase error interrupt

11

01 Quadrature Decoder State Machine

74