International Journal of Computational Intelligence and Information Security, January 2014 Vol. 5, No.

1 ISSN: 1837-7823

Efficient

-bit Dynamic Range Reverse Converter

H. Siewobr and K. A.Gbolagade Department of Computer Science Faculty of Mathematical Sciences University for Development Studies GHANA Abstract

This paper proposes a new -bits dynamic range moduli set , and a modulo operation free reverse converter based on New Chinese Remainder Theorem I. The proposed reversed converter is purely adder based and only requires one level of regular carry propagate adder. Theoretical analyses show that the proposed converter outperform existing known state of the art equivalent converters in terms of both area cost and conversion time. Experiments were conducted by implementing the proposed converter and the state of the art equivalent converters using Xilinx ISE 14.3 software to target a Spartan 3 FPGA. The results obtained after design place and route given in terms of the number of FPGA slices and input-to-output propagation delays (in nano seconds) for various dynamic range requirements (different values of n) suggest that, the proposed converter improves the area and delay of the most efficient state of the art equivalent converter by about . and respectively. Keywords: Chinese Remainder Theorem, Moduli Set, Multiplicative Inverses, Reverse Conversion.

1. Introduction
Residue Number System (RNS) is an integer number system with the capabilities to support parallel, carry-free addition, borrow-free subtraction and single step multiplication without partial product. These features enable RNS utilization in Digital Signal Processing applications such as digital filtering, convolution, fast Fourier transform and image processing [8], [5]. The two critical issues for the residue arithmetic are moduli selection and data conversion. For a successful application of RNS, data conversion must be very fast so that the conversion overhead doesnt nullify the RNS advantages [5]. Residue to binary conversions are traditionally based on the Chinese Remainder Theorem (CRT), New CRTs (CRT-I, CRT-II) or Mixed-Radix Conversion (MRC). CRT embraces parallelism in the operation requirement makes it not very efficient. whereas the conversion process, but its large modulo sequential (non-parallel) MRC approach involves relatively smaller modulo operations. On the order hand, CRTI and CRT-II, which are the most recent of the three approaches also involve smaller modulo operations when compared to the traditional CRT. Several moduli sets have been proposed with algorithms designed for performing RC. Among them is the [3,5,7]. The converter proposed in [5] which demanded popular three-moduli set delay was proven to outperform the ones in [7, 8 and 9]. area and imposed In this paper, we propose the new moduli set from the traditional moduli set and to form the modulus in . The major by combining the moduli are numerous as the merit of moduli sets, which are free of advantages of the proposed moduli set { 2n+1 type modulus have been documented in literature [4]. Consequently, we propose an efficient reverse converter for the new moduli set using CRT-I. When compared to [5], our algorithm is superior in terms of both area and delay. The rest of this article is organized as follows. In Section II, we present the necessary background information. Section III presents the proposed reverse converters while the hardware implementation is presented in Section IV. Section V evaluates the performance of our scheme while the paper is concluded in Section VI.

International Journal of Computational Intelligence and Information Security, January 2014 Vol. 5, No. 1 ISSN: 1837-7823

2. Background
For a moduli set with the dynamic range the residue number can be converted into the decimal number , according to the, as follows: (1) where and is the multiplicative inverse of with respect to [4]. , the binary

New Chinese Remainder Theorem I (New CRT-I) ; Given the residue number number can be computed as;

(2) which can further be simplified to; (3) where, (4) (5) . In the next section we present the proposed CRT-I based reverse converters. (6)

3. Proposed Converter
The following property is important to the conversion algorithm to be introduced in this next section; Property 1: Modulo multiplication of a residue number by , where and are positive integers, is equivalent to -bit circular left shifting [4]. Property 2: Modulo integers [11]. of is equal to modulo of , where and are

Given the RNS number with respect to the moduli set in the form the proposed algorithm computes the binary equivalent of this RNS number based on the CRT-I. First, we wish to show that and are relatively prime. the moduli Theorem 1: The moduli set Proof: It has been shown in [10]. Following Equation (3), the CRT-I for two moduli can thus be represented as; (7) contains pairwise relatively prime moduli.

International Journal of Computational Intelligence and Information Security, January 2014 Vol. 5, No. 1 ISSN: 1837-7823 Theorem 2: Given the with and , the following hold true: (8) Proof: substituting the moduli and (8) into (7) we have; (9) We can further simplify (9) as; (10) where, (applying property 1) (11) Thus (7) holds true.

and (applying property 2) (12)

Finally, (10) can be written as; (13)

4. Hardware Realization
The diagram of blocks in Fig. 1 represents the proposed reverse converter architecture. Considering and as the delay and area of a -bit Full Adder (FA), respectively, we consider also that the delay of a Carry-Propagate Adder (CPA) with End-Around Carry (EAC) is twice the delay of a regular CPA at a similar and hardware cost. Furthermore, we consider that the area and delay of a half adder (HA) are , respectively. The bitwise operations are ignored for area and delay analysis, as they are expected to be negligible regarding the FAs and HAs. From Fig. 1, the hardware structures of the proposed reverse converter is based on (12) and (13). Equation (12) is computed by a CSA with EAC and regular regular CPA. It is worth noting that though CPA is a -bit adder, it contains -bit HAs since one of its operands has a constant -bit 1s. The final binary equivalent of an RNS with -bit circular left shifting of the output of the CPA i.e. at no number is computed by concatenating hardware cost. In terms of area and delay requirements of the proposed scheme, the CSA is made up of , while the CPA imposes a delay of at cost. XNOR/OR pairs and imposes a delay of

International Journal of Computational Intelligence and Information Security, January 2014 Vol. 5, No. 1 ISSN: 1837-7823

Bit Organizer

CSA

CPA

Figure 1: Schematic Diagram of the Proposed Scheme

5. Performance Evaluation
To evaluate the performance of the proposed converter, we compare our proposal with the equivalent state of the in [5]. First, it is worth art converters for the equal dynamic range moduli set remembering as stated earlier that the proposed moduli set is more advantageous than the related state of the since it eliminates the high delay and high area imposing equal dynamic range moduli set . Next, the theoretical analysis presented in Table 1 shows that the proposed converter modulo outperforms the state of the art in terms of both area and delay.
Table 1: Area and Delay comparison Converters [5] Proposed Area (

Delay (

To validate these theoretical suggestions, we did a HDL specification of both the proposed and equivalent state of the art converter. Using these HDL specifications, experiments was carried out using Xilinx ISE 14.3 software to target a Spartan 3 FPGA. The results obtained after design place and route are given in terms of the number of FPGA slices in Table II and input-to-output propagation delays (in nano seconds) for various dynamic range requirements (different values of n) in Table III. These results suggest that, the proposed converter improves the and delay by about . area demanded by the equivalent state of the art converter in [5] by about

International Journal of Computational Intelligence and Information Security, January 2014 Vol. 5, No. 1 ISSN: 1837-7823
Table 2: Converters' Area [Number Of Slices] Converter [5] Proposed

Table 3: Converters' Delay

Converter [5] Proposed

6. Conclusion
In this paper, we presented a new and efficient 3n-bits dynamic range moduli set . subsequently, we proposed an efficient reverse converter for the moduli set under investigation. The proposed converter does not require any modulo operations and is simple to design. Both theoretical and experimental results show that the proposed scheme outperforms the best known similar state of the art equivalent converter in terms of both area and delay.

International Journal of Computational Intelligence and Information Security, January 2014 Vol. 5, No. 1 ISSN: 1837-7823

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