Ex.

No:6

DESIGN AND SIMULATION OF FLIP-FLOPS

AIM: Design and Simulation of the following flip-flops 1) JK Flip-flop in Behavioral Model. 2) D Flip-flop in Behavioral Model. 3) RS Flip-flop in Structural Model. 4) T Flip-flop in Structural Model.

SOFTWARE USED:
Xilinx ISE 9.1i A project navigator software tool ModelSim XE II 5.8 C Simulator

THEORY:
JK Flip-flop: The J-K flip-flop is the most versatile of the basic Flip-flop. It has the input- following character of the clocked D Flip-flop, but has two inputs, traditionally labeled J and K. If J and K are different then the output Q takes the value of J at the next clock edge.

D Flip-flop: The D flip-flop tracks the input, making transitions with match those of the input D. The D stands for "data"; this flip-flop stores the value that is on the data line. It can be thought of as a basic memory cell. A D flip-flop can be made from a Set/Reset Flip-flop by tying the set to the reset through an inverter. The result may be clocked.

RS Flip-flop:

A RS-flip-flop is the simplest possible memory element. It is constructed by feeding the outputs of two NOR gates back to the other NOR gates input. The inputs R and S are referred to as the Reset and Set inputs, respectively. When S=1 and R=0: The output of the bottom NOR gate is equal to zero, Q'=0. Hence both inputs to the top NOR gate are equal to one, thus, Q=1. Hence, the input combination S=1 and R=0 leads to the flip-flop being set to Q=1. When S=0 and R=1: Similar to the arguments above, the outputs become Q=0 and Q'=1. We say that the flip-flop is reset. When S=0 and R=0: Assume the flip-flop is set (Q=0 and Q'=1), then the output of the top NOR gate remains at Q=1 and the bottom NOR gate stays at Q'=0. Similarly, when the flipflop is in a reset state (Q=1 and Q'=0), it will remain there with this input combination. Therefore, with inputs S=0 and R=0, the flip-flop remains in its state. When S=1 and R=1: This input combination must be avoided.

T Flip-Flop: The T or "toggle" Flip-flop changes its output on each clock edge, giving an output which is half the frequency of the signal to the T input. It is useful for constructing Binary, frequency dividers, and general binary addition devices. It can be made from a JK Flip-flop by tying both of its inputs high. But here we have constructed using a D Flipflop with and inverter.

PROCEDURE:
1. Open a new project from Xilinx ISE 6, a project navigation software tool. 2. Select a source file name as VHDL module and define the VHDL sources respectively the input and output ports. 3. Enter the program and save the file. 4. Check the syntax option from synthesis to know the error. 5. Go for the Synthesize XST to view RTL schematic report (new list). 6. Launch Modelsim simulator from design entry utilities and enter the values of input ports.

7. Run the program to view the waveform representation of the output.

PROGRAMS:
1a. Design and simulation of JK Flip-flop using Behavioral Model:library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity jk is port (reset,clk,j,k:in std_logic; q: inout std_logic; q0: out std_logic); end jk; architecture Behavioral of jk is begin process(reset,clk.j,k) begin if rst='1' then q<='0'; q0<=1; elsif clk=1 and clkevent and j='0' and k='0' then q<=q ; q0<=q0; elsif clk=1 and clkevent and j='0' and k='1' then q<='0' ; q0<=not q; elsif clk=1 and clkevent and j='1' and j='0' then q<='1' ; q0<=not q; elsif clk=1 and clkevent and j='1' and k='1' then q<='not q ; q0<= not q0; end if; end if; end process;

end Behavioral;

jk

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity jkff is Port ( reset,clk,j,k : in STD_LOGIC; q,qbar : inout STD_LOGIC); end jkff;

architecture Behavioral of jkff is

begin

process(reset,clk,j,k) begin if reset='1' then q<='0'; qbar<='1'; elsif clk='1' and clk'event then if j='0' and k='0' then q<=q ; qbar<=qbar; elsif j='0' and k='1' then q<='0' ; qbar<='1'; elsif j='1' and k='0' then

q<='1' ; qbar<='0'; elsif j='1' and k='1' then q<=not q ; qbar<=not qbar; end if; end if; end process;

end Behavioral;

1b. Design and simulation of D Flip-flop using Behavioral Model:

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity d is port (rst,clk,d: in std_logic; q: inout std_logic); end d; architecture Behavioral of d is begin process(rst,clk,d) begin if rst='0' and clk='1' and clkevent then q<=d; end if; end process; end Behavioral; 1c. Design and simulation of RS Flip-flop using Structural Model:

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity rs is port (r: in std_logic; s: in std_logic; q: inout std_logic; q0: inout std_logic); end rs;

architecture Structural of rs is component Nor1 port (a, b: in std_logic; x: inout std_logic); end component; begin N1: Nor1 port map(r, q0, q); N2: Nor1 port map(s, q, q0); end Structural; i) Design and simulation of Nor Gate: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity nor1 is port (a, b: in std_logic; x: inout std_logic); end nor1; architecture structural of nor1 is

signal y: std_logic; begin x<= (a or b); y<=not x;

end structural;
Program: Behavioral -RS Flip Flop library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY SRFF2 IS PORT ( S : IN STD_LOGIC; R : IN STD_LOGIC; CLK : IN STD_LOGIC; Q : OUT STD_LOGIC; QNOT : OUT STD_LOGIC); END SRFF2; ARCHITECTURE BEHAVIORAL OF SRFF2 IS SIGNAL QTEMP:STD_LOGIC; BEGIN PROCESS(CLK) BEGIN IF(CLK'EVENT AND CLK='1') THEN IF(S='0' AND R='0')THEN Q<=QTEMP; ELSIF(S='0' AND R='1')THEN Q<='0'; QNOT<='1'; QTEMP<='0'; ELSIF(S='1' AND R='0')THEN Q<='1'; QNOT<='0'; QTEMP<='1'; ELSE Q<='X'; QNOT<='X'; QTEMP<='X'; END IF; END IF; END PROCESS; End Behavioral;

RSFF library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity rsff is Port ( reset,clk,r,s : in STD_LOGIC; q,qbar : inout STD_LOGIC); end rsff; architecture Behavioral of rsff is begin process(reset,clk,r,s) begin if reset='1' then q<='0';qbar<='1'; elsif clk='1' and clk'event and s='0' and r='0' then q<='0'; qbar<='1'; elsif clk='1' and clk'event and s='0' and r='1' then q<='0'; qbar<='1'; elsif clk='1' and clk'event and s='1' and r='0' then q<='1'; qbar<='0'; else assert s='1' and r='1'; report "wrong input" severity error; end if; end process; end Behavioral;

1d) Design and simulation of T Flip-flop using structural Model:

library IEEE;

use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity tff is port (t: inout std_logic; clk: in std_logic; q: inout std_logic); end tff;

architecture structural of tff is component dff1 port (x, y: in std_logic; z: out std_logic); end component; component not1 port (m: in std_logic; n: out std_logic); end component; begin n1:not1 port map (q, t); d1:dff1 port map (clk, t, q); end structural; 1) Design and simulation of D Flip-flop:

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity dff1 is

port (x, y: in std_logic; z: out std_logic); end dff1;

architecture Behavioral of dff1 is begin process (x, y) begin if y='1' then z<=x; end if; end process; end Behavioral;;

i) Design and simulation of Not gate:

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity not1 is port (m: in std_logic; n: out std_logic); end not1;

architecture dataflow of not1 is

begin n<= not m; end dataflow;

Behavioral- T FLIP FLOP library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity TFF2 is Port ( T : in STD_LOGIC; CLK : in STD_LOGIC; Q : out STD_LOGIC; QNOT : out STD_LOGIC); end TFF2; architecture Behavioral of TFF2 is SIGNAL QTEMP:STD_LOGIC:='0'; begin PROCESS(CLK) BEGIN IF(CLK'EVENT AND CLK='1') THEN IF(T='0')THEN Q<=QTEMP; QNOT<=NOT QTEMP; ELSE Q<=NOT QTEMP; QNOT<=QTEMP; QTEMP<=NOT QTEMP; END IF; END IF; END PROCESS; end Behavioral;

Result: Hence the design and simulation of flip flops implemented and output is verified.