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Hangseok Choi
www.fairchildsemi.com
Agenda
Introduction
Idealized Operation of AHB Converters Steady state Analysis of an Actual AHB Converter Design Procedure with Example Design Tips Experimental Verification Conclusion
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Inherent zero voltage switching (ZVS) capability since parasitic components can be incorporated to achieve ZVS High efficiency and low EMI through ZVS Simple topology and simple control MOSFET voltage is clamped to the input voltage Fixed switching frequency operation Smaller inductor can be used compared to forward converter topologies (less than half)
What if an asymmetric square wave is introduced to the transformer in series with a DC blocking capacitor?
Not saturated thanks to the voltage of blocking capacitor
+ VCB + Vd 0 + CB V p 1:1
5
+ Vp -
Same area 0
VCB
Ip
Q2
Vin
+ CB + Lm Vd Vp - VCB +
IM
+ Vrec
n:1
ILO
1-D Q1 D Vd Vp Vin
Vin-VCB VCB
Vrec Vo
D (1 D ) + VCB = Vo n n
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+ CB Vd Vp -
+ Lm
+ Vrec
ILO + Vo
Io
1-D
IM
Q1 D Vd Vin
- VCB +
n:1
Vp
VCB
Vrec Vo
In steady state, the mean value of the transformer magnetizing current, IM.avg is obtained from the condition for zero net current through the DC blocking capacitor (CB) as
( I M .avg + I M .avg
IO I ) D = ( I M .avg + O )(1 D) n n IO = (1 2 D) n
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+ VCB + Vd + CB V p -
Ip + Vrec n:1 + Vo
VCB
Vp Vin D Ip
0 Vrec Vo 0 0
Actual model with series inductance Series inductor causes Ip to lag Vp Duty loss is observed in Vrec
Vp Vin Ip D
Vin
+ VCB + Vd + CB V p Lr
Ip + Vrec n:1 + Vo
VCB
0 Vrec Vo 0 0
n:1
+ Vrec -
ILO
Io
+ VO
C2 -
Ro -
D Q1 Ids1 C1
Rectifier network
Square wave generator produces a square wave voltage (Vd) by driving switches Q1 and Q2 complementarily Energy transfer network removes the DC offset of the square wave voltage (Vd) using the DC blocking capacitor (CB) transfers the pure AC square wave voltage to the secondary side through the transformer Causes Ip to lag Vpr to provide ZVS condition for Q1 and Q2 Rectifier network produces a DC voltage by rectifying the AC voltage with rectifier diodes and a low-pass LC filter
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Steady State Analysis of an AHB Converter Basic assumptions for steady state analysis:
The dead time is negligible since it is very small compared to the switching cycle The leakage inductance is much smaller than the magnetizing inductance The DC blocking capacitor CB is large enough to neglect the voltage ripple across CB The output filter inductor operates in continuous conduction mode All circuit elements are ideal and lossless The duty cycle for lower MOSFET, D, is less than 50% The capacitors C1 and C2 include not only the internal output capacitance of the MOSFETs, but also the external parasitic capacitance
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The lower switch Q1 is conducting and a voltage of (Vin-VCB) is applied to the transformer primary side (Vpr) The transformer primary side current (Ip) is the sum of the output inductor current referred to as the primary side (ILO/n) and magnetizing current (IM)
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The lower switch Q1 is turned off at t1 and the primary side current, Ip charges C1 and discharges C2 This mode continues until the primary side voltage drops to zero (in order words, until C2 is discharged to VCB) at t2
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At t2, the transformer primary side and secondary side voltages become zero and the secondary side is decoupled from the primary side Then, the output inductor current, ILO begins to freewheel in the secondary side through the rectifiers and C2 continues to be discharged
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The body diode of Q2 is conducting and the voltage across the switch Q2 is clamped at zero; By turning on Q2 while the body diode is conducting, zero voltage switching (ZVS) is achieved. A voltage of -VCB is applied across the leakage inductance and the primary side current (Ip) decreases During this mode, energy is not transferred to the secondary side (duty losses)
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The upper switch Q2 is conducting and VCB is applied to the transformer primary side (Vpr) The transformer primary side current (Ip) is the sum of output inductor current referred to as the primary side (-ILO/n) and the magnetizing current (IM)
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The upper switch Q2 is turned off at t5 and the primary side current Ip charges C2 and discharges C1 This mode continues until the primary side voltage becomes zero (in other words, until C1 is discharged to Vin-VCB) at t6
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At t6, the transformer primary side and secondary side voltages become zero and the secondary side is decoupled from the primary side Then, the output inductor current, ILO begins to freewheel in the secondary side and C1 continues to be discharged
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The body diode of Q1 is conducting and the voltage across the switch Q1 is clamped at zero voltage. By turning on Q1 while the body diode is conducting, zero voltage switching (ZVS) is achieved. During this mode, a voltage of (Vin-VCB) is applied across the leakage inductance and the primary side current (Ip) increases During this mode, energy is not transferred to the secondary side (duty losses)
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Vgs1
Vds1 Vds2
Vin
Vin
Vpr
Vin-VCB
VCB
Llk [ I p (t6 )]2 > (C1 + C2 )[(1 D )Vin ]2 I p (t6 ) = Io V (1 D ) DTS + I M .avg in n 2 Lm
IP
Vgs1
Vgs2
Vgs2
Vgs1
Vpr
Vin-VCB
VCB
Vds2
Vin-VCB VCB VCB t1 t2 t3
Vds1
Vin-VCB t5 t6 t7
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VD1 =
VD 2 =
VCB Vin D = n n
Current stresses of the rectifier diodes are balanced Current stresses of the primary side MOSFETs are unbalanced Magnetizing current DC offset decreases
I M .avg =
Io (1 2 D) n
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10
VD1 = VD 2 =
Current stresses of the rectifier diodes are unbalanced Current stresses of the primary side MOSFETs are unbalanced Magnetizing current DC offset increases
I M .avg =
Io (1 2 D) n
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LCD TV
fs=100kHz
400Vdc
192W
24V-8A
20ms
330uF
[STEP-1] Define the system specifications Estimated efficiency (Eff) =92% Input voltage range: hold up time should be considered for minimum input voltage
Pin =
22
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Llk =
Considering margin on the maximum duty cycle of the PWM controller (50%), the worst-case maximum duty cycle to calculate the transformer turns ratio is chosen as 42%.
n= =
(Vin min Dmax (1 Dmax )) 2 4(Vo + VF ) I o Llk f s Vin min Dmax (1 Dmax ) + (Vo + VF ) (Vo + VF ) (367 0.42 (1 0.42)) 2 4(24 + 1.2) 8 43 10 6 100 103 367 0.42 (1 0.42) + (24 + 1.2) (Vo + VF )
= 6.2
23
24
12
I L pk = I o +
I L 8.8 A 2
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Io V (1 D) DTS 2 < I M > + in ] > 2Coss [(1 D)Vin ]2 n 2 Lm Vin max (1 D) DTS 2Coss I 2[ (1 D)Vin o 2 D ] Llk n = 400 (1 0.28) 0.28 10 106 2 150 1012 8 0.2 2[ (1 0.28) 400 2 0.28] 43 10 6 6.2 = 654 H
Lm <
determine Lm=630H
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13
Magnetizing current can reach pulse-by-pulse current limit during the transient. Thus, Bmax=0.15T is used to guarantee non-saturation of the transformer during transient (EER3542, Ae=109mm2).
N p min = Lm I M max 630 106 1.29 = = 49.7turns Ae Bmax 109 106 0.15
Then, Np=50 turns and Ns=8 turns The maximum flux density in the worst case scenario will be checked in STEP-8 after the current limit level is determined.
Pin Inductance Leakage 18 18 Spec. 630H 5% 45H 10% Test Condictions 100kHz, 1V Short one of the secondary windings
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1 CB
p
DTS
i dt = C
p 0
1 I o Io [ + (1 2 D )] n B n
i dt = C
0
1 I o Io [ + (1 2 Dnom )]DnomTS 30V n n 1 8 8 CB > [ + (1 2 0.34)] 0.34 10 106 = 193nF 30V 6.2 6.2 CB >
: Select CB=220nF
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14
Since Vth=0.6V, Select Rsense=0.2 ohms Then, the pulse-by-pulse current limit =3A
Bmax worst =
29
VD1 = Vin D
2 n
2 = 64V 6.2
2 = 128V 6.2
VD 2 = Vin (1 D)
2 n
VD 2 = 400 1
Considering the voltage spike, 100V and 200V diodes are selected for D1 and D2, respectively
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Design Tips
A. Unbalanced secondary winding approach (center tap winding)
I LO NS1 Np
Ids1 IP
D < 0.5
Ids1
NS 2 Np
N S1 > N S 2
I LO
The magnetizing current DC offset for some operating point can be reduced using unbalanced turns
I M .avg = I o NS 2 N (1 D) I o S1 D Np Np
I M .avg = 0 when D =
NS2 N S1 + N S 2
But, this increases current ripple in the output inductor Requires larger inductor
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Design Tips
B. External Soft-start
Only with duty cycle soft-start can there be a current overshoot during startup when the leakage inductance is very small
Vgs
IP
di Vin (1 D ) = dt Llk
IP
di Vin (1 D ) = dt Llk
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Experimental Verification
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Experimental Verification
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Experimental Verification
95 94 93 92
E ff (% )
91 90 89 88 87 86 85
25
50
75
100 Po (W)
125
150
175
200
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Conclusion
The operation principle of an asymmetric PWM halfbridge converter has been investigated
The design procedure of an asymmetric PWM halfbridge converter has been presented
The design procedure has been verified with a 192W prototype converter
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18
Appendix
Two switch forward Active clamp forward
Lo
S2 Lo D1 Vs S1 D2 Vo
Asymmetric Half-bridge
C Vs
Vc
D1 D2
Vo
S2
Vmax/Vmin=1.6~2.0 Not clamped to the input voltage and usually goes up to twice that of the input voltage. Limiting function is definitely required. Usually 2~3 and 4~6 times of the output voltage for powering diode (D1) and freewheeling diode (D2), respectively ZVS is very difficult to achieve at full load condition. (Design for ZVS at full load condition is not practical) ZVS at full light condition is relatively easy Tight tolerance is not required for the resonant components (L,C)
Usually 2~3 to 4~6 times of the output voltage for powering (D1) and freewheeling diode (D2), respectively No soft-switching
Usually about 3 to 6 times the output voltage for powering (D1) diode and freewheeling diode (D2), respectively (for center tapped transformer) ZVS is difficult to achieve at light load condition ZVS at full load condition is relatively easy Tight tolerance is not required for the resonant components (L,C) Much smaller output inductor
Other features
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Appendix
LLC resonant converter
Io Ro Lm Cr + VO -
Asymmetric Half-bridge
Q1
Lr
Vin
Q2
Control method Practically input voltage range Primary side MOSFET voltage Secondary side rectifier voltage stress Output capacitor current ripple ZVS condition
Variable frequency with fixed duty cycle (50%) Vmax/Vmin=1.2~1.4 Clamped to the input voltage 2 times the output voltage (for center tapped transformer) Almost twice the output current (peak-to-peak)
PWM with fixed frequency Vmax/Vmin=1.2~1.3 Clamped to the input voltage Usually about 3 to 6 times the output voltage for powering and freewheeling diodes, respectively (for center tapped transformer) Several tens % of output current (peak-to-peak)
ZVS is easily achieved from full load to no load condition using the energy in the magnetizing inductance No simple power limit capability such as pulseby-pulse current limit in PWM operation Requires tight tolerance of resonant components (L,C) Relatively large circulating current 38
ZVS is difficult to achieve at light load condition ZVS at full load condition is relatively easy Tight tolerance is not required for the resonant components (L,C)
Other features
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