Switch-Mode Power Supplies - SPICE Simulations and Practical Designs - EE Times2

Switch-Mode Power Supplies---SPICE Simulations and Practical Designs | EE Times
Profile | Logout Home News Opinion Messages Video Slideshows Education Events
e Planet Analog Power Management Programmable Logic Prototyping SoC Test & Measurement
Mobile Site
BREAKING NEWS
NEWS & ANALYSIS: Flexible Curved Displays to Top $27 Billion by 2023
Navigate to Related Links
Design How-To
Switch-Mode Power Supplies--SPICE Simulations and Practical Designs

Christophe P. Basso
5/10/2008 05:00 PM EDT Post a comment
NO RATINGS 1 saves RATE IT SAVED
Power Tip 63: Testing High-di/dt Power Supplies Oscilloscope Mistakes, Part 2 Dialog Mulls MEMS Market Entry Oscilloscope Mistakes, Part 1 Dialog's CEO Lays Ambitious Plans
Like
Tweet
Most Commented
Most Popular
3.2 Stability Criteria Among stability tools (Nyquist, Nichols, . . .), Bode's approach is probably the most popular owing to its simplicity. When other methods require manipulating data in the complex plane, the Bode diagram offers an immediate insight as the transfer function amplitude appears in the frequency domain. We know that a feedback system takes a portion of the output variable and compares it to a stable reference. It then further "amplifies" the error between these signals, via the loop gain, to generate a corrective action. In other words, if the output voltage deviates from its targetlet us assume it increasesthe error signal must reduce to instruct the converter to diminish its output. On the contrary, if the output voltage stays below the target, the error voltage will increase to let the converter know that there is a demand for more output voltage. The control action consists of opposing the variation observed on the regulated output, hence the term negative feedback. As the frequency increases, the converter output stage H(s) introduces further delay (we say it "lags") and its gain drops. Combined with the correction loop H(s) , a case might quickly appear where the total phase difference between the control signal and the output signal vanishes to 0. Theory thus shows that if, for any reason, both output and error signals arrive in phase while the gain loop reaches unity (or 0 dB in a log scale), we have built a positive feedback oscillator, delivering a sinusoidal signal at a frequency fixed by the 0 dB crossover point. When we compensate a power supply, the idea is not to build an oscillator! The design work will thus consist of shaping the correction circuit G(s) to make sure that (1) when the loop gain crosses the 0 dB axis, there exists sufficient phase difference between the error and the output signal and (2) G(s) offers a high
179 What? Electronics Engineers Who Cannot Solder? 134 September's Caption Contest Is Knocking on ... 126 Are We Losing the Secrets of the Masters? 113 Top 8 Tools For Building a Personal ... 94 Intel processor outperforms Nvidia, ... 94 Why Arent Our STEM Graduates Hired? 85 Intel's new CEO shakes things up 82 Get some fresh air with the June caption ... 80 Why I'm Dumping Nexus7 & Android & Buying ... 68 Tablets Are Cool, I Just Don't Use Them
Like Us on Facebook
http://www.eetimes.com/document.asp?doc_id=1273248&page_number=2[19-Sep-13 11:43:58 AM]
gain value in the dc portion to reduce the static error and the output impedance and to improve the input line rejection. This phase difference is called the phase margin (PM). How much phase margin must be selected? Usually, 45 represents the absolute minimum, but rock-solid designs aim for around 70 to 80 phase margin, offering good stability and a fast nonringing transient response. Figure 3-7 represents the loop gain of a compensated CCM buck voltage-mode converter and highlights the phase margin. We can read a PM greater than 50 and a 0 dB crossover frequency (or a bandwidth) of 4.2 kHz. Please note that PM on this drawing is read as the distance between the phase curve and the 0 line. Sometimes, in textbooks, PM is assessed as the distance between the phase curve and the -180 line. It leads to the same interpretation either way. (Click on Image to Enlarge)
EE Times on Twitter
follow us
Tweets about "from:eetimes OR #eetimes OR @eetimes"
Datasheets.com Parts Search

185 million searchable parts (please enter a part number or hit search to begin)
powered by DataSheets.com
SEARCH
Figure 3-7: The compressed loop gain of a compensated CCM voltage-mode buck converter. Note that a null phase margin at above or below the 0 dB point offers what is called conditional stability. That is, if the gain moves up or down (the phase shape remaining the same), the unity gain crossover point can coincide with a 0 phase margin, engendering oscillations. What matters is the distance between the 0 dB axis and the point at which danger can occur. This situation can be seen on the right side of Fig. 3-7 where both error and output signals are in phase (0). If the gain increased by 20 dB, we would be in trouble. . . The gain increase (or decrease in some cases) necessary to reach the 0 dB axis is called the gain margin (GM). Good designs ensure at least a 10 to 15 dB margin to cope with any gain variations, due to loading conditions, component dispersions, ambient temperature, and so on. (Click on Image to Enlarge)
Figure 3-8: In this configuration, the bandwidth did not
change, but the phase margin did. Figure 3-8 represents the same CCM buck but now featuring a reduced phase margin of 25 at the crossover frequency. This is too low. Furthermore, the phase almost hits 0 around 2 kHz. If the gain reduces by 20 dB and crosses 0 dB at that particular point, oscillations will occur, this is the conditional stability described above.
3.3 Phase Margin and Transient Response A relationship exists between the phase margin of a second-order closed-loop system and the quality coefficient Q of its transfer function [1]. If the phase margin is too small, the peaking induces high output ringing, exactly as in an RLC circuit. On the contrary, if the phase margin becomes too large, it slows down the system: the overshoot goes away but to the detriment of response and recovery speed. An equivalent quality coefficient of 0.5 brings a theoretical phase margin of 76 as highlighted in [1]. It leads to a critically-damped converter, combining response speed and lack of overshoot. Based on this statement, the converter phase margin target must be set to 70, with a worst case of 45. The CCM buck featuring a 4.3 kHz bandwidth was simulated in a transient load step together with various phase margins imposed by the compensation network. Figure 3-9 has collected all transient responses. We can see that a weak phase margin gives birth to oscillations and large overshoots: the system becomes undamped. This is obviously not an acceptable design. As the phase margin increases, the response time slows down a little, but the overshoot fades away. For a 76 phase margin, the overshoot keeps within a 0.5 percent window. (Click on Image to Enlarge)
Figure 3-9: Various step load responses versus phase margin. The undershoot depends on different parameters, including the output capacitor, but the recovery time links to the phase margin. 3.4 Choosing the Crossover Frequency The crossover frequency is chosen depending on various design factors and constraints. In a power converter, it is possible to approximate its closed-loop output impedance by the output capacitor impedance at the crossover frequency fC. Therefore, the output voltage undershoot level V p occurring during an output transient step Iout can be approximated by the following formula [2](Eq. 3-3)
where C out is the output capacitor and fc the crossover frequency. Note that this equation holds as long as the output capacitor ESR is less than the reactance of C out at the crossover frequency, implying that the capacitor is solely held responsible for the
undershoot. This condition can be expressed by (Eq. 3-4)
As Fig. 3-9 shows, the undershoot depends on Eq. (3-3), but the recovery time mostly depends on the phase margin at the crossover frequency. Equation (3-3) can help you make the decision on the crossover value once the output capacitor has been selected based on the needed ripple performance and its rms current capability, for instance. However, there are other limiting factors that you need to consider. For instance, if your converter features a RHP zero, like in CCM boost, buck-boost or flyback converters, then the crossover frequency fc cannot be higher than 30 percent of its worse-case lowest position. It quickly closes the debate! In voltage-mode operated converters, the peaking of the LC network (L or Le) also bounds the crossover frequency: trying to fix fc too close to the resonant frequency f0 of the LC network will bring obvious stability troubles given the phase lag at resonance. Make sure to select f0 at least equal to three times f0 in worse-case conditions. In absence of RHP zero, however, one-tenth to one-fifth of the switching frequency (10 percent to 20 percent of F SW ) looks like a possible target. Extending the crossover frequency can bring additional problems such as noise pick-up: a theoretical design might show adequate PM and GM at the chosen cutoff frequency, but the reduction to practice can show instability because of noise susceptibility brought by the wide loop bandwidth. Do not push the cutoff frequency beyond what you really need to avoid this problem: there is no need for a 15 kHz crossover if a 1 kHz one can do the job transient wise! 3.5 Shaping the Compensation Loop The stability exercise requires shaping the compensation circuit G(s) in order to provide adequate phase margin at the selected crossover point, together with a high gain in dc. To do so, several compensation circuits can be used, assembling poles and zeros. What we usually need is a phase boost at the crossover frequency to provide the right phase margin. This is done by forcing the loop to cross over with a -1 slope, or -20 dB/decade in the vicinity of the crossover frequency. However, the needed boost is sometimes so large that you cannot reach the crossover frequency you have in mind. You must revise your goal and adopt a more humble target. Let us review the basics about passive filters first, quickly followed by operational amplifier-based circuits. 3.5.1 The Passive Pole Figure 3-10a represents an RC circuit producing a so-called passive single-pole response. Also known as a low-pass filter, it introduces phase lag (or delay) as the frequency increases. Its Laplace transfer function has the following form (Eq. 3-5): (Click on Image to Enlarge)
The cutoff pulsation of this passive filter, that is, when the dc "gain" reduces by -3 dB, is given by the classical formula (Eq. 3-6) o = 1/RC
Figure 3-10a represents the electrical construction of such a lowpass filter whereas Fig. 3-10b shows its Bode plot. (Click on Image to Enlarge)
Figure 3-10a, b: A single-pole RC network and its frequency response. A single pole is often inserted in compensation circuits to roll off the gain at a certain point. The rate at which the amplitude goes down is -20 dB by decade. That is, after the cutoff frequency, the amplitude difference at frequencies f1 and f2, where f2 = 10 f1, will be -20 dB. On the Bode plot, this is shown as a "-1" slope, whereas a -40 dB by decade circuit (typically a second-order network) would be designated as a -2 slope. A pole corresponds to a root in the transfer function denominator D(s) . Solving for the roots gives an indication of the system stability (please see App. 2B for more details).
3.5.2 The Passive Zero If the transfer function contains a zero, it appears in the numerator N(s) . At the zero frequency, the numerator cancels and nulls the transfer function. Equation (3-7) describes the generalized form of the zero (Eq. 3-7):
Such an expression describes a 0 dB "gain" in dc, followed by a +20 dB/decade slope (a +1 slope) occurring at the zero location. The phase is now positive, as seen in Fig. 3-11a. This is the property of a zero that actually "boosts" the phase, compared to a pole that "lags" the phase. Zeros are thus introduced in G(s) to compensate for excessive phase lag occurring in the power stage response. Back to the passive circuits, Fig. 3-11b represents a high-pass filter. The transfer function of such a simple RC circuit also contains one pole and one zero, but placed at the origin. It looks like (Eq. 3-8) (Click on Image to Enlarge)
where the cutoff pulsation is the same as Eq. (3-6). (Click on Image to Enlarge)
Figure 3-11a: A single zero network and its frequency response.
(Click on Image to Enlarge)
Figure 3-11b, c: A high-pass RC network and its frequency response. This filter features a low-frequency asymptote of a +20 dB/decade slope (a +1 slope) and high-frequency gain of 1 or 0 dB. Here we have a zero located at the origin nulling the transfer function in dc (s = 0) as Fig. 3-11c portrays. In all the above equations, a negative numerator root sign signifies a left half-plane zero (LHPZ) position. In some converters, a right half-plane zero (RHPZ) can exist and stability is jeopardized.
3.5.3 Right Half-Plane Zero The RHPZ is not part of the loop shaping toolbox. You actually undergo a RHPZ rather than create it for stability purposes! Its general form looks pretty much like Eq. (3-7) except that a negative sign appears (Eq. 3-9a): G(s) = 1 - s/o A RHPZ can be formed by using the circuit in Fig. 3-12a where we can see an active high-pass filter whose inverting output (the negative sign) is summed with the input. The transfer function is easy to derive (Eq. 3-9b): (Click on Image to Enlarge)
with Eq. (3-6) again ruling the cutoff frequency. (Click on Image to Enlarge)
Figure 3-12a: A RHPZ artificially created via an active highpass filter and an adder. (Click on Image to Enlarge)
Figure 3-12b: The Bode plot looks like a zero, but the phase lags. As Fig. 3-12b shows, the gain output looks like a traditional zero: a +1 slope of 20 dB/decade with a cutoff frequency imposed by R 1 and C 1. The difference lies in the phase diagram. Instead of a phase boost, the perfidious RHPZ gives you a phase lag and further degrades the phase margin you strived to save. Right halfplane zeros usually exist in indirect energy transfer converters where energy is first stored (on time) prior to being dumped in the output capacitor (off time). If we take the example of the boost converter, the average diode current equals the load dc current. This diode current Id actually equals the inductor current IL during the off time, or d'T sw. Its average value can thus be written (Eq. 310): (Click on Image to Enlarge)
Suppose we have a 40 percent duty cycle in a CCM-operated boost converter. A sudden load step occurs which, via the feedback loop, pushes the duty cycle to 50 percent. The current in the inductor increases accordingly, but what about the average output current in the diode? It drops because as d' = 1 - d, if d increases, d' shrinks and the output capacitor first discharges instead of increasing! The change goes in the wrong direction until the current builds up in the inductor, bringing the average diode current to its right value and finally lifting up the output voltage. Since it is a closed-loop system, the converter becomes unstable. There is nothing you can do about it, except to severely roll off the bandwidth in order to not undergo the RHPZ additional phase lag. The RHPZ frequency position unfortunately changes with the duty cycle. The typical rule of thumb recommends that you select a crossover frequency to be around one-third of the lowest RHPZ position. If you try to increase the bandwidth closer to the RHPZ location, you might encounter a problem as the phase lag becomes too large. The RHPZ occurs in CCM operated converters such as buck-boost, boost, or flybacks. The RHPZ disappears in DCM although some academic studies state the presence of one in DCM, but relegated to higher frequencies. Figure 3-13 plots a converter featuring a RHPZ. In the presence of a load step, the duty cycle suddenly increases. As a result, the inductor current increases as the switch stays closed for a longer time. But as d' has diminished, the diode average current now goes down. This situation translates into a decreasing output voltage, the opposite of what the loop is asking for. Then the average current eventually catches up with the inductor current, and the output voltage rises. The above lines showed how passive poles and zeros help to shape the loop gain. Unfortunately, used on their own, they do not provide any dc gain, which is badly needed for a low static error, good input rejection, and so on. Associated with operational amplifiers (op amps), these so-called active filters provide the necessary transfer function together with the required
amplification. Three different types have been identified. (Click on Image to Enlarge)
Figure 3-13: A RHPZ effect in a boost converter operating in CCM.
p. 2, Switch-Mode Power Supplies, Copyright McGraw-Hill, 2008

EMAIL THIS PRINT COMMENT < PREVIOUS PAGE 2 / 3 NEXT >
Comments
VIEW COMMENTS: NEWEST FIRST | OLDEST FIRST | THREADED VIEW
Be the first to post a comment regarding this story.
Sign up for EE Times newsletter
Get the iPhone App
Terms of Service | Privacy Statement | Copyright 2013 UBM Tech, All rights reserved

Switch-Mode Power Supplies - SPICE Simulations and Practical Designs - EE Times2

Uploaded by

Document Information

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

Switch-Mode Power Supplies - SPICE Simulations and Practical Designs - EE Times2

Uploaded by

Copyright:

Available Formats

Switch-Mode Power Supplies---SPICE Simulations and Practical Designs | EE Times

Navigate to Related Links