Chapter

Power Dissipation in Modern FPGAs

2.1 CMOS Technology Scaling Trends and Power Dissipation in VLSI Circuits 2.2 Dynamic Power in FPGAs 2.3 Leakage Power in FPGAs
2.3.1 CMOS Device Leakage Mechanisms 2.3.2 Current Situation of Leakage Power in Nanometer FPGAs The tremendous growth of the semiconductor industry in the past few decades is fueled by the aggressive scaling of the semiconductor technology following Moores law. As a result, the industry witnessed an exponential increase in the chip speed and functional density with a signicant decrease in power dissipation and cost per function [39]. However, as complementary metal oxide semiconductor (CMOS) devices enter the nanometer regime, leakage current is becoming one of the main hurdles to Moores law. According to Moore, the key challenge for continuing process scaling in the nanometer era is leakage power reduction [40]. Thus, circuit designers and CAD engineers have to work hand in hand with device designers to deliver high-performance and low-power systems for
Low-Power Design of Nanometer FPGAs: Architecture and EDA Copyright 2010 by Elsevier, Inc. All rights of reproduction in any form reserved.

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future CMOS devices. In this chapter, the power dissipation problem is discussed in the VLSI industry in general and in FPGAs in particular.

2.1 CMOS TECHNOLOGY SCALING TRENDS AND POWER DISSIPATION IN VLSI CIRCUITS
The main driving forces that govern the CMOS technology scaling trend are the overall circuit requirements: the maximum power dissipation, the required chip speed, and the needed functional density. The overall device requirements such as the maximum MOSFET leakage current, minimum MOSFET drive current, and desired transistor size are determined to meet the overall circuit requirements. Similarly, the choices for MOSFET scaling and design, including the choice of physical gate length Lg and equivalent oxide thickness of the gate dielectric tox , and so forth, are made to meet the overall device requirements. Figure 2.1 depicts the scaling trend for the CMOS feature size across several technology generations as well as some future predictions according to the semiconductor road map published by the International Technology Roadmap for Semiconductors (ITRS) [41].
600 500 Feature size (nm) 400 350 300 200 100 0 1993 1995 1997 1999 2001 2004 2007 2010 2013 2016 Year

500

250 180 130 90 65 45 32 22

FIGURE 2.1 Gate length scaling of CMOS technologies [41].

2.1 CMOS Technology Scaling Trends and Power Dissipation in VLSI Circuits 33

There are two common types of scaling trends in the CMOS process: constant eld scaling and constant voltage scaling. Constant eld scaling yields the largest reduction in the power-delay product of a single transistor. However, it requires a reduction in the power supply voltage as the minimum feature size is decreased. Constant voltage scaling does not suffer from this problem, therefore, it provides voltage compatibility with older circuit technologies. The disadvantage of constant voltage scaling is the electric eld increases as the minimum feature length is reduced, resulting in velocity saturation, mobility degradation, increased leakage currents, and lower breakdown voltages. Hence, the constant eld scaling is the most widely used scaling approach in the CMOS industry. Table 2.1 summarizes the constant eld scaling in the CMOS process. Table 2.1 Constant Field Scaling of the CMOS Process Parameter
Gate length Gate width Field Oxide thickness Substrate doping Gate capacitance Oxide capacitance Circuit delay Power dissipation Area Power density

Symbol
L W tox Na CG Cox td Pd A P /A

Constant Field Scaling

1/ 1/ 1 1/ 1/ 1/ 1/2 1 1

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To maintain the switching speed improvement of the scaled CMOS devices, the threshold voltage VTH of the devices is also scaled down to maintain a constant device overdrive. However, decreasing VTH results in an exponential increase in the subthreshold leakage current, ID 10
VGS VTH +VDS S

(2.1)

where S = nkT q ln 10. Moreover, as the technology is scaled down, the oxide thickness tox is also scaled down, as shown in Table 2.1. The scaling down of tox results in an exponential increase in the gate oxide leakage current. As a result of the continuous scaling of VTH and tox , the contribution of the total leakage power to the total chip power dissipation is increasing notably. The contribution of leakage power is expected to exceed 50% of the total chip power by the 65 nm CMOS process [41], as shown in Fig. 2.2.
500 350 250 180 130 90 65 45 100 22 Technology node (nm)

1 Normalized power

Dynamic power

0.01

0.0001 Leakage power

0.0000001 1990

1995

2000

2005 Year

2010

2015

2020

FIGURE

2.2 Leakage power contribution to the total chip power [41].

2.3 Leakage Power in FPGAs 35

2.2 DYNAMIC POWER IN FPGAs

FPGAs provide recongurability by using redundant logic and switches inside the chip. As a result, FPGA design dynamic power dissipation is much larger than their application-specic integrated circuit (ASIC) counterparts. In a study by Kuan and Rose [42], the authors performed a quantitative study to compare the dynamic power dissipation in FPGAs to that of ASICs, and the results are listed in Table 2.2. The results in Table 2.2 suggest that, on average, FPGAs consume 14 more dynamic power than ASICs when the circuits contain only logic. However, when the design uses some of the hard blocks inside the FPGA, e.g., memory blocks and multipliers, the dynamic power gap is reduced between FPGAs and ASICs, with multipliers being the main factor in reducing FPGA power dissipation. The main reason for this reduction in the power gap is due to the fact that using the hard macros inside the FPGAs means fewer logic resources are used, hence, less power is being dissipated. As a result, it can be concluded that FPGAs are less efcient in terms of power dissipation when compared to ASICs. In order for FPGAs to be able to compete with ASICs, extensive work is still needed to reduce FPGA dynamic power dissipation.

2.3 LEAKAGE POWER IN FPGAs 2.3.1 CMOS Device Leakage Mechanisms

There are six short-channel leakage current mechanisms in CMOS devices. Figure 2.3 summarizes the leakage current types that affect state-of-the-art CMOS devices [43]. I1 is the reverse-bias pn junction leakage; I2 is the subthreshold leakage; I3 is the oxide tunneling current; I4 is the gate current due to hot-carrier injection; I5 is the gateinduced drain leakage; and I6 is the channel punchthrough current. Currents I2 , I5 , and I6 are OFF-state leakage currents, while I1 and I3 occur in both ON and OFF states.

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Table 2.2 Dynamic Power Consumption Ratio (FPGA/ASIC) [42] Circuit

booth rs_cncodcr cordic18 cordic8 desarea des_perf fir_restruct mac1 aesl92 tir3 diffeq diffeq2 molecular rs_dccodcrl rs_decoder2 atm aes aes_inv ethernet serialproc fir24 pipe5proc raytracer Geomean

Logic Only
26 52 6.3 5.7 27 9.3 9.6 19 12 12 15 16 15 13 11 14

Logic and DSP Logic and Memory Logic, Memory, and DSP
7.5 12 12 16 16 11 12 15 13 12 16 16 14 5.3 8.2 8.3 7.1

2.3 Leakage Power in FPGAs 37

Gate

I3 , I4
Source Drain

n1

I2 I6 I1

n1

p-well

I5
Body

FIGURE 2.3 Leakage current mechanisms of deep submicron devices [43].

I4 can occur in the OFF state, but more typically occurs during the transistor transition [43]. The main sources for leakage power dissipation in current CMOS technologies are the subthreshold leakage and gate oxide leakage currents. There are two main components for the reverse-bias pn junction leakage I1 : minority carrier diffusion/drift near the edge of the depletion region and electron-hole pair generation in the depletion region of the reverse-biased junction. I2 ows between the source and drain in a MOSFET when the gate voltage is below Vth . I3 occurs by electrons tunneling from the substrate to the gate and also from the gate to the substrate through the gate oxide layer. I4 occurs due to electrons or holes gaining sufcient energy from the applied electric eld to cross the interface potential barrier and enter into the oxide layer. I5 is due to the high eld effect in the drain junction of the MOSFET. Because of the proximity of the drain and the source, the depletion regions at the drain-substrate and source-substrate junctions extend into the channel. Channel length reduction and increase in the reverse bias across the junctions push the junctions nearer to each other until they almost merge, thus leading to the punchthrough current I6 .

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Of these six different leakage current mechanisms experienced by current CMOS devices, subthreshold and gate leakage currents are the most dominant leakage currents. Furthermore, the contribution of subthreshold leakage current to the total leakage power is much higher than that of gate leakage current, especially at above room temperature operating conditions. The contribution of gate leakage current to the leakage power dissipation is expected to increase signicantly with the technology scaling, unless high-k materials are introduced in the CMOS fabrication industry [41].

2.3.2 Current Situation of Leakage Power in Nanometer FPGAs

For FPGAs to support recongurability, more transistors are used than those used in an ASIC design that performs the same functionality. Consequently, leakage power dissipation in FPGAs is higher than that in their ASIC counterpart. It was reported in a study by Kuon and Rose [42] that on average, the leakage power dissipation in FPGA designs is almost 5.4 times that of their ASIC counterparts under worst-case operating conditions. The excess leakage power dissipated in FPGAs is mainly due to the programming logic that is not present in ASIC designs. A study of the leakage power dissipation in a 90-nm CMOS FPGA was performed by Tuan and Lai [44], the results of which are summarized in Table 2.3. By comparing the average leakage power dissipation of a typical 90-nm CMOS FPGA at 25 C and 85 C, it can be seen that the average leakage power increases by four times. Moreover, the results in the rst column are for a utilization of 75%; hence, the leakage power dissipation for a 1000-CLB FPGA would be in the range of 4.2 mW. If these FPGAs are to be used in a wireless mobile application, which has a typical leakage current of 300 A, then the maximum number of CLBs that can be used would be 86 CLBs for the 25 C and 20 CLBs for the 85 C.

2.3 Leakage Power in FPGAs 39

Table 2.3 FPGA Leakage Power for Typical Designs and DesignDependent Variations [44] T
25 C 85 C

Typical PLEAK (avg. Input Data; UCLB = 75%)

4.25 W/CLB 18.9 W/CLB

Best-Case Input Data

12.8% 31.1%

Worst-Case Input Data

+13.0% +26.8%

In addition, the dependence of leakage on the input data increases signicantly with the temperature. This can be deduced from Table 2.3 as the variation due to the worst and best case input vectors change from 13% at 25 C to approximately 28% at 85 C. Furthermore, in another experiment conducted by Tuan and Lai [44], it was found out that for a 50% CLB utilization, 56% of the leakage power was consumed in the unused part of the FPGA. Hence, in future FPGAs, these unused parts have to be turned down to reduce this big portion of leakage power dissipation.