CENTURION INSTITUTE OF TECHNOLOGY, BHUBANESWAR Stream:- M.

Tech VLSI Subject:- VLSI System and architecture Faculty:- Shreetam Behera T1. GABlaauw and F P Brooks, Computer Architecture: Concepts and D EvolutionAddison 1997 Computer organization and R1. A Patterson and JWesley, L Hennessy, Design:Hardware/Software interface Second Edition, Margan Kaufmann, 1998 Books to be followed: R2. D A Patterson and I L Hennessy, Computer Architecture: A Quantitative approach,Second edition, Margon Kaufmann, 1996 T2. W. Stallings, Computer Organization and architecture: Designing for Performance,Fourth Edition, PH, 1996 Exp. date Module Lect No. Topics Contents Sources of class Lect-1 Behavior and Architecture Behavior and Architecture CISC Architecture Concepts CISC Architecture Concepts CISC Architecture Concepts CISC Architecture Concepts Dedicated and Programmable VLSI architectures Instruction sets and through enhancement techniques (Parallelism. pipelining. cache, etc.) Typical CISC instruction set and its VLSI implementation Rtlevel optimization through hardware flow charting Design of the execution unit, 08-02-13 Web

Lect-2

08-05-13

R-2 Ch(2,3)

Lect-3 1 Lect-4 Lect-5 Lect-6

08-14-13 R-2 Ch(3) T-1 Ch(3,4,5, 6) T-2 Ch(15.1) T-2 Ch(15.215.3) T-2 Ch(16.116.3) T-1 Ch(2.1) T-4 Ch(13) T-1 Ch(13) T-1 Ch(13)

08-26-13 09-02-13 09-11-13

Lect-7

Design of the control part (micro programmed and hardwired) Instruction boundary Handling exceptions interrupts, immediate interrupts and traps. RISC Architecture concepts Typical RISC instruction set and its VLSI implementation Execution pipeline Benefits and problems of pipelined execution Hazards of various types of pipeline stalling

09-13-13

Lect-8 Lect-9

09-16-13 09-18-13 09-23-13 09-25-13

RISC Architecture concepts RISC Architecture Lect-10 concepts RISC Architecture Lect-11 concepts

Lect-12

RISC Architecture concepts

Concepts of scheduling (Static and dynamic) and forwarding to reduce /minimize pipeline stalls Exceptions in pipelined processors Concepts of scheduling (Static and dynamic) and forwarding to reduce /minimize pipeline stalls Exceptions in pipelined processors Typical DSP instruction set and its VLSI implementation

09-27-13

T-4 Ch(13)

Lect-13

RISC Architecture concepts

10-07-13

T4Ch(13)

Lect-14

DSP architecture concepts

10-11-13

Web

Dedicated Hardware Example and Case studies Lect-15 Architecture Concepts 3 Dedicated DSP Lect-16 architecture Concepts Dedicated DSP Lect-17 architecture Concepts Scheduling and Resource allocation Conventional Residue number

10-25-13

Web

10-28-13

Web

11-01-13

Web