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Chapitre 4
Copyright
Ce chapitre est extrait des documents prpars dans le cadre de ST Ecole. Intervenants dans le programme ST Ecole:
Abdellatif BEN RABAA (ENIT) Chadlia JERAD (ENSI) Emir DAMERGI (INSAT) Halim KACEM (STMicroelectronics) Hanen BEN FRAJ (ISI) Younes LAHBIB (ENISOU, ESTI)
Outline
Introduction Cortex-M3 Cortex-M3 based MCUs: The STM32F10x Family STM32 Programming STM32VL Discovery Kit
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Also develop technologies to assist with the design-in of the ARM architecture
Software tools, boards, debug hardware, application software, bus architectures, peripherals etc.
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Why ARM?
One of the most licensed and thus widespread processor cores in the world
Used in PDA, cell phones, multimedia players, handheld game console, digital TV and cameras 75% of 32-bit embedded processors
Used especially in portable devices due to its low power consumption and reasonable performance
LM3S8x
Cortex-R Cortex-M
Thumb-2 NVIC MPU 3 stages pipeline Thumb/Thumb-2 MPU FP Unit 8 stages Pipeline
Analog Devices
13 stages Pipeline Multi-core (1-4)
Toshiba Samsung
1,6 DMIPS
Outline
Introduction Cortex-M3 Cortex-M3 based MCUs: The STM32F10x Family STM32 Programming STM32VL Discovery Kit
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Cortex-M3 Processor
Hierarchical processor integrating core and advanced system peripherals
Interrupt controller: -1 to 240 interrupts. - 256 Priority levels - NMI -SysTick (Porting !!!) CM3 Core: Harvard (Separate Busses) 32 Bits Register & ALUs.
Embedded Trace MacroCell Wakup Int. controller: Wakeup from Sleep modes throuht interrupts & exceptions
WIC
Optional Memory Protection Unit (8 regions) Integrated Trace module: Low cost (2 wires) 8 Hardware Breakpoints Multi layer Bus Matrix (Parallel transfers between core, memory, & peripherals 9
Cortex-M3 Processor
Write Buffer
Used to decouple writes to memory Data is placed in the buffer so the processor can continue execution Data is written to memory when possible
Instruction Bus
Core
I D
Write Buffer
Data Bus
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12
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Allows access to APSR, EPSR and IPSR special purpose registers xPSR stored on stack during exceptions Condition code flags
N = Negative result from ALU Z = Zero result from ALU C = ALU Operation carried out V = ALU Operation overflowed Q = Saturated math overflow
IT/ICI Bits
Contain IF-THEN base condition code and Interrupt Continue information
ISR Number
ISR contains information on which exception was pre-empted
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These technologies can dramatically improve data (SRAM) memory utilization, potentially enabling designers and users to reduce the amount of SRAM required and dramatically impacting silicon usage
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long (32) char (8) long (32) char (8) char (8) char (8) char (8) long
long (32) long (32) char (8) char (8) char (8) long (32) int (16)c int (16) long
Data aligned
int (16) long (32) int (16)c int (16) long (32) char (8)
char (8)
long (32)
When an unaligned transfer takes place, it is broken into separate transfers and as a result it takes more clock cycles for a single data access and might not be good for situations in which high performance is required. Unaligned access: Better memory use but Performance degradation
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byte number
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Byte_offset = 0x40000303 - 0x40000000 = 0x303 0x42000000 + ( 0x303*32) + (15 * 4) = 0x4200609C =bit_word_addr Reading address 0x4200609C returns the value of bit 15 of the byte at address 0x40000303. Writing to address 0x4200609C has the same effect as a readmodify-write operation on bit 15 of the byte at address 0x40000303.
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0x22000000 + ( byte_offset*32) + (bit_number * 4) = 0x22006008 ( byte_offset*32) + (bit_number * 4) = 0x6008 ( byte_offset = 0x300) +and (bit_number =2 ) Accessing address 0x22006008 has the same effect as accessing the bit 2 of the byte at SRAM address 0x20000303.
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The NVIC supports up to 240 dynamically reprioritizes interrupts each with up to 256 levels of priority
1-240 Interrupts + NMI
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PUSH
ISR
R0-R3 ; R12 R15 (Program Counter) R14 (Link register) PSR (Registre dtat)
For the ARM7 architecture ( Cortex-M predecessor), The PUSH and POP operations were coded in assembler and they last 26 and 16 cycles respectively
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ISR 1
POP 16
PUSH 26
ISR 2
POP 16
Cortex-M3
Interrupt handling in HW
PUSH 12
ISR 1 6 6 CYCLES
ISR 2
POP 12
ARM7 26 cycles from IRQ1 to ISR1 entered 42 cycles from ISR1 exit to ISR2 entry 16 cycles to return from ISR2
Cortex-M3 12 cycles from IRQ1 to ISR1 entered 6 cycles from ISR1 exit to ISR2 entry 12 cycles to return from ISR2
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IRQ1 IRQ2 42 CYCLES ARM7 ISR 1 POP 16 PUSH 2 26 ISR 2 6 POP 12 ISR 2 POP 16
Cortex-M3
ISR 1
POP
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7-18 CYCLES
Cortex-M3 ARM7 Load Multiple uninterruptible, and hence the core must complete the POP and the full stack PUSH POP may be abandoned early if another interrupt arrives If POP is interrupted it only takes 6 cycles to enter ISR2 ( Equivalent to Tail -chaining)
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Late Arrival
PUSH 26 ISR 1 6
TailChaining
ISR 1
POP 16
ISR 2
POP 16
ISR 2
POP 12
ARM7 26 cycles to ISR2 entered Immediately pre-empted by IRQ1 and takes a further 26 cycles to enter ISR 1. ISR 1 completes and then takes 16 cycles to return to ISR 2.
Cortex-M3 Stack push to ISR 2 is interrupted Stacking continues but new vector address is fetched in parallel 6 cycles from late-arrival to ISR1 entry. Tail-chain into ISR 2
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Example
PUSH
PUSH
NMI
ISR 1
POP
Cortex-M3
ISR 2
ISR 3
POP
ISR 2 Starts
Push for ISR1 begins Pre-empted by NMI New instruction fetch in parallel minimises time to NMI
Following NMI processor tail-chains into ISR1 ISR2 Completed Pop only occurs on return to Main
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In STM32F10x the SysTick clock can be: CPU clock or CPU clock/8 (provided externally by the Reset Clock Control)
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JTAG
SWD
Debugging features still kept whilst the core entered low power mode
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ETM
Outline
Introduction Cortex-M3 Cortex-M3 based MCUs: The STM32F10x Family STM32 Programming STM32VL Discovery Kit
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The Microcontroller
Microcontroller or MCU (MicroController Unit) :
a small computer on a single integrated circuit.
Processor Core
Memory (RAM)
System BUS
Bridge
Programmable I/O Peripherals (Parallel, Serial (UART, SPI, CAN, I2C), Analog (ADC, DAC), Timers,
+ Size (High Integration) + Cost ( <1$ for large qty) + Energy Consumption
Decode Unit
UAL + Registers
Debug component s
Data Bus Flash Memory
NVIC
Interface
Provided by ARM
Instruction Bus
MPU (optional)
Bus Matrix
Input/Output Peripherals
System Peripherals
SRAM memory
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STM32 Series
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103 102
72 48 36 24
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Nested Vectored Interrupt Controller (NVIC) w/ 43 maskable IT + 16 prog. priority levels Embedded Memories : SRAM: up 96Kbytes CRC calculation unit 7 Channels DMA Power Supply with internal regulator and low power modes : 2V to 3V6 supply 4 Low Power Modes with Auto Wake-up Integrated Power On Reset (POR)/Power Down Reset (PDR) + Programmable voltage detector (PVD) Backup domain w/ 20B reg Up to 72 MHz frequency managed & monitored by the Clock Control Rich set of peripherals & IOs Embedded low power RTC with VBAT capability Dual Watchdog Architecture 5 Timers w/ advanced control features (including Cortex SysTick) 9 communications Interfaces Up to 80 I/Os (100 pin package) w/ 16 external interrupts/event Up to 2x12-bits 1Msps ADC w/ up to 16 channels and Embedded temperature sensor w/ +/-1.5 linearity with T FLASH: up 1Mbytes
Up to 96kB SRAM
20B Backup Regs Reset Clock Control ARM Peripheral Bus (max 36MHz)
PLL
DMA 7 Channels
RTC / AWU
CRC
1x 1616-bit PWM
Synchronized AC Timer
Bridge Bridge
1x USB 2.0FS 1x bxCAN 2.0B 2x USART/LIN Smartcard / IrDa Modem Control 1x SPI
3x 16-bit Timer ARM Peripheral Bus Independent Watchdog Window Watchdog 2x 12-bit ADC 16 channels / 1Msps Temp Sensor
(max 72MHz)
Up to 16 Ext. ITs
2x I2C
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0xE000 0000
Boot modes:
Depending on the Boot configuration
Embedded Flash Memory System Memory Embedded SRAM Memory
BOOT Mode Selection Pins
Reserved
Reserved
0x4000 0000
Peripherals Reserved
Flash
0x0801 FFFF
Aliasing User Flash is selected as boot space SystemMemory is selected as boot space Embedded SRAM is selected as boot space 42
BOOT1
0x0800 0000
BOOT0
x 0
0 1 1
0x2000 0000
SRAM Reserved
0x0000 0000
CODE
STM32F10x:Boot Modes
Boot mode = user Flash: For finalized debuged and tested applications where update is not necessary (example: Washing machine). Boot mode = System Memory: For applications where firmware update is performed frequently (example: Satellite receiver, Playsattion, etc). The internal boot ROM memory contains the Bootloader (programmed by ST in production) used to re-program the FLASH. The CPU executes Data packets the boot loader: (code) 1) Data packets containing code are Received through through serial peripheral (UART).
CPU
UART
Bus Matrix
2) The Flash is reprogrammed with the new received code Boot mode = SRAM
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I-bus
CORTEX-M3 Master 1
D-bus
FLASH
BusMatrix
System
SRAM Slave
APB2 AHB
GP-DMA Master 2
Arbiter
AHB-APB2 AHB-APB1
Bridges APB1
GPIOA,B,C,D,E - AFIO USART1- SPI1 - ADC1,2 TIM1 - EXTI USART2,3 - SPI2 - I2C1,2 TIM2,3,4 - IWDG WWDG USB CAN BKP PWR
VDDA domain
VDD domain
I/O Rings STANDBY circuitry (Wake-up logic, IWDG, RCC CSR reg) Voltage Regulator
V18 domain
VSS VDD
Backup domain
LSE crystal 32K osc BKP registers RCC BDCR register RTC
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Integrated POR / PDR circuitry guarantees proper product reset when voltage is not in the product guaranteed voltage range (2V to 3.6V)
No need for external reset circuit
Vtrh Vtrl
POR
40mv hysteresis
PDR
Tempo 2ms
Reset
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Detector
Enabled by software Monitor the VDD power supply by comparing it to a threshold Threshold configurable from 2.2V to 2.9V by step of 100mV Generate interrupt through EXTI Line16 (if enabled) when VDD < Threshold and/or VDD > Can be used to generate a warning message and/or put the MCU into a safe state
VDD
PVD Threshold
100mv hysteresis
PVD Output
Threshold
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power switch
VDD
ANTI_ TAMP
20 byte data
RTC
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Outline
Introduction Cortex-M3 Cortex-M3 based MCUs: The STM32F10x Family STM32 Programming STM32VL Discovery Kit
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Cortex-M3 exceptions
Low-level & API functions to Perform basic operations offered by the peripheral 53
main.c #include "stm32f10x.h int main(void) { /* Setup STM32 system (clock, PLL and Flash configuration) */ SystemInit(); /* main program*/ ... GPIO_WriteBit(GPIOD, GPIO_Pin_1, Bit_SET); }
stm32f10x_conf.h
/* Includes ----------------------------------------------------------------*/ /* Uncomment the line below to enable peripheral header file inclusion */ /* #include "stm32f10x_adc.h" */ /* #include "stm32f10x_bkp.h" */ /* #include "stm32f10x_can.h" */
stm32f10x.h
/* Uncomment the line below according to the target STM32 device used in your application */ #if !defined (STM32F10X_LD) && !defined (STM32F10X_MD) && !defined (STM32F10X_HD) /* #define STM32F10X_LD */ /*!< STM32 Low density devices */ /* #define STM32F10X_MD */ /*!< STM32 Medium density devices */ #define STM32F10X_HD /*!< STM32 High density devices */ #endif
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Coding conventions
All firmware is coded in ANSI-C
Strict ANSI-C for all library peripheral files
PPP is used to reference any peripheral acronym, e.g. TIM for Timer. Registers & Structures
STM32F10x registers are mapped in the microcontroller address space
FW library registers have the same names as in STM32F10x Datasheet & reference manual.
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2
Optional step
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RCC_APB2PeriphClockCmd
( RCC_APB2Periph_GPIOC, ENABLE );
GPIO_InitStructure.GPIO_Pin = GPIO_InitStructure.GPIO_Speed = GPIO_InitStructure.GPIO_Mode =
stm32f10x_conf.h
/* Includes ----------------------------------------------------------------*/ /* #include "stm32f10x_adc.h" */ /* #include "stm32f10x_bkp.h" */ /* #include "stm32f10x_can.h" */ #include "stm32f10x_NVIC.h"
Programming interrupts
1) Uncomment the NVIC header file in the stm32f10x_conf.h (if commented)
main.c
#include "stm32f10x.h int main(void) { /* Setup STM32 system (clock, PLL and Flash configuration) */ SystemInit();
2) 3)
Declare the NVIC structure Define the peripheral generating the interrupt: For the complete STM32 Devices
IRQ Channels list, refer to stm32f10x.h file
NVIC_InitTypeDef NVIC_InitStructure;
/* main program*/ ...
4)
5) 6)
Programming interrupts
stm32f10x_It.c #include "stm32f10x_it.h" . void PPPx_IRQHandler(void) { // code Clearpendingbit ( ) }
The function prototype must be declared In the stm32f10x_it.h Dont forget to clear the interrupt bit
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Outline
Introduction Cortex-M3 Cortex-M3 based MCUs: The STM32F10x Family STM32 Programming STM32VL Discovery Kit
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