U Proccessors

Computer
An electronic equipment that performs high-speed arithmetic, logical or transfer operations or that assembles, stores, correlates, or otherwise processes information. Hardware + Software
EXAMPLE
Addition Function is is programmed by dedicated the interconnection A 4-bit adder circuit a specialized, computer of wires Computer Elements are Logic Gates
Early Computer - ENIAC

(Electronic Numerical Integrator and Computer)
1946, Univ. of Pennsylvania Constructed by Eckert and Mauchly 30 tons 1500 sq ft 18,000 Vacuum Tubes Programmed by connecting:
switches and cables
6000 different switches and cables!
HARDWARE PROGRAMMABLE
Stored Program Concept

John von Neumann (Univ. of Penn.), A.W. Burks, H.H. Goldstein - wrote paper describing Stored Programs Based on Theoretical Mathematical model, Turing Machine, Alan Turing, 1936
Simple type of computer
works by reading/writing symbols on tape tape can move left or right
Finite State Machine As powerful (in theory) as any possible computer Still Used in Computability Theory, find out what they cant do
Charles Babbage also proposed a mechanical device that could
store a program, Analytical Engine in 1822

Never constructed (although he tried)
First Stored Program Computer - EDVAC

(Electronic Discrete Variable Automatic Computer)
Completed in 1952 Storage: 1000 words 1 word=10 decimal digits Programmed using Paper Tape
Sequential Storage
Random Access Core Developed

Random Access
SOFTWARE PROGRAMMABLE
Modern Computer Model
CPU - Central Processing Unit = Microprocessor

arithmetic, logical, synchronization functions
Memory - Stores Information (DRAM, ROM)

CPU instructions and Data
I/O - Input/Output Devices - Peripherals (KBD, PRN)

Interface to Outside World (humans, other machines)
Bus - Set of Parallel wires (Address Bus, Data Bus)

Transmit instructions/data between CPU/Memory/IO
Fetch and Execute Cycle

1. CPU issues: (FETCH)
Memory Read Signal on Control Bus Location of Desired Memory Data on Address Bus
2.
Memory issues:
(FETCH)
Data Valid Signal on Control Bus Actual Memory Data on Data Bus
3.
CPU Stores Data Internally
(FETCH)
Contains Registers
4. CPU Interprets Data as an Instruction (FETCH/EXECUTE*)

Instruction Decoder Circuit
5.
CPU Performs the Instruction (EXECUTE)
May Require more Memory Accesses *Some consider step 4. To be part of fetch; others part of Execute May Require Interaction with Peripherals
Quantifying Memory
Measured in the quantity of BInary digiT (BIT)
1 nybble 1 byte 1 word 1 doubleword 1 quadword 1 paragraph 1 page 1 segment (max) = = = = = = = = 4 bits 8 bits 16 bits 32 bits 64 bits 16 256 bytes 65,636 bytes
Standard
Machine Dependent bytes (8086)
Capacity Measures
1 kilobyte 1 megabyte 1 gigabyte 1 terabyte (kB) (MB) (GB) (TB) = = = = 210 bytes 220 bytes 230 bytes 240 bytes
Inside the CPU - Arithmetic Logic Unit

(ALU)
Combinational Logic Circuit

Two Classes of Inputs:
Control Data
Two Classes of Outputs

Status Data
General Arithmetic Circuit

- Attempt to Share logic Example - Purely combinational - data path between registers - 3-bit ALU A0 B0 0 1 2 3 s1 s0 Cin FA S Cout C0
X Y
A1 B1 0 1 2 3 s1 s0 X Y Cin FA S Cout C1
A2 B2 0 1 2 3 s1 s0 X Y Cin FA S Cout C3 C2
S1 S0
Arithmetic Logic Unit (ALU)

In a higher level diagram:
ALU
n
n+1
CLK S1 S0
Inside the CPU - Control Unit

FSM - Finite State Machine
Generates Control Signals
External - Bus Signals Internal - Register Load/Clear; ALU Control
Synchronization
Controls when to Fetch/Execute Generates Timing Signals Handles External Events - Interrupts
Generally Composed of Subcircuits

Bus Controller Memory Controller Cache Controller
Computer Organization
Principle Components
CPU - (Central Processing Unit)
Fetch/Execute Machine
Main Memory
An Array of Storage Locations for Bits Data and Instructions Stored Here
Secondary Storage
Memory that is Cheap Memory that is Slow
I/O Devices - (Input/Output)

Human and Computer to Communication Computer and Other Device Communication
Intel x86 Microprocessors

CPU Name 8080 8086 80286 80386 80486 Pentium Pentium Pro Pentium MMX Pentium II Celeron Pentium III Year Intro. 1974 1978 1982 1985 1989 1994 1995 1997 1998 1998 1999 Int. CPU Clock 2-3 MHz 5-10 MHz 6-16 MHz 16-33 MHz 25-50 MHz 60-200 MHz 150-200 MHz 133-266 MHz 233-500 MHz 266-500 MHz 450-600 MHz # Trans. Addr. Pins Data Pins 4500 8 16 29000 16 20 130000 16 24 275000 32 32 1.2M 32 32 3.1M 64 32 5.5M 64 36 64 32 7.5M 64 7.5M 64 64
Intel x86 Microprocessors

8086 - 20 bit Addr. Bus - 1MB of Memory 80286 - 24 Addr. Bus - Added Prot. Mode 80386 - 32 bit regs/busses - Virtual 86 Mode 80486 - RISC Core - L1 Cache - FPU Pentium - Superscalar - Dual Pipeline - Split L1 Cache Pentium Pro - L2 Cache - Br. Pred. - Spec. Exec. Pentium MMX - 57 Instructions - Integrated DSP (MMX) Pentium II - 100 MHz Bus - L2 Cache - MMX Celeron - 66 MHz Bus - True L2 Cache Integration Pentium III - 100 MHz Bus - 70 Instr. Streaming SIMD Ext. .actual processors: P IV, Centrino, DualCore, Atom,
Intel x86 Family Tree

Designer Intel Intel Intel Intel Intel Intel Intel Intel Intel Intel Intel Intel Intel Intel Intel Intel Intel Intel Intel Intel Intel Intel Intel Intel Intel Intel Intel Intel Intel Intel Intel Intel Intel Intel Intel Intel Processor 4004 8080 8086 8086 8086 8088 8088 80186 80186 80186 80188 80188 80286 80286 80286 80386DX 80386DX 80386DX 80386DX 80386SX 80386SX 80486DX 80486DX 80386SL 80486SX 80486SX 80486SX 80486DX2 80486DX2 80486DX2 80486DX2 80486DX4 Pentium Pentium Pentium Pentium 1990 1991 1991 1991 1992 1992 1992 1992 1994 1993 1988 1988 1989 1982 1982 1982 1985 Codename Year 1971 1974 1978 1978 1978 1979 1979 1982 CPU Clk 0.1 2 4.77 8 10 4.77 8 8 10 12.5 8 10 8 10 12.5 16 20 25 33 16 20 25 33 20 16 20 25 50 50 66 66 60 60 66 75 90 60 66 50 60 1 1 1.5 1.5 25 25 33 33 2 2 2 2 4.77 8 10 4.77 8 BUS Clk Clk Mult 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 5, 12 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 3.3 5 5 3.3 3,3 0.8 0.8 0.8 0.6 0.6 0.6 0.6 0.6 0.8 0.8 0.6 0.6 BiCMOS BiCMOS PGA PGA PGA PGA 273 273 296 296 1.5 1.5 0.8 1.5 1.5 1.5 1.5 Voltage Feature Size 10 6 3 3 3 3 3 NMOS NMOS, CHMOS NMOS, CHMOS NMOS, CHMOS NMOS, CHMOS NMOS, CHMOS NMOS, CHMOS NMOS, CHMOS NMOS, CHMOS NMOS, CHMOS NMOS, CHMOS NMOS NMOS NMOS CHMOS CHMOS CHMOS CHMOS CHMOS CHMOS CHMOS CHMOS CHMOS CHMOS CHMOS CHMOS DIP DIP DIP DIP DIP DIP PLCC, PGA,LCC PLCC, PGA,LCC PLCC, PGA,LCC PLCC, PGA,LCC PLCC, PGA,LCC PLCC, PGA,LCC PLCC, PGA,LCC PLCC, PGA,LCC PGA PGA PGA PGA PQFP PQFP PGA PGA PQFP, LGA PQFP, PGA PQFP, PGA PQFP, PGA PGA Quad FP PGA Quad FP 40 40 40 40 40 40 68 68 68 68 68 68 68 68 132 132 132 132 100 100 168 168 196/227 196/168 196/168 196/168 168 196 168 196 Tech. Package Pins
80x86 microprocessors
1972 Intel Corp. 8008 1978 8086
20 bit address instead of 16 1MB memory access / 64K Bus Interface Unit/ Execution Unit instruction fetch/ execution Internal Registers : Data = 16bits HW multiplier/Divider External arithmetic processor
8088
8bit external Bus Can use cheap and simple 8bit memory interface 16bit register / 20 bit address bits 1982 XT : 16 K memory, 4.77 MHz
Internal architecture of 8086 microprocessor
Address Bus
Data Bus
Instr. Decode; Bus Controller
BIU
AH BH CH
AL BL CL DL BP DI SI SP CS ES SS DS IP
ADD
1 2 3 4 5 6
EU
DH
Instruction Queue
SYSTEM BUS (Internal)
ALU/EXECUT
FLAGS
80186/80188
Single Computer in a chip 8086(8) + clock generator + timer + interrupt controller + DMA (Direct Memory Access) controller + IO interface
80286
16bit data/ 24bit address Operation modes: Real mode / protected mode
Real mode : same as 8086 Protected mode : multitasking programming Many segments in memory Once in a protected mode, cannot return real mode -> pitfall
80386
1985 : 32 bit data/address 4GB physical memory access Real mode : same as 8086 Protected mode : descriptor register controls tasks, allocates segment Segment size boundary, size Virtual Memory support
80386
Windows, OS/2 2 clock cycles for memory access Cache 16 added instructions 386SX : 16bit data/ 24bit address bits
80486
RISC (Reduced Instruction Set Computer) concept is applied Improved 386 performance 5 stage pipeline 80387 floating point processor DX2/DX4 : fast internal bus/slow external bus(clock)
Pentium
Super-scalar processor Separate 2 Pipelines Code cache/data cache 5 -8 -stage pipeline 64 bit external bus
Operating modes for Pentium

REAL MODE similar as 8086 with possibility to switch PROTECTED MODE
Virtual 8086 multitasking, virtual memory addressing,
SYTEM MANAGEMENT MODE (SMM):

Standard architectural feature since Intel 387 SL provides an operating system and application independent power management system Activated by an external interrupt SMI# switches the CPU to a separate address space while saving the entire context of the CPU
Advanced technologies used in Pentium (1)

Superscalar execution Compared with I486 which can execute only one instruction at a time, Pentium can sometimes execute 2 instructions at a time Pipeline architecture Instructions are executed in 5 stages: this allows the processor to overlap multiple instructions so that it takes less time to execute two instructions in a row Pentium has 2 independent pipelines Branch target buffer Pentium processor fetches the branch target instruction before it executes the branch instruction Dual on-chip caches two separate caches on chip--one for instructions and one for data which allows the processor to fetch data and instructions from the cache simultaneously Write-back cach When data is modified; only the data in the cache is changed. Memory data is changed only when the processor replaces the modified data in the cache with a different set of data
Advanced technologies used in Pentium (2)

64 bit bus
with its 64-bit-wide external data bus (Intel486 has 32-bit external bus) the processor can handle up to twice the data load of the Intel486 processor at the same clock frequency
Instruction optimization
The Pentium processor has been optimized to run critical instructions in fewer clock cycles than the Intel486 processor
Floating Point Optimization

The Pentium processor executes individual instructions faster through execution pipelining, which allows multiple floating-point instructions to be executed at the same time
Pentium extension
The Pentium processor has fewer instruction set extensions than the Intel486 processors. The Pentium processor also has a set of extensions for multiprocessor (MP) operation. This makes a computer with multiple Pentium processors possible
Compared with I486: separate instruction and data c

aches dual integer pipelines (U and V) branch prediction with BTB pipelined FPU 64 external bus about 3 million transistors
Pentium Pro
Two separate silicon die : processor + second cache(256K or 512K) Internal bus : 32 bit External data bus : 64 bit Address bus : 36bit for 64GB 100% compatible with 80x86 programs 3 processor instruction + 2 floaing point instructions
Improvements in Pentium Pro

Superpipelining: increases the number of execution steps, to 14, from the Pentium's 5. Integrated Level 2 Cache: The Pentium Pro features a higher-performance secondary cache compared to all earlier processors. Instead of using motherboardbased cache running at the speed of the memory bus, it uses an integrated level 2 cache with its own bus, running at full processor speed, typically three times the speed that the cache runs at on the Pentium. The Pentium Pro's cache is also nonblocking, which allows the processor to continue without waiting on a cache miss. 32-Bit Optimization: The Pentium Pro is optimized for running 32-bit code (which most modern operating systems and applications use) and so gives a greater performance improvement over the Pentium when using the latest software. Wider Address Bus: The address bus on the Pentium Pro is widened to 36 bits, giving it a maximum addressability of 64 GB of memory. Greater Multiprocessing: Quad processor configurations are supported with the Pentium Pro compared to only dual with the Pentium. Out of Order Completion: Instructions flowing down the execution pipelines can complete out of order. Superior Branch Prediction Unit: The branch target buffer is double the size of the Pentium's and its accuracy is increased. Register Renaming: This feature improves parallel performance of the pipelines. Speculative Execution: The Pro uses speculative execution to reduce pipeline stall time in its RISC core.
P6 Microarchitecture
1st level cache = 8KB instruction cache + 8KB data cache 2nd Level cache = 1 MB static RAM, 64 bits bus CENTERPIECE =Out of Order Execution called Dynamic Execution) 3 functions
Deep branch prediction (DBP)
Dynamic Data Flow Analysis (DDFA) Speculative Execution (SE) execute instructions beyind a branch
Pentium 4
NetBurst Architecture
1. Hyper pipeline technology: more pipelines: 20 31 pipes 2. Rapid Execution Engine: the ALU in the core of the CPU actually operate at twice the core clock frequency 3. Execution Trace Cache: It stores decoded micro-operations, so that when executing a new instruction, instead of fetching and decoding the instruction again, the CPU directly accesses the decoded microops from the trace cache, thereby saving a considerable time
High clock speeds (up to 4 GHz) SSE2 and SSE3 instruction sets to accelerate media processing Integration of HyperThreading
make one physical CPU work as two logical and virtual CPUs
Bigger L2 cache (512KB, 2MB) Pipeline: 31 stages
HyperThreading Technology
Figure shows a comparison of a processor that supports HT Technology (implemented with two logical processors) and a traditional dual processor system.
The technology enables a single physical processor to execute two or more separate code streams (threads) concurrently logical processors The logical processors in an IA-32 processor supporting HT Technology share the core resources of the physical processor. This includes the execution engine and the system bus interface. After power up and initialization, each logical processor can be independently directed to execute a specified thread, interrupted, or halted.
Dual (Multi) Core Processors

Based on core technology: more processors on a single chip they share some of the resources / external buses, cache Dual core - Less power consumtion (50%, peak of 65W) Faster on CPU intensive applications (audio/video processing, files scans, etc)
Homework
Explain the concept of pipeline
Explain which is the difference in addressing the memory and ad dressing the peripheral devices Explain the role of the retirement unit from P6 microarchitecture Explain the difference between 1st level cache and 2nd level cache Explain the concept of speculative execution SIMD and SSE2 stand for (Explain). Explain the concept of HyperThreading Which is the number bits allocated for data bus, respectively addr ess bus for the following microprocessors: 8080, Pentium IV, 8048 4, 80286, 8086, 80186.
(C2)
80x86 Internal Architecture
Computer Operation Model

FETCH Instruction - EXECUTE Instruction
FETCH EXECUTE FETCH time EXECUTE FETCH EXECUTE
FETCH
EXECUTE
1) Read Instruction from Memory 2) Decode/Interpret Instruction 3) Increment Instruction Address Register 1) Control Unit - Input is Decoded Instruction 2) Control Signals Set 3) Data is Processed
8086 Architecture Specifics

BIU and EU - Pipelined Arrangement
BIU - Bus Interface Unit Instruction Pipeline EU - Execution Unit Pipeline - Hardware Designed for Parallel Operation
BIU
FETCH
FETCH
FETCH
FETCH
FETCH GET DATA
EU
WAIT
EXECUTE
EXECUTE
EXECUTE
time
8086 Internal Architecture

Execution Model
8086 Overall Architecture

BIU and EU - Pipelined Arrangement
Instruction Pipeline EXECUTION UNIT EU
BUS INTERFACE UNIT BIU
System Bus (PC Bus)
Address Bus
Data Bus
Instr. Decode; Bus Controller
BIU
AH BH CH
AL BL CL DL BP DI SI SP CS ES SS DS IP
ADD
1 2 3 4 5 6
EU
DH
Instruction Queue
SYSTEM BUS (Internal)
ALU/EXECUT
FLAGS
Content of the EU: Content of the BIU: .
BIU Bus Interface Unit (Resp: signals and data/instruction

control)
To bring the instructions into the internal QUEUE To control the content of the queue To computes the address To generates the control signals
BIU - contents
Bloc for controlling the signals FIFO memory to implement the 6 byte s queue Instruction pointer (next instruction to be executed) ALU to calculate the address Internal communication registers Registers for memory segmentation
EU Execution Unit
Decoding of instructions ALU General registers (accessible by user) Internal registers (internal operations) Register to store the status and contr ol of the program
Accumulator Base Counter Data

15
AH BH CH DH
AL BL CL DL
0
AX BX CX DX
Code Segment Data Segment Stack Segment Extra Segment

15
CS DS SS ES
0
Instruction Pointer Stack Pointer Base Pointer Source Index Destination Index
IP SP BP SI DI
} }
For 32 bit processors: AX register (16b) EAX (32b)
8086/8088 Register File (cont)

Instruction Pointer Register
15 0
IP Contains Address of NEXT Instruction to be Fetched
Automatically Incremented
Programmer can Control with jump and branch
AX, BX, CX, DX

General Purpose Registers
7 0 7 0
AH BH CH DH
AL BL CL DL
Can Be Used Separately as 1-byte Registers AX AH:AL Temporary Storage to Avoid Memory Access
Faster Execution Avoids Memory Access
Some Special uses for Certain Instructions
AX, BX, CX, DX

General Purpose Registers - Some Specialized Uses
7 0 7 0
AH BH CH DH
AL BL CL DL
AX, Accumulator Main Register for Performing Arithmetic mult/div must use AH, AL accumulator Means Register with Simple ALU BX, Base Point to Translation Table in Memory Holds Memory Offsets; Function Calls CX, Counter Index Counter for Loop Control DX, Data After Integer Division Execution - Holds Remainder
CS, DS, ES, SS - Segment Registers

Contains Base Value for Memory Address
CS, Code Segment
Used to point to Instructions Determines a Memory Address (along with IP) Segmented Address written as CS:IP
DS, Data Segment

Used to point to Data Determines Memory Address (along with other registers) ES, Extra Segment allows 2 Data Address Registers
SS, Stack Segment

Used to point to Data in Stack Structure (LIFO) Used with SP or BP SS:SP or SP:BP are valid Segment Addresses
IP, SP, BP, SI, DI - Offset Registers

Contains Index Value for Memory Address
IP, Instruction Pointer
Used to point to Instructions Determines a Memory Address (along with CS) Segmented Address written as CS:IP
SI, Source Index;
DI, Destination Index
Used to point to Data Determines Memory Address (along with other registers) DS, ES commonly used
SP, Stack Pointer;
BP, Base Pointer
Used to point to Data in Stack Structure (LIFO) Used with SP or BP SS:SP or SP:BP are valid Segment Addresses
These can also be used as General Registers !!!!!!
8086/8088 Register File (cont)

Flags Register
15 0
x OF DF IF TF SF ZF x AF x PF x CF
Status and Control Bits Maintained in Flags Register
Generally Set and Tested Individually

9 1-bit flags in 8086; 7 are unused
Status Flags
Indicate Current Processor Status
CF OF ZF SF Carry Flag Overflow Flag Zero Flag Sign Flag Arithmetic Carry Arithmetic Overflow Zero Result; Equal Compare Negative Result; NonEqual Compare Even Number of 1 bits Used with BCD Arithmetic
PF
AF
Parity Flag
Auxiliary Carry
Control Flags
Influence the 8086 During Execution Phase DF: Direction Flag Increment/Decrement
used for string operations
IF: Interrupt Flag

TF Trap Flag
Enables Interrupts
Allows Single-Step
allows fetch-execute to be interrupted for debugging; causes interrupt after each op
MOV AH,[SI]
8086 Segmented Memory

x86 Memory Partitioned into Segments 8086: maximum size is 64K (16-bit index reg.) 8086: can have 4 active segments (CS, SS, DS, ES) 8086: 2-data; 1-code; 1-stack x386: maximum size is 4GB (32-bit index reg.) x386: can have 6 active segments (4-data; FS, GS) Why have segmented memory ???????? Other microprocessors could only address 64K since they only had a single 16-bit MemAddrReg (or smaller). Segments allowed computers to be built that could use more than 64K memory (but not all at the same time).
8086/8088 Memory Access Registers

15 0
Code Segment Data Segment Stack Segment Extra Segment

15
CS DS SS ES
0
Instruction Pointer Stack Pointer Base Pointer Source Index Destination Index
IP SP BP SI DI
} }
8086 Generating Physical Addresses

CS
Memory System Address Lines
ES
SS DS
19 Physical Address
Dedicated Segment Registers

ADD
15 Index Reg. 0 15 Segment Reg. 0 0000 BP DI SI SP
Portion of BIU Circuitry
IP
Dedicated Index Registers
Segmented Addressing
Each Segment must begin at Paragraph Boundary

physical address
00000h
CS ES SS
memory paragraph 1
DS
00010h
paragraph 2
00020h
paragraph 3
BP DI SI
Each paragraph has phys. address that is multiple of 10h BIU is responsible for appending 0000 to Segment
only need 16-bit segment registers
SP IP
Segmented Memory (x86 Style)

FFFFFh
Code Segment
Segment Registers
CS ES SS
Extra Segment Stack Segment
DS
Segment Registers: Point to Base Address Index Registers: Contain Offset Value fragmentation Notation (Segmented Address):
CS:IP DS:SI ES:DI SS:BP SS:SP
Data Segment
00000h
System Memory
Memory Storage Organization

Organized as SEGMENTS Maximum segment size = 64KB
(Since 16 bit offsets: 216 = 65,535 = 64KB)
Maximum Memory Size: 220 = 1,048,576 = 1MB Newer Processors (Pentium) Can Utilize More Memory Wider Address Registers 32 bits
232 = 4,294,967,296 = 4GB
Segmented Memory Example

FFFFFh
Code Segment
Segment Registers
CS ES SS
Extra Segment Stack Segment
DS
Logical, Segmented Address: 0FE6:012Bh Offset, Index Address: 012Bh Physical Address: 0FE60h 65120 + 012Bh 299 0FF8Bh 65149
Data Segment
00000h
System Memory
Segmented Memory Aliasing

Logical, Segmented Address 1: DS:SI = 1234:4321 Physical Address: 12340h 74560 + 4321h 17185 16661h 91745 Logical, Segmented Address 2: ES:DI = 1665:0011 Physical Address: 16650h 91728 + 0011h 00017 16661h 91745
Segment Locations in Physical Memory
1 Word = 16 bits Byte Addressable Little Endian Arrangement

MSB (Most Significant Byte) at Higher Address
072CH 072BH 072AH 18H A3H 7EH AD5FCH AD5FBH AD5FAH
0729H
0728H 0727H 0726H 0725H 0724H 0723H 0722H
69H
AAH 2EH 00H 55H 02H 72H 11H
AD5F9H
AD5F8H AD5F7H AD5F6H AD5F5H AD5F4H AD5F3H AD5F2H
Base Address = ACEDH Logical Address = 0724H Physical Address = ACED0H + 0724H = AD5F4H M[ACED:0724] = M[AD5F4] = 5502H
0725H
0724H 0H 0000 2H 0010
5H 0101
5H 0101
hex binary
072CH 072BH 072AH 0729H 0728H 0727H 0726H 0725H 0724H 0723H 0722H 0721H 0720H 071FH 071EH 071DH
18H A3H 7EH 69H AAH 2EH 00H 02H 55H 11H 20H 72H DEH ADH FAH CEH
AD5FCH AD5FBH AD5FAH AD5F9H AD5F8H AD5F7H AD5F6H AD5F5H AD5F4H AD5F3H AD5F2H AD5F1H AD5F0H AD5EFH AD5EEH AD5EDH
Assume: M[DS:DI] Contains a Pointer Value DS = AD5Fh; DI = 0005h (All Segments Start on Paragraph Boundary) SI M[DS:DI] Then: Pointer is M[DS:DI] = M[AD5F:0005] = M[AD5F5] = 0002h M[DS:SI] = M[DS:(DS:DI)] = M[DS:0002h] = M[AD5F:0002] = M[AD5F2] = 1120h
071CH
CAH
FEH
AD5ECH
Default Segment/Index Pairs
Type of Memory Reference Instruction Fetch Stack Operation Variable (except following) - String Source - String Destination - BP used as Base Register - BX Used as Base Register
Default Segment Base CS SS DS DS ES SS DS
Alternate Segment Base Offset None IP None SP CS, ES. SS Effective Address CS, ES, SS SI None DI CS, DS, ES Effective Address CS, ES, SS Effective Address
Homework: Give several exercises
Keypoints
(C3)
Addressing Modes for 80x86 microprocessors
Addressing modes- Classification

Register addressing Immediate addressing Memory addressing
Direct addressing Indirect register addressing Based addressing (with/without displacement) Indexed addressing (with/without displacement) Based-indexed adressing (with/without displacement) Addrssing on strings of bytes Addressing of ports
Exceptions:
-Segm segm -Segm immediate value
Memory addressing
Addressing on strings of bytes

Strings of bytes
Source string (SI), in DS (default) Destination string (DI), in ES (default)
Examples of strings Examples how the address is calculated:

MOVSB, LODSB.
Addressing the ports

What is a port? Input/output on ports Which is the address of the port?
Difference on memory address
Registers used in addressing Examples How to switch on a LED? Example.
Instruction encoding (e.g. MOV)
The instruction set

http://burks.brighton.ac.uk/burks/language/asm/asmtut/asm1.htm#toc http://webster.cs.ucr.edu/AoA/DOS/AoADosIndex.html
1) Instructions for data transfer
2) Arithmetic instructions
3) Logic instructions
4) Shifts/rotate instructions + LOOPS

5) Instructions on strings of bytes
6) Instructions for port input/outpus
Instructions for data transfer
MOV XCHG XLAT PUSH/POP LEA LDS, LES
Arithmetic Instructions ( to be continued)
ADD, ADC INC AAA, DAA SUB, SBB DEC AAS, DAS
(C4)
INTRUCTION SET
The instruction set

1) Instructions for data transfer
2) Arithmetic instructions

Instructions for data transfer
MOV XCHG XLAT PUSH/POP LEA LDS, LES
Important: -Dest & source the same size in bits -Register can not be IP -Transfer memory memory is not possible -Flags are not changed
Exercises (MOV, XCHG)

1) In AH, byte from the address 0, AL FFFFF
1) 2) Using direct addressing Using indexed addressing
2)
ES=1000, DS=5000, DI=100, SI=200 exchange the values of mem locations (bytes):
1) 2) Using only MOV Using XCHG
3) 4) 5) 6) 7)
Use based with index addressing AX ES:[3000h] Interchange DS with ES AXBXCXDXAX (2 solutions give other solutions) Interchange AX with BX without: MOV, XCHG (**) For laboratory: propose 2-3 exercises similar as above
Exercise XLAT
1) 2) 3) 4) Draw the schematic principle Where is applied: encryption, conversion Example with ASCII codes Write an encryption algorithm give the solution:
1) Input from port 100h 2) Encrypt 3) Send to the port 200h
LDS, LES - examples

The schematic explanation (first SI, then DS) LDS SI, adress (LDS BX, address) LES DI, address (LES reg,address) Example for transfer of strings of bytes
Exercises PUSH, POP

Save an the stack all register (CALL) Exchange BX with CX using push/pop AXBXCX using push/pop Propose 2-3 problems
Arithmetic Instructions ( to be continued)
ADD, ADC INC AAA, DAA SUB, SBB DEC AAS, DAS
(C5)
INTRUCTION SET - 2
The instruction set

1) Instructions for data transfer 2) Arithmetic instructions

Exercise XLAT
Conversion of the digit from
AL (0, 1, ...9, A, ...F) in the corresponding ASCII code (30h,...39h, 41h, ...46h)
Give 2 solutions
Example AAA, DAA

AL=37h, BL=32h (in ASCII) The result:
in binary, in ASCII
DAA instruction for BCD numbers
Example AAA
;Example AAA MOV AH, 09h MOV AL, 05h ADD AL, AH MOV AH, 0 AAA
; example AAS
MOV AL, 05h

MOV BL, 09h SUB AL, BL; al=FC (-4)
; convert to BCD, AL = 6, ; AAS

ADD AL, 30h; convert in ASCII
Examples
1) 2) 3) 4) 5) AX= BX-CX Substraction on bytes (SBB) (AX,BX) = (AX,BX) (CX, DX) Al=al-2 Mov bx, 0; Dec bx
On BYTE: On WORD:
AX = AL*operand(8) (DX,AX) = AX*operand(16). Eg:..
Examples MUL
Ex: val1 DB val2 DW mov mul mov mul
mov
3 257 al, 0ah val1 ax,100h val2
al,8 bl,7 bl; AX=38h=56 AX=0506
mov mul aam;
AX=3*AL (mul + add) AX= 5*AL 7*BL 2 solutions AL = BCD representation of a number on 2 digits. BL its binary representation.
On BYTE: AL = [AX / operand(8))], AH = the rest

On WORD: AX = [(DX,AX) / operand(16)], DX the rest
Examples DIV
AL=AL/3 BL = BL/2 (give 2 solutions) AL= AL/5 BL/7
Remarks (AL AX)
Examples:
AX = AX BX (sub ax,bx OR neg bx; add ax,bx
mov mov cmp jl inc label inc bl
al,value bl,2 al,bl label bl
Conditional JUMP
JUMP IF less/bellow less or equal/bellow or eq equal/zero not equal/not zero greater or equal/above eq greater/above carry/not carry sign/not sign JL/JB JLE/JBE JE/JZ JNE/JNZ JGE/JAE JG/JA JC/JNC JS/JNS
Exercises
AL = max(BL, CL) AL = BL+CL (if DL>0), BL-CL (DL<0), 0 DL = 0 if AL is odd, 1 if AL is even AL = ASCII code (digit from AL)
TEST dest,source
Exercises
mov and or xor test ax, 0abcdh ax,0ffh ah, 0fch al,ah al,1
AL = 0 (if BL6=0), 1 (if BL6=1) AX=ASCII AL=binary DL=Binary AX-ASCII
(C6)
INTRUCTION SET - 3
The instruction set

1) Instructions for data transfer 2) Arithmetic instructions

Instuctions for SHIFT

Logic (insert 0s)
Left: Right: SHL reg/mem, {1, CL}
1011 0001 0110 0010
SHR reg/mem, {1, CL}
1011 0001 0101 1000
Arithmetic (insert 0s, but keep the SIGN)

Left: Right: SAL reg/mem, {1, CL} SAR reg/mem, {1, CL}
Instuctions for ROTATE

Without Carry (CY is not rotated)
Left:
1011 0001 0110 0011
ROL
reg/mem, {1, CL}
Right:
1011 0001 1101 1000
ROR reg/mem, {1, CL}
With Carry (CY is included in rotation)

Left:
CY=x CY=1
RCL reg/mem, {1, CL}

1011 0001 0110 001x
Right:
CY=x CY=1
RCR reg/mem, {1, CL}

1011 0001 x101 1000
Examples
a) mov al, 0ffh shl al,1 mov cl,3 shl al,cl -----------------c) mov al, 0fch mov cl,4 rol al,cl shr al,cl
b) sal al,1; sar al,1; (mul 2) (div 2)
Exercises (1)
1) Store in BL the value of bit a4 from AL a) b) mov cl,3 and al,00010000b shl al,cl mov cl,4 mov cl,7 shr al,cl shr al,cl mov bl,al mov bl,al Find out other 2 solutions !!
Exercises (2)
2) AX = ??xy; (x,y=hexa). Obtain AX=0x0y push cx mov cl,4 rol ax,cl; AX=?xy? and ah,0Fh AX=0xy? shr al,cl; AX=0x0y pop cx Propose another solution !!
Exercises (3)
3) AX = 8*AL 7*BL mov cl,3 cbw sal ax,cl xchg ax,bx cbw mov dx,ax sal ax,cl sub ax,dx sub bx,ax xchg ax,bx
Exercises (4)
4) Counts into DL the number of bits 1 from AX xor dl,dl mov cx,16 nextbit rcl ax,1 jnc zerobit inc dl zerobit dec cx jnz nextbit Propose another 2 solutions !!
Exercises (5)
5) Fill in the first 256 bytes from DS with the values: 00, 01, 02, ..., FFh mov si,0 mov cx,256 xor al,al NextByte: mov byte ptr[si],al inc al inc si dec cx jnz NextByte
LOOP instruction
Syntax: LOOP Equivalent with: DEC JNZ label
CX label
Other forms: LOOPE/LOOPZ and LOOPNE/LOOPNZ
Examples
et1: mov xor add loop cx,100 ax,ax ax,2 et1
Instructions to control the FLAGS
Examples: ...some examples.
Example: read from keyboard (port 60h) and write to printer (port 378h):
in
mov out
al,60h
dx,378h dx,al
(!!! Some tests are required: keypressed?, printer busy?...later on)
Examples IN/OUT
1) Generate a rectangular signal on D0 from port 300h 2) Control the frequency 3) Give the solution to control the duration of the signal 4) Signal with another form 5) Connect a DAC and generate a triangular signal (maximum frequency) 6) A dynamic light: control the speecd
Examples: a) wait for non busy, b) timeout
LODSB(W)
Example LODSB
DX = Sum(DS:SI=100h), i=1...20 xor dx,dx mov cx,20 mov si,100h cld nextbyte: lodsb cbw add dx,ax loop nextbyte Propose the solution without using LODS
STOSB(W)
Example STOSB
Generate a string of 256 bytes (00, 01, ...FFh) at the address ES:DI=300H mov di,300h xor al,al mov cx,256 cld sto: stosb inc al loop sto nop Propose the solution without using STOSB
MOVSB
Examples MOVSB (transfer 20 bytes from DS:SI=100h to ES:DI=300h) mov si,100h mov si,100h mov di,300h mov di,300h mov cx,20 mov cx,20 cld e: mov al,[si] e: MOVSB mov [di],al loop e inc si inc di Obs: dec cx REP jnz e MOVSB
Example: returns into BX the offset of the first 00 byte encountered in the string of 100 bytes found at the address ES:DI=200h OR 0FFFF if not found.
mov mov mov s: cmp je inc loop mov f0: mov nop
di,200h cx,100 al,0 al,[di] f0 di s di,0ffffh bx,di
mov mov cx, mov cld REPNE SCASB jcxnz mov f: dec mov nop
di,200h 100 al,0
f di,0 di bx,di
Exercise
Data Acquisition System: - Control port, RD/WR: 200h: (START on D0 active in 1, EOC on D7 active in 0) - data port, RD, 300h - Read 10.000 samples in ES:DI=100h
MACRO - instructions
= a group of instructions identified by a unique name (the name of the MACRO) and interpreted as a new instruction - a MACRO needs to be defined: name MACRO param_1, ..., param_n .... instructions .... ENDM In order to use the MACROs: - They need to be defined - They could be used afterwards
Example 1 (without parameters)

MACRO to store/restore the registers (A) (B) Definitions: push_regs MACRO pop_regs MACRO push ax pop dx push bx pop cx push cx pop bx push dx pop ax ENDM ENDM Usage: .... ..... push_regs ; substituted by the above sequence .... .... pop_regs .... .... Discussion: Advantages (+), Disadvantages (-)
Example 2 (with parameters)

MACRO to FILL in a string of bytes in ES at the address addr with the value 0 (parameters: address and number of bytes ) Definition: fill MACRO addr, n xor al,al cld mov di, addr mov cx, n rep stosb ENDM Usage: .... ..... fill 100h, 200h ; substituted by the above sequence .... ....
Example 3 (with parameters)

MACRO to add/subtract 2 numbers n1, n2 of 1 byte into AL (AL=n1+/- n2) Definition: compute MACRO n1, operand, n2 mov al, [n1] cmp [operand], + jne minus add al, [n2] jmp final minus: sub al,[n2] final: nop ENDM Usage: mov di DB 20h op DB - b DB 10h .... ..... compute a, op, b ; substituted by the above sequence .... ....
Exercises (homework)
MACRO for:
Obtaining in AX the sum of a string of bytes (the offset address in DS and the number of the bytes are the parameters) Obtaining in AL the maximum of a string of bytes (the address and the number of the bytes are the parameters) Returning in CX the length of a string of bytes that ends with 00h (the address is transmited as parameter)
CALL - instructions
The need to substitute sequences of programs which are repeated OR group the functionalities in a single software entity Example diagram Types of CALLS Intrasegment (NEAR Calls) - IP Intersegment (FAR Calls) CS, IP
Execution Steps
1) 2) CALL is classified as NEAR or FAR NEAR FAR save IP on the stack - save CS on the stack - save IP on the stack 3) JUMP at the address CS:IP 4) Execute the sequence, until RET is encountered 5) RET execution: NEAR - get IP from the stack - get IP from the stack - get CS from the stack 6) JUMP at the address CS:IP
Procedures
Definition: namep PROC ... ... instructions ... ... RET; namep ENDP Usage: ... call ... ... namep ... {NEAR or FAR}
PAY ATTENTION !!
Example 1 (find_max in a string; receives in SI begining of the string and the length in CX; returns the max in AL and the index of max in BX)
find_max PROC mov mov dec cmp jge mov mov inc inc loop RET ENDP .... mov mov call ... NEAR al, byte ptr [si] bx,si cx al, byte ptr[si +1] Ok al, byte ptr[si+1] bx,si bx si c
c:
Ok:
Usage: ... si, offset string1 cx,length find_max ...
Example 2 (strlen returns in CX the length of a string of bytes finished with 00h; receives into DI the begining of the string)
strlen PROC xor xor cld scasb jz inc jmp ret ENDP str .... mov call ...
cx,cx al,al
comp:
exit cx comp
exit: Usage:
DB un text, 0 ... di, offset str; (equiv: strlen ...
lea
di,str)
Allocation of memory for variables

DB define byte, DW define word, DD-define double word Examples:
a b c str len DB DB DW DB EQU 1 2 1, 2, 3 text, 0 $-Str
Usage: mov mov mov mov al, [a] si, offset a al, [si] si, offset str
Organisation of the programs in Assembling Language (*.asm)

PAGE 60,132 TITLE ROTIT COMMENT * * STIVA SEGMENT DW STIVA ENDS ; DATA SEGMENT a DB DATA ENDS CODE SEGMENT MAIN PROC ASSUME push ds xor ax,ax push ax mov ax,DATA mov ds,ax ; ..... ret MAIN ENDP CODE ENDS END MAIN PARA 256 STACK DUP(?) 'STACK'
PARA 0
PUBLIC
'DATE'
PARA PUBLIC 'COD' FAR SS:STIVA,DS:DATA,CS:CODE,ES:NOTHING
;preg.pt.ret ;preg. DS
EXE/COM
TASM progr.asm
(progr.obj)
TLINK progr.obj
(com/exe options in TLINK)
THE SYSTEM OF INTERRUPTS 1) 2) 3) 4) 5) 6) 7) 8) Definitions Questions (??) Classification of interrupts The Interrupt Vector Table (IVT) The steps to execute a ISR The interrupt controller 8259 The sequence for Interrupt Acknowledge Applications of software interrupts
1) Definitions
a) Need of communication between the uP and the peripheral devices
uP Peripheral devices
b) Idea: to interrupt the execution of the current program c) Def: Interrupts + Interrupt Service Routine
2) Questions
1) Who can interrupt the uP? (possibilities)
a) Hardware b) Software Classification of interrupts
2) What happens when an interrupt is accepted? 3) How the processor finds the address of ISR? 4) Then, which is the difference between a PROC and ISR?
Address (ISR), address (PROC) End: ISR (iret), PROC (ret)
3) Classification of interrupts
a) Internal interrupts / exceptions b) Hardware interrupts (from peripheral devices data transfer; signals are used)
INTR maskable interrupts
I=1 (STI) I=0 (CLI) NMI
NMI non-maskable interrupts
When accepted? - At the end of an instruction cycle ! How are the peripheral devices recognised? By a type number which is used by the processor as a pointer in the IVT to obtain the address of the ISR
Classification (cont)
c) Software interrupts INT k; k=0...255 (type of interrupt)
Examples: INT 10h (video services) INT 14h (communication on serial interface)
4) The Interrupt Vector Table (IVT)

Implements a mechanism that associates for a specific interrupt request a service (handler or ISR). It stores the addresses of ISRs 256 types of interrupt requests What we need to obtain an address for ISR
CS & IP Many ISRs : k=0 ... 255 (type of interrupts)
The structure of IVT

Location Structuring (IP, CS), 256 entries
The input in the table is the key k (interrupt type) Who delivers the key to the uP? (example of values)
5) The steps to execute a ISR

1) Peripheral device interrupt controller (it associate a key K to the device); K-progr 2) I=1?- uP accepts the interrupt INTA and asks for the key. The key is transmited to the uP. 3) The uP uses the key K to find out the address of the ISR (associates an ISR to the peripheral devices) 4) uP execute the ISR and then returns to the main program
6) The interrupt controller 8259
Inputs on 8259
Explain: IRQi signals + connection of 2 controllers 8259 in the system
7) The sequence for Interrupt Acknowledge

= a hardware mechanism to send the key K from the interrupt controller 8259 to the uP The diagram of signals (if INTR and I=1) 1) Save on the stack: PSW, CS, IP, I=0, T=0 2) It follows the sequence of INTA 2 machine cycles ALE LOCK INTA (1st activation, 2nd activation) Key K 3) Point into IVT at address k*4 to get the address of ISR 4) Jump to ISR and execute it 5) IRET returns in the main program
8) Applications of software interrupts

VIDEO SERVICES (INT 10h) BIOS level AH =2 (setting the cursor to a specific location)
In: DH = raw, DL=column Exercise: position in the centre of the screen
AH=3 (get current cursor position)

Returns in DH=raw, DL=column, CX=the shape of the cursor Exercise: Move Relative Nx, Ny
AH=6 (scroll up)

In: AL=no of lines for scroll (AL=0, CLS), BH=attribute of blank raws CH=upper raw, CL=left column, DH=lower raw, DL=right column Example: Clear Screen
AH= 9 (display a character from AL)

AL, BH=video page, BL=atrribute, CX-rep Example: Display a string defined in DS, starting in raw 3 column 5
AH=0Eh (display char with increment of cursor)
8) Applications of software interrupts

KEYBOARD SERVICES (INT 16h) BIOS level AH =1 (test if keypressed)
Return Z=0 if Keypressed, Z=1 if not Keypressed
AH=0 (read the character)

Returns in AH the scane code and in AL the ASCII code of the Key.
Exercise: Read a string and display it, until ESC is pressed
DOS services (INT 21h)
INT 21h (cont)
Documentation: INT 1Ah, INT 14h, INT 17h, INT 13h
INSTALLING OWN Interrupt Service Routines 1) Why? 2) How to do? 3) Examples
1) Why?
To change or adapt an existing BIOS service:
Keyboard: to capture a combination of keys Timer: to count real time events related to a specific process (ADC). Mouse related procedures Etc? Discussions.
The install a peripheral-specific procedure:

ADC or DAC Own applications Examples?
2) How to do?
STEPS: (the scheme) 1) Write the own ISR 2) Reserve memory in DS for old values from IVT and save IP and CS of previous routine at these locations (CLI) 3) Upload in IVT the new values for IP and CS of the own ISR 4) NOW the interrupts may come (STI) 5) ... The program is executed ... 6) CLI and restore the old values of IP and CS into IVT, then STI.
2.1) Write the own ISR

iroutine PROC FAR ... ... mov al,20h (EOI for 8259) out 20h, al iret ENDP
iroutine
2.2) Save the old IP and CS from IVT

CS_Old IP_Old DW ? DW ? .... .... ; save the old IP and CS from IVT cli xor ax,ax mov es,ax mov di, k*4; k=type of interrupt mov ax, word ptr es:[di] mov [CS_Old],ax add di,2 mov ax, word ptr es:[di] mov [IP_Old],ax
OR 2.2) Save the old IP and CS from IVT (using INT 21h)
CS_Old IP_Old DW ? DW ? .... .... ; save the old IP and CS from IVT cli mov ah,35h mov al,k int 21h; in ES the SEGMENT, in BX the OFFSET mov [CS_Old],es mov [IP_Old],bx
2.3) Install in IVT the new values for IP and CS

mov mov mov add mov mov STI di,k*4 ax, segment iroutine es:[di],ax di,2 ax, offset iroutine es:[di],ax
OR 2.3) Install in IVT the new values for IP and CS (INT 21h, AH=25h)
mov mov mov mov mov int
STI
ah,25h al,k ax,segment iroutine ds,ax bx, offset iroutine 21h
2.6) Restore the old values of IP and CS

mov mov mov mov mov int ax, [CS_Old] ds,ax bx, [IP_Old] ah,25h al,k 21h
Microprocessors and Computer Systems

Chapter 5 8088 Pin Assignment
(*Brey:ch9; Hall:ch7; Triebel:ch7)
ELE 3230 - Chapter 5 1
ELE 3230
Pin Layout of the 8088 Microprocessor

Min Mode
GND A14 A13 A12 A11 A10 A9 A8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 NMI INTR CLK GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 Vcc A15 A16/S3 A17/S4 A18/S5 A19/S6 SS0 MN/MX RD HOLD HLDA WR IO/M DT/R DEN ALE INTA TEST READY RESET (High)
(Max Mode)
Nine pins have functions which depend on the state of MN/MX :
MN/MX =high - 8088 operates in MINIMUM MODE MN/MX =low - 8088 operates in MAXIMUM MODE
minimum mode: - 8088 directly generates the control signals necessary for accessing memory and IO ports. maximum mode:- external support chips are needed to generate control signals; the processor can work in a system containing other processors
2
8088 CPU
(RQ / GT0) (RQ / GT1) (LOCK ) (S2) (S1 ) (S0 ) (QS0) (QS1)
40 LEAD
Signals Common to Both Minimum and Maximum Modes

Name AD7 AD0 A15 A8 A19/S6 A16/S3 MN/MX RD TEST READY RESET NMI INTR CLK VCC GND Common signals Function Address/data bus Address bus Address/status Minimum/maximum Mode control Read control Wait on test control Wait state control System reset Nomaskable Interrupt request Interrupt request System clock +5V Ground
ELE 3230 - Chapter 5
Type Bidirectional, 3state Output, 3-state Output, 3-state Input Output, 3-state Input Input Input Input Input Input Input Input
3
Unique Minimum-mode Signals

Minimum mode signals (MN/ MX = VCC ) Name Function Type HOLD Hold request Input HLDA Hold acknowledge Output
WR
Write control IO/memory control Data transmit/receive Data enable Status line Address latch enable Interrupt acknowledge
Output, 3-state Output, 3-state Output, 3-state Output, 3-state Output, 3-state Output Output
4
IO/M
DT/R DEN
SSO ALE
INTA
Unique Maximum-mode Signals

Maximum mode signals (MN/ MX= GND) Name Function Type RQ/ GT1, 0 Request/grant bus Bidirectional access control Bus priority lock Output, LOCK control 3-state Bus cycle status Output, S2 - S0 3-state QS1, QS2 Instruction queue Output status
Maximum-Mode of 8088
INIT S0 S1 S2 CLK Vcc GND Interrupt interface INTR TEST NMI RESET LOCK
S0 S1 S2
Multibus BUSY CBRQ BPRO BPRN BREQ BCLK IOB
CRQLCK RESB
SYSB/RESB
8289 LOCK Bus arbiter CLK AEN IOB
CLK
ANYREQ AEN
CLK AEN IOB S0 8288 S1 S2 Bus DEN controller DT/R ALE
8088 MPU
MRDC MWTC AMWC IORC IOWC AIOWC INTA MCE/PDEN ALE DT/R DEN A0-A15, A16/S3-A19/S6 D0-D7 RD READY QS1,QS0
MN/MX
Local bus control RQ/GT1 RQ/GT0 ELE 3230 - Chapter 5 6
Maximum-Mode of 8088
8288 Bus Controller
In maximum-mode, the signal to control memory, I/O, and interrupt interface is produced by 8288.
WR, IO/ M, DT/ R , DEN, ALE, and INTA are no longer produced by 8088, instead 8288 generates
MRDC -- memory read command MWTC -- memory write command AMWC -- advanced memory write command IORC IOWC
-- I/O read command -- I/O write command -- interrupt acknowledge command

AIOWC -- advanced I/O write command INTA
Bus Status Codes

8288 produces the commands according to the output bits S 2 S1 S 0 from 8088.
Status Inputs S2 S1 S0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 CPU Cycle 8288 Command
Interrupt Acknowledge INTA Read I/O Port IORC Write I/O Port IOWC, AIOWC Halt None Instruction Fetch MRDC Read Memory MRDC Write Memory MWTC , AMWC Passive None
Queue Status Codes

Two new signals are produced by 8088 in maximum-mode : QS0 and QS1. The two-bit code tells the external circuitry what type of information was removed from the queue in the previous cycle.
QS1 0 (low) QS0 Queue Status 0 No Operation. During the last clock cycle, nothing was taken from the queue. 1 First Byte. The byte taken from the queue was the first byte of the instruction. Queue Empty. The queue has been reinitialized as a result of the execution of a transfer instruction. Subsequent Byte. The byte taken from the queue was a subsequent byte of the instruction.
1 (high)
Pin Diagram
386DX processor view from pin side

Top view for 386SX processor

10
8088 Pin Functions

The 8088 pins may be grouped into the following nine categories: 1. Power Supply and Clock (VCC, GND and CLK) VCC=5 volts (5 or 10% tolerance) Maximum current needed is 340mA (10 mA for CMOS version) BOTH ground (GND) pins must be connected to 0V. CLK input needs a periodic rectangular waveform with rise and fall times of less than 10ns. Clock frequency must be between 2 and 5 MHz. (see ch06, clock chip 8284). 2. Minimum/Maximum Mode pin Minimum mode selected when (MN/MX) is connected to +5V
11
8088 Pin Functions

3. Status Pins ( S0, S1 , and S2 ) - in maximum mode only The status pins are outputs which are used by the 8288 bus controller to generate control signals according to the following table:
S2 0 0 0 0 1 1 1 1
S1 0 0 1 1 0 0 1 1
S0 0 1 0 1 0 1 0 1
Meaning Interrupt acknowledge (INTA) I/O read I/O write HALT Code access (fetching instruction) Memory read Memory write Passive state (not used)
12
8088 Pin Functions

4. Bus Master (HOLD, HLDA, RQ/GT0, RQ/GT1 and LOCK) Control of the local bus is transferred to other devices with aid of the following signals: Minimum Mode - HOLD and HLDA (hold acknowledge) Maximum Mode - request/grant (RQ/ GT0 , RQ/ GT1) and LOCK HOLD is an input (in minimum mode only) which tells the processor to suspend operations and allow other devices to access the system bus. Program execution only resumes when HOLD=0. HLDA (hold acknowledge) is an output which informs other devices in the system that the 8088 is in a HOLD state. When another device wants to access the bus, it waits for HLDA=1.
13
8088 Pin Functions

4. Bus Master (cont.) (HOLD, HLDA, RQ/GT0, RQ/GT1 and LOCK) Request and Grant pins (RQ/ GT0 and RQ/ GT1) are used only in maximum mode and function both as inputs (to accept requests) and outputs (to grant requests). When another device wants to become the BUS MASTER (i.e. take control of the local bus) it issues a request by pulling one of the request pins to a low logic state for one clock cycle. After a request is received, the 8088 enters a HOLD state and sends a grant signal on the same pin. RQ/ GT0 has a higher priority over RQ/ GT1.
LOCK is an output pin in maximum mode and informs other devices that they cannot takeover the local bus
14
8088 Pin Functions

5. Interrupt pins (NMI, INTR and INTA) Interrupt acknowledge pin (INTA ) is available only in minimum mode. NMI (non-maskable interrupt) and INTR (interrupt request) are present in both modes. The NMI (non-maskable interrupt) is an input which accepts a rising edge to trigger the interrupt. It cannot be disabled by software. Interrupt number 2 is generated by an NMI. INTR is an input which accepts a high logic level as an interrupt request. Provided the interrupt flag in the FLAGS register is enabled, the processor will respond to the interrupt request in the same way as it processes an software INT instruction. INTA acknowledges an interrupt request and indicates to the interrupting device that it should place an 8-bit interrupt number on the data bus
15
8088 Pin Functions

6. RESET is an input which resets and initializes the processor. After a RESET the processor reads memory location FFFF0h for an instruction. 7. Bus control pins A group of 7 pins generate the control signals for data transfer to and from the data and address bus in minimum mode. In maximum mode only two (RD and READY) of these 7 functions are available directly (the other bus protocol signals are generated from the status pins). The seven pins in this group include: READY - an input to tell the processor that the selected memory or I/O port is ready to complete a read or write operation. If READY is not asserted, wait states are added (eg. For slow memory).
16
8088 Pin Functions

7. Bus control pins (cont.) RD (read) - an output indicating when the processor is performing read operation from memory or an I/O port. ALE (addressing latch enable) - an output to demultiplex the address/data pins. When ALE is high, address information is being sent. DEN (data enable) - an output used with an external tristate buffer to disconnect the processor data pins from the data bus. (When DEN is low the processor data pins should be connected to the data bus) DT/R (data transmit/receive) - an output indicates direction of data flow WR (write) - an output to indicate when the processor is putting data into memory or I/O port IO/M - an output indicates whether access is to memory or I/O ports The logic is different between 8086 & 8088.
17
8088 Pin Functions

8. Address, data pins and address status pins AD0-AD7 (address/data bus pins) - these pins output both address and data information and input data at different times of the bus cycle. Usually an external latch stores the address information form these pins before the pins are switched to carry data. Both the low and high order bytes of a 16-bit data word must be transferred via these pins. A8-A15 (address bus pins) - used solely for specifying the address of a memory location or IO port. A16/S3-A19/S6 (address bus or status pins) - these either carry memory addressing information or status information. S6 is always at logic 0. S5 describes the state of the interrupt flag in the FLAGS register. S4 and S3 describe the segment register being used to generate the physical address that was output on the address during the current bus cycle.
8088 Pin Functions

8. Address, data pins and address status pins (cont.)
S4 0 0 1 1 S3 0 1 0 1 Segment register ES SS CS or no segment DS
The address pins A0-A15 specify either a 16-bit I/O port number or the first 16 bits of a 20-bit address of a memory location. 9. Coprocessor interaction pins Three pins (TEST, QS0 and QS1) are used for interactions between the 8088 and 8087 arithmetic co-processor to synchronize MPU with external hardware.
8088 Pin Functions

9. Coprocessor interaction pins (cont.) TEST is an input pin that is tested by the WAIT instruction. If TEST is low the WAIT instruction functions as a NOP. If TEST is at logic 1 then the WAIT instruction waits until it goes to logic 0 (MPU enters idel state). The TEST pin is often connected directly to a 8087 coprocessor (it must be connect to logic 0 if the 8087 is not present) QS0 and QS1 (queue status) pins provide information on the 8088 internal instruction queue. The information is used by the 8087 coprocessor. The queue status bits indicate the contents of the internal instruction queue according to the following table: QS1 QS0 instruction queue contents 0 0 No operation (queue is idle) 0 1 First byte of an opcode 1 0 Queue is empty 1 1 Subsequent byte of an opcode
DC characteristics of Pin
It is important to know the input and output characteristics which are required for hardware designer to select proper components. Input characteristics: Output characteristics:
Logic Level 0 1 Voltage 0.8 V max 2.0 V min Current 10A max 10A max
Logic Level 0 1 Voltage 0.45 V max 2.4 V min Current 2.0mA max -400A max
Logic 1
Undetermined Range Input voltage range VIH(min) VIL(max)
Logic 1
VOH(min) Disallowed Range VOL(max)
Logic 0
Logic 0
Output voltage range

21
DC characteristics of Pin
Noise immunity :
VNL [Low-level (Logic 0) noise immunity] = Vin_low (max)- Vout_low(max) VNH [High-level (Logic 1) noise immunity] = Vout_high(min)-Vin_high(min)
For 8088, VNL is 350mV (=0.8V-0.45V). Typical logic circuit has noise immunity 400mV (=0.8V-0.4V). Smaller noise immunity means 8088 and 8086 would encounter problem with longer wire or larger load. ! recommendation : no more than 10 loads Family Fanout Sink Current Source Current recommended fan out:
TTL (74XX) TTL (74LSXX) TTL (74SXX) TTL (74ALSXX) CMOS (74HCXX) CMOS (CD4XXX) NMOS 1 5 1 10 10 10 10 -1.6 mA -0.4 mA -2.0 mA -0.2 mA -1.0 A -1.0 A -10 A 40 A 20 A 50 A 20 A 1.0 A 1.0 A 10 A
22
FAQ
What are sink and source current, and the sign of the current?
The component source current is the current that it will output to the next stage device when the component's output pin is high. The component sink current is the current that it will take in from its output pin when its output is at its logic low state. The minus sign for sink current is to denote that the current is flowing back the component.
Noise immunity
The noise immunity for logic low and high are defined in pp22 of ch05. Pls use these definitions for the noise immunity. Please note that noise immunity is the difference between the INPUT and OUTPUT, not difference between logic 0 and logic 1. The old slide that I showed in the class is not correct. Let's use the definition in your lecture note.
FAQ
Why uses the difference between input and output for noise immunity calculation?
Let's take a look at the noise immunity for logic 0. If you look the figure in pp21, the output disallow range is bigger than the undetermined range for the input, and V_IL (max)> V_OL(max). So if the output of logic 0 from a chip is corrupted with noise dN, the aggregated signal into the other chip will has a max. value of V_OL(max)+dN. This value should be less than V_IL so that the total amplitude will not fall in the undetermined range. So noise immunity for logic 0 is defined as V_IL(max)-V_OL(max). By the same token, the noise immunity for logic 1 can be defined.
24
Microprocessors and Computer Systems

Chapter 6
8284 Clock Generator Bus Demux Bus Cycle
(Brey's ch8; Hall's ch7)
ELE 3230
8284 Clock Generator

8284 is an integrated circuit which generates the CLOCK, READY and RESET signals needed in the 8088. Internally the 8284 consists of an oscillator circuit (which needs an external crystal oscillator), dividers, flip-flops, buffers and logic gates. The external crystal frequency is divided by 3 to produce the basic clock frequency as shown 10 ns Max 10 ns Max below:
6 +5 3.9 118.33 ns Min 1.5 .6 0 -.5 200 ns Min 500 ns Max
68.66 ns Min

RES X1 X2 D Q CRYSTAL OSCILLATOR CK OSC RESET
F/C 3 SYNC EFI CSYNC RDY1 AEN1 CK RDY2 AEN2 ASYNC D FF1 Q D FF2 CK Q READY 2 SYNC PCLK
CLK
Internal Block Diagram of the 8284 clock generator


CSYNC PCLK
AEN1 RDY1
1 2 3 4 5 6 7 8 9
8284A
18 17 16 15 14 13 12 11 10
Vcc X1 X2
ASYNC
READY RDY2
AEN2
EFI
F/ C
OSC
RES
CLK GND
RESET
8284 Output Pins

PCLK - peripheral clock outputs clock signal which is at half the frequency of the main CLK output. CLK - clock outputs a 33% duty cycle periodic clock which runs at one third the frequency as the EFI or crystal frequency. OSC - oscillator output provides a buffered periodic waveform running at the crystal frequency. Output is suitable for driving the EFI input of another 8284. RESET - generates an output suitable for the reset input of the 8088. READY - generates READY signal suitable for 8088 READY input.
Relation between CLK and PCLK
OSC
CLK
PCLK
8284 Input Pins

VCC, GND - power supply pins RDY1 and RDY2 - bus ready accepts input of the bus ready signal AEN1, AEN2 - address enable (qualifies RDY1 and RDY2) ASYNC - ready synchronization select (selects one or two stages of synchronization for the RDY1 and RDY2 inputs
X1, X2 - crystal inputs (for connection of external clock signal input) EFI - external frequency input (external clock signal input) CSYNC - clock synchronization used with the EFI to synchronize the clock output in multiprocessor systems. MUST BE GROUNDED if the crystal oscillator is used. F/C - frequency/crystal (selects crystal oscillator or EFI as source) RES - reset input (accept input from a switch for generating reset)
Example - A simple 8284 circuit

The 8284 can be used simply to generated the CLOCK signal as shown below:
5V 4.7K 8088 RDY1 RDY2 EFI CLK F/C CSYNC AEN1 READY AEN2 ASYNC 510 X1 510 15MHz 5V 4.7K Reset Switch 100nF X2 RES 8284 RESET
CLK READY RESET
5V 4.7K
If WAIT states for slow memory or IO peripherals are needed, the circuit must be modified.
Vcc
Minimum Mode System Block Diagram

8284A RES clock generator CLK MN/ MX READY IO/ M RESET RD WR 8088 INTA CPU DT/ R DEN ALE AD0-AD7 A8-A19 INTR
Vcc
GND
GND
STB OE
Address /data 8282 Latch

(1, 2 or 3)
Address
T OE 8286 Transceiver
Data
EN 8259A Interrupt controller
WEOE
OE 27162 PROM
CS
RD WR Peripheral
2142 RAM (2)
IR0-7
INT
Demultiplexing the Address and Data Bus

Address and data bus are multiplexed in 8086 (AD0AD15) and 8088(AD0-AD7) to reduce the number of pins required. Address and Data need to be demultiplexed from the bus. (Why not leave it multiplexed?) How to maintain a stable address throughout a read or write cycle?
10
Demultiplexing the Address and Data Bus on 8088

Two transparent latches (74LS373) are used for demultiplexed. ALE indicates when address information is on AD0-AD7. In maximum mode, ALE is generated by the bus controller.
A19/S6 A18/S5 A17/S4 A16/S3 A15 A14 A13 A12 A11 A10 A9 A8
OE 373 G
8088
A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
Address bus
Minimum mode address/data demultiplexing
ALE AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 IO/M RD WR MN/MX
373
OE
D7 D6 D5 D4 D3 D2 D1 D0 IO/M RD WR
Data bus
Control bus
+5V
11
Latches
The address and data bus of the 8088 are multiplexed on pins AD0 to AD7. Address information are contained on AD0-AD7 only when ALE (address latch enable) is asserted. External Latches are needed to store (latch) the addressing information before AD0-AD7 change to carrying data. A latch simply consists of a D-type flip-flop with additional logic to select when to read and output data.
12
Latches and flip-flops

D latch
D CK
Q
D X 0 1
S 1 1 1 1 0 1 0 R 1 1 1 1 1 0 0 D 1 0 X X X X X
CK 0 1 1
Q Q Q Q 0 1 1 0
N
S D Q
D flip-flop
CK Q R
CK 0 1 X X X
Q 1 0 Q Q 1 0
Q 0 1 Q Q 0 1
13
Latches(cont.)
Integrated circuits containing many latches (one latch is needed per bit) are available to perform the latching function of an address line e.g. 8282, 74LS373. These packages typically have a single input, called strobe (STB), latch enable (LE) or Gate (G), which qualifies the data (i.e. passes the data to the flip-flops only when it the strobe or gate input is high). Some latches also have an output enable (OE) input which qualifies the output data (when OE is low, the outputs are open circuit).
14
8088 Fan-out and Buffers

In order to drive the system buses, which typically have many devices attached and with large capacitance, the address and data output pins must be buffered. A buffer merely amplifies the output current. Demultiplexed pins are already buffered by latches (e.g. 74LS373). Un-multiplexed address pins can be buffered by 74LS245 octal bi-directional buffer and 74LS244 uni-directional buffer.
15
Example: 8088 Fully Buffered Buses

DT/R, DEN and ALE signals are available from the 8088 in minimum mode mode only. They must be derived from the bus controller when the 8088 operates in maximum mode.
IO/M RD WR A19/S6 A18/S5 A17/S4 A16/S3 A15 A14 A13 A12 A11 A10 A9 A8 OE OE
244 373
G A13
IO/M RD WR A19 A18 A17 A16 A15 A14 A12 A11 A10 A9 A8 A7 A6 A5 A4 A2 A1 A0
Buffered Control bus
8088
Example of bus buffering in 8088 (minimum mode system)
244
OE
Buffered Address bus
ALE
A3
G AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0
373
OE B7 A7 B6 A6 B5 A5 B4 A4 B3 A3 B2 A2 B1 A1 A0 G DIR B0 D7 D6 D5 D4 D3 D2 D1 D0
Buffered Data bus
DT/R DEN
16
Bidirectional Buffers
Information is transferred in both directions on the data bus - hence the data bus buffer must be bidirectional. A bidirectional buffer has a direction (DIR) input which indicates the direction of data transfer. The direction input to the buffer can be taken from the DT/R (data transmit/receive) output of the 8088 (minimum mode system) or bus controller (maximum mode 8088 system). Examples of bidirectional buffers include the 74LS245 and 8286.
Inputs/outputs
Outputs/inputs
EN
DIR
17
8088 Fan-out and Buffers

The output pins of the 8088 have a limited fan out (the output current can only drive a finite number of derives and large capacitive loading on the output will cause problems with dynamic signals Recommended 8088 Fan-out
Logic family Sink current Source Current fanout from (mA) 8088 ( A) TTL (74XX) -1.6 40 1 TTL (74LSXX) -0.4 20 5 TTL (74SXX) -2 50 1 TTL (74ALSXX) -0.2 20 10 CMOS (74HCXX) -0.001 1 10 CMOS (CD4XXX) -0.001 1 10 NMOS -0.01 10 10
Q: Pros and cons of buffer?

Example of Basic 8086 System Timing

(4+NWAIT)=TCY T1 T2 T3 TWAIT T4 T1 T2 (4+NWAIT)=TCY T3 TWAIT T4
CLK ALE M/IO ADDR/STATUS ADDR/DATA RD

READY READY BHE A19-A16 A15-A0 S7-S3
BUS RESERVERED FOR DATA IN
BHE A19-A16 A15-A0
S7-S3
D15-D0 VALID
DATA OUT D15-D0
READY
WAIT WAIT
DT/R DEN
MEMORY ACCESS TIME
WR
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Bus Timing of the 8088

Access to memory and I/O operates in bus-cycles. Bus cycles are periods of time equal to four system clocking periods (1 clock period is often called a T state). For instance, if the 8088 operates at 5MHz, the bus cycle rate (which is maximum rate of data transfer) is at 5/4 MHz.
Example of BUS READ CYCLE The basic steps of the read cycle (simplified) are: 1. Put memory address on the address bus (T1) 2. Issue a read (RD) memory signal (T2-T3) 3. Read the data from the data bus (T3)
20
Bus Timing of the 8088 READ Cycle

Example - 8088/8086 Read bus cycle (simplified)
ONE BUS CYCLE
T1 CLK
T2
T3
T4
ADDRESS
VALID ADDRESS
ADDRESS/DATA
ADDRESS
DATA FROM MEMORY
RD
21
Bus Timing Diagrams (General)

To transfer data without error on the system bus, the signals in the bus must change and hold the values within a certain period of time in a bus cycle. Physically, a system bus consists of conducting wires or tracks on circuit board. These have distributed inductance and capacitance which tend to distort the signal waveforms. Long system buses can have clock skew (there is a delay in signals received by distant peripherals - and their clock is slightly out of phase with the clock received by the microprocessor). The rise-time, fall-time, and duration of signals must be within the specifications of the device or microprocessor - otherwise errors will occur in transferring data. The manufacturers data sheet contain important information on the timing requirements which can be quite demanding.
Bus Cycle Operation

T1 - start of bus cycle. Actions include setting control signals (or S0-S2 status lines) to give the required values for ALE, DT/R and IO/M , and putting a valid address onto the address bus.
T2 - the RD or WR control signals are issued, DEN is asserted and in the case of a write, data is put onto the data bus. The DEN turns on the data bus buffers to connect the cpu to the external data bus. The READY input to the cpu is sampled at the end of T2 and if READY is low, a wait state TW (one or more) is inserted before T3 begins.
23
Bus Cycle Operation

T3 - this clock period is provided to allow memory to access the data. If the bus cycle is a read cycle, the data bus is sampled at the end of T3. T4 - all bus signals are deactivated in preparation for the next clock cycle. The 8088 also finishes sampling the data (in a read cycle) in this period. For the write cycle, the trailing edge of the WR signal transfers data to the memory or I/O, which activates and write when WR returns to logic 1 level.
24
Read Cycle Timing

The most important information contained in the read timing diagram is the amount of the time allowed for getting data from memory. Memory chips usually have a specified memory access time. The memory access time is defined as the interval from when a valid address is put on the address bus (near the start of T1) to the time when the data is read (near the end of T3). The permitted memory access time is therefore less than three T states if no wait states are added. To find the exact access time permitted by the read timing diagram: 1. Find the maximum interval necessary for a valid address to appear after the start of T1. This interval is given the symbol TCLAV (clock-to-address valid) the microprocessor data sheet (For a 5MHz 8088, TCLAV=110ns)
25
Read Cycle Timing (cont.)

2. Valid data must appear on the data bus before the end of T3 in order to allow the data to be read. The minimum time interval before the end of T3 for valid data to appear is given the symbol TDVCL (data valid-to clock) and is specified as 30ns for the 5MHz 8088. 3. The maximum memory access time=3T-TCLAV-TDVCL which, for the 5MHz 8088, is 600-110-30=460ns. Actually the memory access time must be less than this since there will be propagation delays in going through buffers (about another 40ns).
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Read Cycle Timing Information from Data Sheet
Bus Timing of 8088 Write Bus Cycle

ONE BUS CYCLE
T1 CLK
T2
T3
T4
ADDRESS
VALID ADDRESS
ADDRESS/DATA
ADDRESS
DATA WRITE TO MEMORY
WR
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Example - 8088/8086 Write Bus Cycle (simplified)

Write bus cycle (simplified) consists of : 1. Put memory address on the address bus (T1) 2. Issue a write ( WR ) to memory signal (T2-T3) 3. Send data to data bus (T2-T3) and write to memory Actual (non-simplified) read and write bus cycle include changes on other signals such as M/IO, ALE, DEN, DT/R and READY. The actual cycles will be investigated in detail later. T4 in the bus cycle is used to deactivate all the signals in preparation for the next bus cycle (it is also the time when the 8088 samples the READY signal to see if extra wait states are needed)
29
Write Cycle Timing

Write cycle is very similar to the read cycle. Main differences are 1. RD Strobe is replaced by WR 2. Data bus contains data for memory rather than data from memory 3. DT/R =1instead of DT/R =0 The most critical of the write timing diagram is the time interval between the point when WR becomes logic 1 and the time when data are removed from the data bus, since data are only written after the trailing edge of the strobe. This critical time interval is given the label TWHDX and is specified as 88ns for 5MHz 8088.
30
Write Cycle Timing

T1 VCH CLK(8284 Output) VCL
TCLAV TCLDV TCLAX TCHDX TCH1CH2
T2
T3
TCL2CL1
TW
T4
AD7-AD0
TCVCTV
AD7-AD0
AD0
DATA OUT
TWHDX TCVCTV
WRITE CYCLE NOTE 1
DEN
TCVCTV
TWLWH
WR
TCVCTX
31
READY and the WAIT state

If the access time for a memory device is longer than the memory access time calculated, need to give extra clock periods, wait state Tw, for memory. The READY input is sampled at the end of T2 and again, if applicable, in the middle of Tw. If READY is a logic 0 on 1-to-0 clock transition, then Tw is inserted between T2 and T3. And will check for logic 1 on 0-to-1 clock transition in the middle of Tw to see if it shall go back T3. During the wait state, signals on the buses remain the same as they were at the start of the WAIT state. By having the WAIT state, slow memory and devices has at least one more cycle (200ns for 5 MHz 8088) to get its data output. The READY signal is synchronized by the clock generator 8284A.
32
READY and RDY input timing

T2 CLK TW T3
8ns READY
30ns
(a) 8088/86 READY Input Timing

T2 CLK TW T3
35ns RDY 0ns
(b) 8284 RDY Input Timing

33
Maximum Mode Bus Buffering and Demultiplexing

Vcc CLK
GND
8284A RES RDY CLK READY RESET 8088 GND WAIT STATE GENERATOR STB AD0-AD7 A8-A19 DATA DIR LS373
S0 S1 S2
S0 S1 S2
8288
DEN
DT/R
ALE
ADDR
LS245
8288 bus controller generates control signals needed by interrupt controllers and peripheral devices (memory)
Maximum Mode System Block Diagram

V cc
MN/ MX S0
GND
S0 S1
CLK
MRDC MWTC
8284A RES clock generator
S1 CLK READY RESET S2
8288 AMWC
NC NC
S2 Bus Ctrl IORC DEN IOWC DT/ R A IOWC ALE INTA
GND
8088 MPU
STB
GND
AD 0 AD 7 INTR
OE 8282 Latch (1, 2 or 3)
A 8 A 19
Address/data
Address
OE
8286 Transceiver
Data
EN
WEOE
OE
CS
RDWR
2142 RAM (2) 8259A Interrupt controller IR 0-7

INT
27162 PROM
Peripheral
35
8088/8086 (maximum mode) Read Bus Cycle (detailed)

T1 CLK S2 * S0 Address/data and BHE/S7 Address/data (AD15-AD0) *ALE *MRDC or IORC *DT/R *DEN S2 -S0 S2 -S0 Inactive BHE, A19-A16 S7 - S3 A15 - A0 Data in D15 - D0 Float T2 One bus cycle T3 T4
Bus master (8088) actions S0-S2 changed for ALE Output A0-A19 (ALE asserted) DT/R =0, change S0 - S2 to DEN Wait until READY asserted Read data from data bus set S0 - S2 to 111
Slave (memory) Actions Decode address, negate RDY Put data on data bus Assert RDY
36
8088/8086 (maximum mode) Write Bus Cycle (detailed)

T1 CLK S2 * S0 Address/data and BHE/S7 Address/data (AD15-AD0) *ALE *AMWC or AIOWC *MWTC or IOWC *DEN S2 * S0 S2 * S0 Inactive BHE, A19-A16 S7 - S3 A15 - A0 Data in D15 - D0 Float T2 One bus cycle T3 T4
Bus master (8088) actions S0-S2 changed for ALE Output A0-A19 (ALE asserted) DT/R =1, change S0 - S2 to DEN Output data onto data bus Wait until READY asserted read data, set S0 - S2 to 111
Slave (memory) Actions Decode address, negate RDY
Store data Assert RDY

37
Pin Diagram of 8085

X1 X2 RESET OUT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 SOD SID TRAP RST 7.5 RST 6.5 RST 5.5 INTR _____ INTA AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 VSS 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 Vcc HOLD HLDA CLK ( OUT) READY
___ 1
DMA
_________________
Serial i/p, o/p signals
RESET IN
__
IO / M S RD
___
8085 A
WR ALE S0 A15 A14 A13 A12 A11 A10 A9 A8
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Signal Groups of 8085

+5V XTAL X1 X2 5 4 Vcc Vss A15 A8 AD7 AD0 GND
SID SOD TRAP RESET 7.5 RESET 6.5 RESET 5.5 INTR READY HOLD HLDA
______
High order Address bus Multiplexed address / data bus
ALE S1 S0
____ ____
___
______________
RESET IN
IO / M
RD
INTA RESET OUT

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WR CLK OUT
2
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INTA INT R
RES 5.5
RES 6.5
RES 7.5
TRAP
SID
SIO
INTERRUPT CONTROL
SERIAL I / O CONTROL 8 BIT INTERNAL DATA BUS
ACCUMULATOR (8)
TEMP REG(8)
INSTRUCTION REGISTER ( 8 ) R E G. S INSTRUCTIO N DECODER AND MACHINE ENCODING E L W
MULTIPLXER ( 8 ) C ) REG ( 8 REG ( 8 REG ( 8 ) ( 16 )
FLAG ( 5) ARITHEMETIC LOGIC UNIT ( ALU) +5V GND X1 X2 CLK GEN CONTRO L READY R WR AL D E TIMING AND CONTROL (8) FLIP FLOPS
TEMP . REG. B REG (8)
D REG ( 8 E ) ) H REG ( 8 L ) STACK POINTER
PROGRAM COUNTER ( 16 E ) INCREAMENT / DECREAMENT C ADDRESS LATCH ( 16 ) T
STATUS
DMA
ADDRESS BUFFER ( 8 )
DATA / ADDRESS BUFFER ( 8 )
CLK OUT
RESET S0 S1 IO / M HOLD HLDA RESET IN OUT
A 15 A8 ADDRESS BUS
AD7 AD0 ADDRESS / BUFFER BUS
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Flag Registers
D7 S D6 Z D5 D4 AC D3 D2 P D1 D0 CY

INDIVIDUAL B, C, D, E, H, L COMBININATON B & C, D & E, H & L
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AH BH CH GENERAL REGISTERS DH SP BP SI DI
AL BL CL DL ADDRESS BUS ( 20 ) BITS DATA BUS ( 16 ) BITS ES CS SS DS ALU DATA BUS 16 BITS BUS IP 8 0 8
TEMPORARY REGISTERS
CONTRO 6 L LOGIC B U S EU CONTROL SYSTEM Q BUS 8 BIT
ALU
INSTRUCTION QUEUE 1 2 3 4 5 6
FLAGS EXECUTION UNIT ( EU )
BUS INTERFACE UNIT ( BIU)
Fig:
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Pin Diagram of 8086

GND AD14 AD13 AD12 AD11 AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 NMI INTR CLK GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 VCC AD15 A16 / S3 A17 / S4 A19/S6
____
A18 / S5
_____
8086 CPU
BHE / S7
_____ _____
MN/MX
___
RD
___
RQ _____
/ GT0 ( HOLD)
____
( HLDA) RQ / GT 1 ___ _______

LOCK (WR)
___
____
___
S 1 ___ S0
______
(DT / R) _____
(DEN)
________
S2
(M / IO )
QS1 (INTA) TEST READY RESET
QS0 (ALE)
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VCC
GND A0 - A15, A16 / S3 A19/S6
INTR
_____
INTA INTERRUPT
______
ADDRESS / DATA BUS D0 - D15 8086 MPU ALE ___ BHE / S7

__
TEST NMI RESET
INTERFACE
HOLD HLDA VCC

____
DMA INTERFACE
MEMORY I/O CONTROLS
M / IO
____
__
DT / R
RD
_____
_____
WR
MN / MX
MODE SELECT
DEN READY
CLK
Signal Description of 8086

The Microprocessor 8086 is a 16-bit CPU available in different clock rates and packaged in a 40 pin CERDIP or plastic package. The 8086 operates in single processor or multiprocessor configuration to achieve high performance. The pins serve a particular function in minimum mode (single processor mode ) and other function in maximum mode configuration (multiprocessor mode ). The 8086 signals can be categorised in three groups. The first are the signal having common functions in minimum as well as maximum mode.
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Signal Description of 8086 (cont..)

The second are the signals which have special functions for minimum mode and third are the signals having special functions for maximum mode. The following signal descriptions are common for both modes. AD15-AD0 : These are the time multiplexed memory I/O address and data lines. Address remains on the lines during T1 state, while the data is available on the data bus during T2, T3, Tw and T4. These lines are active high and float to a tristate during interrupt acknowledge and local bus hold acknowledge cycles.
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A19/S6,A18/S5,A17/S4,A16/S3 : These are the time multiplexed address and status lines. During T1 these are the most significant address lines for memory operations. During I/O operations, these lines are low. During memory or I/O operations, status information is available on those lines for T2,T3,Tw and T4. The status of the interrupt enable flag bit is updated at the beginning of each clock cycle.
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The S4 and S3 combinedly indicate which segment register is presently being used for memory accesses as in below fig. These lines float to tri-state off during the local bus hold acknowledge. The status line S6 is always low . The address bit are separated from the status bit using latches controlled by the ALE signal.
S4 0 0 1 1 S3 0 1 0 1 Indication Alternate Data Stack Code or none Data
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BHE/S7 : The bus high enable is used to indicate the transfer of data over the higher order ( D15-D8 ) data bus as shown in table. It goes low for the data transfer over D15-D8 and is used to derive chip selects of odd address memory bank or peripherals. BHE is low during T1 for read, write and interrupt acknowledge cycles, whenever a byte is to be transferred on higher byte of data bus. The status information is available during T2, T3 and T4. The signal is active low and tristated during hold. It is low during T1 for the first pulse of the interrupt acknowledge cycle.
BHE 0 0 1 1 A0 0 1 0 1 Indication Whole word address Upper byte bytefrom fromor orto toodd even address Lower byte from or to even address None
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RD Read : This signal on low indicates the peripheral that the processor is performing s memory or I/O read operation. RD is active low and shows the state for T2, T3, Tw of any read cycle. The signal remains tristated during the hold acknowledge. READY : This is the acknowledgement from the slow device or memory that they have completed the data transfer. The signal made available by the devices is synchronized by the 8284A clock generator to provide ready input to the 8086. the signal is active high.
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INTR-Interrupt Request : This is a triggered input. This is sampled during the last clock cycles of each instruction to determine the availability of the request. If any interrupt request is pending, the processor enters the interrupt acknowledge cycle. This can be internally masked by resulting the interrupt enable flag. This signal is active high and internally synchronized. TEST : This input is examined by a WAIT instruction. If the TEST pin goes low, execution will continue, else the processor remains in an idle state. The input is synchronized internally during each clock cycle on leading edge of clock.
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NMI- Nonmaskable interrupt : This is an edge triggered input which causes a Type 2 interrupt. The NMI is not maskable internally by software. A transition from low to high initiates the interrupt response at the end of the current instruction. This input is internally synchronized. RESET : This input causes the processor to terminate the current activity and start execution from FFF0H. The signal is active high and must be active for at least four clock cycles. It restarts execution when the RESET returns low. RESET is also internally synchronized. Vcc +5V power supply for the operation of the internal circuit. GND ground for internal circuit.
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CLK- Clock Input : The clock input provides the basic timing for processor operation and bus control activity. Its an asymmetric square wave with 33% duty cycle. MN/MX : The logic level at this pin decides whether the processor is to operate in either minimum or maximum mode. The following pin functions are for the minimum mode operation of 8086. M/IO Memory/IO : This is a status line logically equivalent to S2 in maximum mode. When it is low, it indicates the CPU is having an I/O operation, and when it is high, it indicates that the CPU is having a memory operation. This line becomes active high in the previous T4 and remains active till final T4 of the current cycle. It is tristated during local bus hold acknowledge .

INTA Interrupt Acknowledge : This signal is used as a read strobe for interrupt acknowledge cycles. i.e. when it goes low, the processor has accepted the interrupt. ALE Address Latch Enable : This output signal indicates the availability of the valid address on the address/data lines, and is connected to latch enable input of latches. This signal is active high and is never tristated. DT/R Data Transmit/Receive: This output is used to decide the direction of data flow through the transreceivers (bidirectional buffers). When the processor sends out data, this signal is high and when the processor is receiving data, this signal is low.
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DEN Data Enable : This signal indicates the availability of valid data over the address/data lines. It is used to enable the transreceivers ( bidirectional buffers ) to separate the data from the multiplexed address/data signal. It is active from the middle of T2 until the middle of T4. This is tristated during hold acknowledge cycle. HOLD, HLDA- Acknowledge : When the HOLD line goes high, it indicates to the processor that another master is requesting the bus access. The processor, after receiving the HOLD request, issues the hold acknowledge signal on HLDA pin, in the middle of the next clock cycle after completing the current bus cycle.
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MAM/M1/LU4/V1/2004
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At the same time, the processor floats the local bus and control lines. When the processor detects the HOLD line low, it lowers the HLDA signal. HOLD is an asynchronous input, and is should be externally synchronized. If the DMA request is made while the CPU is performing a memory or I/O cycle, it will release the local bus during T4 provided : The request occurs on or before T2 state of the current cycle. The current cycle is not operating over the lower byte of a word. The current cycle is not the first acknowledge of an interrupt acknowledge sequence.
1. 2. 3.
M. Krishna Kumar
MAM/M1/LU4/V1/2004
19

4. A Lock instruction is not being executed. The following pin function are applicable for maximum mode operation of 8086. S2, S1, S0 Status Lines : These are the status lines which reflect the type of operation, being carried out by the processor. These become activity during T4 of the previous cycle and active during T1 and T2 of the current bus cycles.
S2 0 0 0 0 1 1 1 1
M. Krishna Kumar
S1 0 0 1 1 0 0 1 1
S0 0 1 0 1 0 1 0 1
Indication Interrupt Acknowledge Read I/O port Write I/O port Halt Code Access Read memory Write memory Passive
MAM/M1/LU4/V1/2004 20

LOCK : This output pin indicates that other system bus master will be prevented from gaining the system bus, while the LOCK signal is low. The LOCK signal is activated by the LOCK prefix instruction and remains active until the completion of the next instruction. When the CPU is executing a critical instruction which requires the system bus, the LOCK prefix instruction ensures that other processors connected in the system will not gain the control of the bus. The 8086, while executing the prefixed instruction, asserts the bus lock signal output, which may be connected to an external bus controller.

QS1, QS0 Queue Status: These lines give information about the status of the code-prefetch queue. These are active during the CLK cycle after while the queue operation is performed. This modification in a simple fetch and execute architecture of a conventional microprocessor offers an added advantage of pipelined processing of the instructions. The 8086 architecture has 6-byte instruction prefetch queue. Thus even the largest (6-bytes) instruction can be prefetched from the memory and stored in the prefetch. This results in a faster execution of the instructions. In 8085 an instruction is fetched, decoded and executed and only after the execution of this instruction, the next one is fetched.

By prefetching the instruction, there is a considerable speeding up in instruction execution in 8086. This is known as instruction pipelining. At the starting the CS:IP is loaded with the required address from which the execution is to be started. Initially, the queue will be empty an the microprocessor starts a fetch operation to bring one byte (the first byte) of instruction code, if the CS:IP address is odd or two bytes at a time, if the CS:IP address is even. The first byte is a complete opcode in case of some instruction (one byte opcode instruction) and is a part of opcode, in case of some instructions ( two byte opcode instructions), the remaining part of code lie in second byte.

But the first byte of an instruction is an opcode. When the first byte from the queue goes for decoding and interpretation, one byte in the queue becomes empty and subsequently the queue is updated. The microprocessor does not perform the next fetch operation till at least two bytes of instruction queue are emptied. The instruction execution cycle is never broken for fetch operation. After decoding the first byte, the decoding circuit decides whether the instruction is of single opcode byte or double opcode byte. If it is single opcode byte, the next bytes are treated as data bytes depending upon the decoded instruction length, otherwise, the next byte in the queue is treated as the second byte of the instruction opcode.

The second byte is then decoded in continuation with the first byte to decide the instruction length and the number of subsequent bytes to be treated as instruction data. The queue is updated after every byte is read from the queue but the fetch cycle is initiated by BIU only if at least two bytes of the queue are empty and the EU may be concurrently executing the fetched instructions. The next byte after the instruction is completed is again the first opcode byte of the next instruction. A similar procedure is repeated till the complete execution of the program.
M. Krishna Kumar
MAM/M1/LU4/V1/2004
25

The fetch operation of the next instruction is overlapped with the execution of the current instruction. As in the architecture, there are two separate units, namely Execution unit and Bus interface unit. While the execution unit is busy in executing an instruction, after it is completely decoded, the bus interface unit may be fetching the bytes of the next instruction from memory, depending upon the queue status.
QS1
0 0 1 1
QS0
0 1 0 1
Indication No operation First byte of the opcode from the queue Empty queue Subsequent byte from the queue
M. Krishna Kumar
MAM/M1/LU4/V1/2004
26

RQ/GT0, RQ/GT1 Request/Grant : These pins are used by the other local bus master in maximum mode, to force the processor to release the local bus at the end of the processor current bus cycle. Each of the pin is bidirectional with RQ/GT0 having higher priority than RQ/GT1. RQ/GT pins have internal pull-up resistors and may be left unconnected. Request/Grant sequence is as follows: A pulse of one clock wide from another bus master requests the bus access to 8086.
MAM/M1/LU4/V1/2004 27
1.
M. Krishna Kumar

2. During T4(current) or T1(next) clock cycle, a pulse one clock wide from 8086 to the requesting master, indicates that the 8086 has allowed the local bus to float and that it will enter the hold acknowledge state at next cycle. The CPU bus interface unit is likely to be disconnected from the local bus of the system. A one clock wide pulse from the another master indicates to the 8086 that the hold request is about to end and the 8086 may regain control of the local bus at the next clock cycle. Thus each master to master exchange of the local bus is a sequence of 3 pulses. There must be at least one dead clock cycle after each bus exchange.
3.
M. Krishna Kumar
MAM/M1/LU4/V1/2004
28

The request and grant pulses are active low. For the bus request those are received while 8086 is performing memory or I/O cycle, the granting of the bus is governed by the rules as in case of HOLD and HLDA in minimum mode.
M. Krishna Kumar
MAM/M1/LU4/V1/2004
29
General Bus Operation

The 8086 has a combined address and data bus commonly referred as a time multiplexed address and data bus. The main reason behind multiplexing address and data over the same pins is the maximum utilisation of processor pins and it facilitates the use of 40 pin standard DIP package. The bus can be demultiplexed using a few latches and transreceivers, when ever required. Basically, all the processor bus cycles consist of at least four clock cycles. These are referred to as T1, T2, T3, T4. The address is transmitted by the processor during T1. It is present on the bus only for one cycle.
M. Krishna Kumar
MAM/M1/LU4/V1/2004
30
General Bus Operation ( cont..)

During T2, i.e. the next cycle, the bus is tristated for changing the direction of bus for the following data read cycle. The data transfer takes place during T3, T4. In case, an address device is slow NOT READY status the wait status Tw are inserted between T3 and T4. These clock states during wait period are called idle states (Ti), wait states (Tw) or inactive states. The processor used these cycles for internal housekeeping. The address latch enable (ALE) signal is emitted during T1 by the processor (minimum mode) or the bus controller (maximum mode) depending upon the status of the MN/MX input.
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MAM/M1/LU4/V1/2004
31

The negative edge of this ALE pulse is used to separate the address and the data or status information. In maximum mode, the status lines S0, S1 and S2 are used to indicate the type of operation. Status bits S3 to S7 are multiplexed with higher order address bits and the BHE signal. Address is valid during T1 while status bits S3 to S7 are valid during T2 through T4.
M. Krishna Kumar
MAM/M1/LU4/V1/2004
32
T1 CLK ALE S2 S0 Add/stat Add/data A0-A15 RD/INTA READY DT/R DEN WR A19-A16 BHE
Memory read cycle T2 T3 Tw
T4
T1
Memory write cycle T2 T3 Tw
T4
S3-S7 Bus reserve for Data In
A19-A16 BHE D15-D0
S3-S7
Data Out D15 D0 A0-A15 Ready
D15-D0
Ready Wait Wait
Memory access time General Bus Operation Cycle in Maximum Mode

Systems Design & Programming Memory Types Two basic types: ROM: Read-only memory RAM: Read-Write memory
Memory I
CMPE 310
Four commonly used memories: ROM Flash (EEPROM) Static RAM (SRAM) Dynamic RAM (DRAM) Generic pin conguration: Address connection A0 A1 ... AN
WE OE
Write Read Select
O0 O1 ...
CS Output/Input-output connection 1
ON
AR
YLAND BA L
TI
IVERSITY O F
U M B C
1966
UMBC
MO
(Feb. 25, 2002)
RE COUNT Y
UN
Systems Design & Programming
Memory I
CMPE 310
Memory Chips The number of address pins is related to the number of memory locations. Common sizes today are 1K to 256M locations. Therefore, between 10 and 28 address pins are present. The data pins are typically bi-directional in read-write memories. The number of data pins is related to the size of the memory location. For example, an 8-bit wide (byte-wide) memory device has 8 data pins. Catalog listing of 1K X 8 indicate a byte addressable 8K memory. Each memory device has at least one chip select (CS) or chip enable (CE) or select (S) pin that enables the memory device. This enables read and/or write operations. If more than one are present, then all must be 0 in order to perform a read or write.
AR
YLAND BA L
TI
IVERSITY O F
U M B C
1966
UMBC
MO
(Feb. 25, 2002)
RE COUNT Y
UN
Memory I
CMPE 310
Memory Chips Each memory device has at least one control pin. For ROMs, an output enable (OE) or gate (G) is present. The OE pin enables and disables a set of tristate buffers. For RAMs, a read-write (R/W) or write enable (WE) and read enable (OE) are present. For dual control pin devices, it must be hold true that both are not 0 at the same time. ROM: Non-volatile memory: Maintains its state when powered down. There are several forms: ROM: Factory programmed, cannot be changed. Older style. PROM: Programmable Read-Only Memory. Field programmable but only once. Older style. EPROM: Erasable Programmable Read-Only Memory. Reprogramming requires up to 20 minutes of high-intensity UV light exposure.
YLAND BA L
TI
AR
IVERSITY O F
U M B C
1966
UMBC
MO
(Feb. 25, 2002)
RE COUNT Y
UN
Memory I
CMPE 310
Memory Chips ROMs (cont): Flash EEPROM: Electrically Erasable Programmable ROM. Also called EAROM (Electrically Alterable ROM) and NOVRAM (NOn-Volatile RAM). Writing is much slower than a normal RAM. Used to store setup information, e.g. video card, on computer systems. Can be used to replace EPROM for BIOS memory.
AR
YLAND BA L
TI
IVERSITY O F
U M B C
1966
UMBC
MO
(Feb. 25, 2002)
RE COUNT Y
UN
Systems Design & Programming EPROMs Intel 2716 EPROM (2K X 8): A7 A6 A5 A4 A3 A2 A1 A0 O0 O1 O2 GND 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13
Memory I
CMPE 310
VCC VPP is used to program the device A8 by applying 25V and pulsing PGM A9 while holding CS high. VPP CS Data Outputs A10 PD/PGM O7 Chip Select O6 CS Output O5 PWR Down O4 PD/PGM Buffers Prog Logic O3 Address Inputs Y Decoder Y-Gating
2K x 8 EPROM Pin(s) Function A0-A10 Address PD/PGM Power down/Program Chip Select CS Outputs O0-O7
M
2716
X Decoder
16,384 Cell Matrix
AR
YLAND BA L
TI
IVERSITY O F
U M B C
1966
UMBC
MO
(Feb. 25, 2002)
RE COUNT Y
UN
Systems Design & Programming EPROMs 2716 Timing diagram:
Memory I
CMPE 310
Address tOH CS High Z tACC1 Data Out Valid tDF
Read Mode (PD/PGM =VIL) Sample of the data sheet for the 2716 A.C. Characteristics.
Symbol tACC1 tOH tDF ... Parameter Addr. to Output Delay Addr. to Output Hold Chip Deselect to Output Float ... Limits Unit Min Typ. Max 250 450 ns 0 ns 0 100 ns ... ... ... ... Test Condition PD/PGM= CS =VIL PD/PGM= CS =VIL PD/PGM=VIL ...
This EPROM requires a wait state for use with the 8086 (460ns constraint).
M
AR
YLAND BA L
TI
IVERSITY O F
U M B C
1966
UMBC
MO
(Feb. 25, 2002)
RE COUNT Y
UN
Systems Design & Programming SRAMs TI TMS 4016 SRAM (2K X 8): A7 A6 A5 A4 A3 A2 A1 A0 DQ1 DQ2 DQ3 GND 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 VCC A8 A9 W G A10 S DQ8 DQ7 DQ6 DQ5 DQ4
Memory I
CMPE 310
Pin(s) A0-A10 DQ0-DQ7 S (CS) G (OE) W (WE)
TMS4016
Function Address Data In/Data Out Chip Select Read Enable Write Enable
2K x 8 SRAM Virtually identical to the EPROM with respect to the pinout. However, access time is faster (250ns). See the timing diagrams and data sheets in text. SRAMs used for caches have access times as low as 10ns.
AR
YLAND BA L
TI
IVERSITY O F
U M B C
1966
UMBC
MO
(Feb. 25, 2002)
RE COUNT Y
UN
Memory I
CMPE 310
DRAMs DRAM: SRAMs are limited in size (up to about 128K X 8). DRAMs are available in much larger sizes, e.g., 64M X 1. DRAMs MUST be refreshed (rewritten) every 2 to 4 ms Since they store their value on an integrated capacitor that loses charge over time. This refresh is performed by a special circuit in the DRAM which refreshes the entire memory using 256 reads. Refresh also occurs on a normal read, write or during a special refresh cycle. More on this later. The large storage capacity of DRAMs make it impractical to add the required number of address pins. Instead, the address pins are multiplexed.
AR
YLAND BA L
TI
IVERSITY O F
U M B C
1966
UMBC
MO
(Feb. 25, 2002)
RE COUNT Y
UN
Systems Design & Programming DRAMs TI TMS4464 DRAM (64K X 4): G DQ1 DQ2 W RAS A6 A5 A4 VDD 1 2 3 4 5 6 7 8 9 18 17 16 15 14 13 12 11 10 VSS DQ4 CAS DQ3 A0 A1 A2 A3 A7
Memory I
CMPE 310
TMS4464
Pin(s) A0-A7 DQ0-DQ4 RAS CAS G W
Function Address Data In/Data Out Row Address Strobe Column Address Strobe Output Enable Write Enable
64K x 4 DRAM
The TMS4464 can store a total of 256K bits of data. It has 64K addressable locations which means it needs 16 address inputs, but it has only 8. The row address (A0 through A7) are placed on the address pins and strobed into a set of internal latches. The column addres (A8 through A15) is then strobed in using CAS.
M
AR
YLAND BA L
TI
IVERSITY O F
U M B C
1966
UMBC
MO
(Feb. 25, 2002)
RE COUNT Y
UN
Memory I
CMPE 310
DRAMs TI TMS4464 DRAM (64K X 4) Timing Diagram: RAS CAS Row Column Dont care Something is inconsistent here (see MUX below).
CAS also performs the function of the chip select input. A0 A8 A1 A9 A2 A10 A3 A11 Address BUS A4 A12A5 A13A6 A14 A7 A15 1A 1B 2A 2B 3A 3B 4A 4B 74157 (2-to-1MUX) S 1Y A0
M
RAS 0: latch A to Y 1: latch B to Y
1A 1B 2A 2B 3A 3B 4A 4B S 74157 (2-to-1MUX) 1Y 2Y A5 3Y A6 4Y A7
2Y A1
3Y A2
4Y
A3 Inputs to DRAM A4 10
AR
YLAND BA L
TI
IVERSITY O F
U M B C
1966
UMBC
MO
(Feb. 25, 2002)
RE COUNT Y
UN
Memory I
CMPE 310
DRAMs Larger DRAMs are available which are organized as 1M X 1, 4M X 1, 16M X 1, 64M X 1 (with 256M X 1 available soon). DRAMs are typically placed on SIMM (Single In-line Memory Modules) boards. 30-pin SIMMs come in 1M X 8, 1M X 9 (parity), 4M X 8, 4M X 9. 72-pin SIMMs come in 1/2/3/8/16M X 32 or 1M X 36 (parity). VSS VCC Addr0-11 RAS DQ0-31 CAS NC W PD1-4
10
15
20
25
30
35
40
45
50
55
60
65
70
AR
YLAND BA L
TI
IVERSITY O F
U M B C
1966
UMBC
MO
11
(Feb. 25, 2002)
RE COUNT Y
UN
Memory I
CMPE 310
DRAMs Pentiums have a 64-bit wide data bus. The 30-pin and 72-pin SIMMs are not used on these systems. Rather, 64-bit DIMMs (Dual In-line Memory Modules) are the standard. These organize the memory 64-bits wide. The board has DRAMs mounted on both sides and is 168 pins. Sizes include 2M X 64 (16M), 4M X 64 (32M), 8M X 64 (64M) and 16M X 64 (128M). The DIMM module is available in DRAM, EDO and SDRAM (and NVRAM) with and without an EPROM. The EPROM provides information abou the size and speed of the memory device for PNP applications.
AR
YLAND BA L
TI
IVERSITY O F
U M B C
1966
UMBC
MO
12
(Feb. 25, 2002)
RE COUNT Y
UN
Systems Programming
8086/88 Memory Interface II
CMPE 310
Memory Address Decoding The processor can usually address a memory space that is much larger than the memory space covered by an individual memory chip. In order to splice a memory device into the address space of the processor, decoding is necessary. For example, the 8088 issues 20-bit addresses for a total of 1MB of memory address space. However, the BIOS on a 2716 EPROM has only 2KB of memory and 11 address pins. A decoder can be used to decode the additional 9 address pins and allow the EPROM to be placed in any 2KB section of the 1MB address space.
AR
YLAND BA L
TI
IVERSITY O F
U M B C
1966
UMBC
MO
RE COUNT Y
(April 10, 2000 12:36 pm)
UN
Systems Programming Memory Address Decoding
CMPE 310
Address Bus A19 A18 A17 A16 A15 A14 A13 A12 A11 IO/M
A0 A1 A10
O0 O1 O7
Data Bus
Logic 0 when A11 through A19 are all 1.
...
...
(2K X 8) EPROM CS
2716
(Book shows OE connection for RD but chip definition does NOT have this pin).
RD of 8088/86 Or MRDC bus signal.
AR
YLAND BA L
TI
IVERSITY O F
U M B C
1966
UMBC
MO
RE COUNT Y
(April 10, 2000 12:36 pm)
UN
Systems Programming
CMPE 310
Memory Address Decoding To determine the address range that a device is mapped into: A19 - A11 A10 - A0
1111 1111 1XXX XXXX XXXX
1111 1111 1000 0000 0000 (FF800H) To 1111 1111 1111 1111 1111 (FFFFFH) This 2KB memory segment maps into the reset location of the 8086/8088 (FFFF0H). NAND gate decoders are not often used. Rather the 3-to-8 Line Decoder (74LS138) is more common.
AR
YLAND BA L
TI
IVERSITY O F
U M B C
1966
UMBC
MO
RE COUNT Y
(April 10, 2000 12:36 pm)
UN
Systems Programming
CMPE 310
Memory Address Decoding The 3-to-8 Line Decoder (74LS138)

Inputs Enable Select Output
Select Inputs
A B C
Enable
G2A G2B G1
0 1 2 3 4 5 6 7
G2A G2B G1
C B A 0 1 2 3 4 5 6 7
1 X X X X X 1 1 1 1 1 1 X 1 X X X X 1 1 1 1 1 1 X X 0 X X X 1 1 1 1 1 1 0 0 1 0 0 0 0 1 1 1 1 1 0 0 1 0 0 1 1 0 1 1 1 1 0 0 1 0 1 0 1 1 0 1 1 1 0 0 1 0 1 1 1 1 1 0 1 1 0 0 1 1 0 0 1 1 1 1 0 1 0 0 1 1 0 1 1 1 1 1 1 0 0 0 1 1 1 0 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 0 1
1 1 1 1 1 1 1 1 1 1 0
Note that all three Enables (G2A, G2B, and G1) must be active, e.g. low, low and high, respectively. Each output of the decoder can be attached to an 2764 EPROM (8K X 8).
M
AR
YLAND BA L
TI
IVERSITY O F
U M B C
1966
UMBC
Outputs 4
MO
RE COUNT Y
(April 10, 2000 12:36 pm)
UN
Systems Programming Memory Address Decoding
CMPE 310
A13 through A15 select Address Bus a 2764 A16 through A19 enable Data Bus the decoder A13 F0000-F1FFF 0 A A14 F2000-F3FFF 1 B A15 F4000-F5FFF 2 C 3 F6000-F7FFF F8000-F9FFF 4 FA000-FBFFF G2A 5 G2B 6 FC000-FDFFF A16 G1 7 FE000-FFFFF
A0
A12 O0 O7
... ...
CS CS CS CS CS CS CS CS A17 Address space RD of 8088/86 A18 F0000H-FFFFFH (Not sure about 2764 pinout, A19 text is in error with 2716) The EPROMs cover a 64KB section of memory.
YLAND BA L
TI
AR
IVERSITY O F
U M B C
1966
UMBC
74LS138
(8K X 8) EPROM
2764
MO
RE COUNT Y
(April 10, 2000 12:36 pm)
UN
Systems Programming
CMPE 310
Memory Address Decoding Yet a third possibility is a PLD (Programmable Logic Device). PLDs come in three varieties: PLA (Programmable Logic Array) PAL (Programmable Array Logic) GAL (Gated Array Logic) PLDs have been around since the mid-1970s but have only recently appeared in memory systems (PALs have replaced PROM address decoders). PALs and PLAs are fuse-programmed (like the PROM). Some are erasable (like the EPROM). A PAL example (16L8) is shown in the text and is commonly used to decode the memory address, particularly for 32-bit addresses generated by the 80386DX and above.
AR
YLAND BA L
TI
IVERSITY O F
U M B C
1966
UMBC
MO
RE COUNT Y
(April 10, 2000 12:36 pm)
UN
Systems Programming
CMPE 310
Memory Address Decoding AMD 16L8 PAL decoder. It has 10 fixed inputs (Pins 1-9, 11), two fixed outputs (Pins 12 and 19) and 6 pins that can be either (Pins 13-18). Programmed to decode address lines A19 - A13 onto 8 outputs. VCC O8 O7 Equations: O6 /O1 = A19 * A18 * A17 * A16 * /A15 * /A14 * /A13 O5 /O2 = A19 * A18 * A17 * A16 * /A15 * /A14 * A13 O4 O3 /O3 = A19 * A18 * A17 * A16 * /A15 * A14 * /A13 O2 /O4 = A19 * A18 * A17 * A16 * /A15 * A14 * A13 O1 /O5 = A19 * A18 * A17 * A16 * A15 * /A14 * /A13 I10 /O6 = A19 * A18 * A17 * A16 * A15 * /A14 * A13 /O7 = A19 * A18 * A17 * A16 * A15 * A14 * /A13 /O8 = A19 * A18 * A17 * A16 * A15 * A14 * A13 ;pins 1 2 3 4 5 6 7 8 9 10 A19 A18 A17 A16 A15 A14 A13 NC NC GND ;pins 11 12 13 14 15 16 17 18 19 20 NC O8 O7 O6 O5 O4 O3 O2 O1 VCC
I1 1 I2 2 I3 3 I4 4 I5 5 I6 6 I7 7 I8 8 I9 9 GND 10
20 19 18 17 16 15 14 13 12 11
AND/NOR device with logic expressions (outputs) with up to 16 ANDed inputs and 7 ORed product terms.
M
AR
YLAND BA L
TI
IVERSITY O F
U M B C
1966
UMBC
16L8
MO
RE COUNT Y
(April 10, 2000 12:36 pm)
UN
Systems Programming
CMPE 310
8088 and 80188 (8-bit) Memory Interface The memory systems sees the 8088 as a device with: 20 address connections (A19 to A0). 8 data bus connections (AD7 to AD0). 3 control signals, IO/M, RD, and WR. Well look at interfacing the 8088 with: 32K of EPROM (at addresses F8000H through FFFFFH). 512K of SRAM (at addresses 00000H through 7FFFFH). The EPROM interface uses a 74LS138 (3-to-8 line decoder) plus 8 2732 (4K X 8) EPROMs. The EPROM will also require the generation of a wait state. The EPROM has an access time of 450ns. The 74LS138 requires 12ns to decode. The 8088 runs at 5MHz and only allows 460ns for memory to access data. A wait state adds 200ns of additional time.
AR
YLAND BA L
TI
IVERSITY O F
U M B C
1966
UMBC
MO
RE COUNT Y
(April 10, 2000 12:36 pm)
UN
Systems Programming
CMPE 310
8088 and 80188 (8-bit) EPROM Memory Interface To wait state generator A12 A13 A14 IO/M A15 A16 A17 A18 A19 WAIT 74LS138 0 A 1 B 2 C 3 4 G2A 5 G2B 6 G1 7 1K 5V Address Bus Data Bus A0 A11 O0 O7
... ...
(4K X 8) RD OE CS CS CS CS CS CS CS CS
2732
Address space F8000H-FFFFFH
(This is the 2732 pinout as shown in the text.)
The 8088 cold starts execution at FFFF0H. JMP to F8000H occurs here.
M
AR
YLAND BA L
TI
IVERSITY O F
U M B C
1966
UMBC
MO
RE COUNT Y
(April 10, 2000 12:36 pm)
UN
Systems Programming
CMPE 310
8088 and 80188 (8-bit) RAM Memory Interface A0 A O0 Address Bus 0 A1 A8 A14 O7 A2 A9 WE A3 A10 OE A4 A11 A CS 0 A5 A12 B 1 CS A6 C 2 A 13 CS A7 3 A 1G 2G 14 CS 4 G1 5 CS 1G 2G 6 G2A CS 7 G2B WR CS 2 RD CS A0 O0 A15 A16 Data Bus 3 A14 O7 A17 WE OE A CS 0 G B A 1 CS 0 1G 2G B C 2 1 CS 3 C 2 A18 CS 4 3 G1 5 4 CS G1 4 A19 Dir 6 G2A CS G2A 5 G2B 7 IO/M G2B 6 CS 7 CS
...
...
74LS244 Buffer
74LS244 Buffer
74LS138
74LS244 Buffer
62256 (32K X 8)
74LS138
62256 (32K X 8)
AR
YLAND BA L
TI
IVERSITY O F
U M B C
1966
UMBC
10
(April 10, 2000 12:36 pm)
UN
74LS245 BD Buffer
...
...
74LS138
MO
RE COUNT Y
Systems Programming
CMPE 310
8088 and 80188 (8-bit) RAM Memory Interface The 16 62256s on the previous slide are actually SRAMs. Access times are on order of 10ns. Flash memory can also be interfaced to the 8088 (see text). However, the write time (400ms !) is too slow to be used as RAM (as shown in the text). Parity Checking: Parity checking is used to detect single bit errors in the memory. The current trend is away from parity checking. Parity checking adds 1 bit for every 8 data bits. For EVEN parity, the 9th bit is set to yield an even number of 1s in all 9 bits. For ODD parity, the 9th bit is set to make this number odd. For 72-pin SIMMs, the number of data bits is 32 + 4 = 36 (4 parity bits).
M
AR
YLAND BA L
TI
IVERSITY O F
U M B C
1966
UMBC
MO
RE COUNT Y
11
(April 10, 2000 12:36 pm)
UN
Systems Programming
CMPE 310
Parity for Memory Error Detection 74AS280 Parity Generator/Checker G H NC I EVEN ODD GND 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VCC F E D C B A Number of inputs A Outputs thru I that are HIGH EVEN ODD 0, 2, 4, 6, 8 1, 3, 5, 7, 9 H L L H
9-bit parity generator/checker This circuit generates EVEN or ODD parity for the 9-bit number placed on its inputs. Typically, for generation, the 9th input bit is set to 0. This circuit also checks EVEN or ODD parity for the 9-bit number. In this case, the 9th input bit is connected to the 9th bit of memory. For example, if the original byte has an even # of 1s (with 9th bit at GND), the parity bit is set to 1 (from the EVEN output). If the EVEN output goes high during the check, then an error occurred.
M
AR
YLAND BA L
TI
IVERSITY O F
U M B C
1966
UMBC
74AS280
MO
RE COUNT Y
12
(April 10, 2000 12:36 pm)
UN
Systems Programming
CMPE 310
Parity for Memory Error Detection Address Bus A0 O0 62256 (32K X 8) A14 O7 WE OE CS A B C 0 1 2 3 G1 4 5 G2A 6 G2B 7 74LS138 A0 Generator A EVEN B ODD C D E F G H I A EVEN B C ODD D E F G H I Checker 74LS280 Q 74LS74 Q D 74LS280
WR RD A15 A16 A17 A19 A18 IO/M
O0
A14 O7 WE OE CS 62256 (32K X 8)
NMI RESET
M
WE CE
6287 (64K X 1)
A0 DO DI A15
Data Bus
...
...
...
...
...
CLK Clear (April 10, 2000 12:36 pm)
AR
YLAND BA L
TI
IVERSITY O F
U M B C
1966
UMBC
MO
RE COUNT Y
13
UN
Systems Programming
CMPE 310
Error Detection This parity scheme can only detect a single bit error. Block-Check Character (BCC) or Checksum. Can detect multiple bit errors. This is simply the twos complement sum (the negative of the sum) of the sequence of bytes. No error occurred if adding the data values and the checksum produces a 0. For example: Given 4 hex data bytes: 10, 23, 45, 04 Compute the sum: 10 23 45 04 7C Invert and add 1 to get checksum byte: 0111 1100 + 1 1000 0011 + 1 1000 0100 = 84H Check is made by adding and checking for 00 (discard the carry): 10 23 45 04 84 1 00
This is not fool proof. If 45 changes to 44 AND 04 changes to 05, the error is missed.
M
AR
YLAND BA L
TI
IVERSITY O F
U M B C
1966
UMBC
MO
RE COUNT Y
14
(April 10, 2000 12:36 pm)
UN
Systems Programming
CMPE 310
Error Detection Cyclic Redundancy Check (CRC). Commonly used to check data transfers in hardware such as harddrives. Treats data as a stream of serial data n-bits long. The bits are treated as coefficients of a characteristic polynomial, M(X) of the form: M ( X ) = b n + b n 1 X + b n 2 X + ... + b 1 X
2 n1
+ b0 X
where b0 is the least significant bit while bn is the most significant bit. For the 16-bit data stream: 26F0H = 0010 0110 1111 0000 M( X) = 0 + 0X + 1X + 0X + 0X + 1X + 1X + 0X + 1X + 1X + 1X
2 5 9 10 1 2 3 4 5 6 7 8
+ 1X
6
11
+ 0X
12
+ 0X
13
+ 0X + 1X
14
+ 0X
15
M( X) = 1X + 1X + 1X + 1X + 1X + 1X
10
11
AR
YLAND BA L
TI
IVERSITY O F
U M B C
1966
UMBC
MO
RE COUNT Y
15
(April 10, 2000 12:36 pm)
UN
Systems Programming
CMPE 310
Error Detection Cyclic Redundancy Check (CRC) (cont.) The CRC is found by applying the following equation. M(X)X CRC = -------------------- = Q ( X ) + R ( X ) G(X)
n
Q(X) is the quotient R(X) is the remainder
G(X) is the called the generator polynomial and has special properties. A commonly used polynomial is: G(X) = X
16
+X
15
+X +1
The remainder R(X) is appended to the data block. When the CRC and R(X) is computed by the receiver, R(X) should be zero. Since G(X) is of power 16, the remainder, R(X), cannot be of order higher than 15. Therefore, no more than 2 bytes are needed independent of the data block size.
M
AR
YLAND BA L
TI
IVERSITY O F
U M B C
1966
UMBC
MO
RE COUNT Y
16
(April 10, 2000 12:36 pm)
UN
Systems Programming
CMPE 310
Error Detection Cyclic Redundancy Check (CRC)(cont.)

16 27 26 25 24 22 21 18 M(X)X X +X +X +X +X +X +X ----------------------- = ---------------------------------------------------------------------------------------------------------G(X) 16 15 2 X +X +X +1 X X 16 +X 15 2 27 26 25 24 22 21 18 +X +1 X +X +X +X +X +X +X X 27 +X 26 + 25 24 22 21 18 X +X +X +X +X 25 24 + X +X 22 21 18 X +X +X 22 21 X +X X X 18 18 + 13 11 X +X 13 11 X +X 11 9 X +X X 13 + + + +X X 17 + +X 16 X X 13 + + 13 + X 9 8 6 X +X 9 8 6 X +X +X 4 2 X +X 9 8 6 4 2 X +X +X +X +X 3 X +X
11
9 6 2 +X +X +X +X+1
17 17
Final Solution is: R( X) = X

15
+X
13
+X +X +X +X +X +X+1
...
Value appended is the reverse coefficient value 1101 1010 1100 0101 = DAC5H
M
AR
YLAND BA L
TI
IVERSITY O F
U M B C
1966
UMBC
MO
RE COUNT Y
17
(April 10, 2000 12:36 pm)
UN
Systems Programming
CMPE 310
Error Correction Parity, BCC and CRC are only mechanisms for error detection. The system is halted if an error is found in memory. Error correction is starting to show up in new systems. SDRAM has ECC (Error Correction Code). Correction will allow the system can continue operating. If two errors occur, they can be detected but not corrected. Error correction will of course cost more in terms of extra bits. Error correction is based on Hamming Codes. There is lots of theory here but our focus will be on implementation. The objective is to correct any single bit errors in an 8-bit data byte. The data bits of the byte are labeled X3, X5, X6, X7, X9, X10, X11 and X12. The parity bits are labeled P1, P2, P4 and P8. In other words, we need 4 parity bits to correct single bit errors. Note that the parity bits are at bit positions that are powers of 2.
M
AR
YLAND BA L
TI
IVERSITY O F
U M B C
1966
UMBC
MO
RE COUNT Y
18
(April 10, 2000 12:36 pm)
UN
Systems Programming
CMPE 310
Error Correction Hamming Codes (cont). P1 is generated by computing the parity of X3, X5, X7, X9, X11, X13, X15. These numbers have a 1 in bit position 1 of the subscript in binary. Given data byte: 4 3 2 1 0 0 0 0 0 11010010 P1 0 0 0 1 1 P1 is assigned even parity using P2 0 0 1 0 2 P1 uses blue bits: X3, X5, X7, X9, X11, X13, X15 12 11 10 9 7 6 5 0 0 1 1 3 P3 0 1 0 0 4 P2 is assigned even parity using 1 1 0 1 0 0 1 0 1 0 1 5 X3, X6, X7, X10, X11, X14, X15 P1 even parity is 1. 0 1 1 0 6 P3 is assigned even parity using P2 uses brown bits: 0 1 1 1 7 P4 1 0 0 0 8 X5, X6, X7, X12, X13, X14, X15 12 11 10 9 7 6 5 1 0 0 1 9 1 1 0 1 0 0 1 1 0 1 0 10 P4 is assigned even parity using P even parity is 1. 2 1 0 1 1 11 X9, X10, X11, X12, X13, X14, X15 1 1 0 0 12 P3 uses cyan bits: 1 1 0 1 13 Note that each data bit is used 1 1 0 1 0 0 1 1 1 1 0 14 P3 even parity is 0. in the parity computation of 1 1 1 1 15 at least 2 P bits. P4 uses purple bits: 1 1 0 1 0 0 1 P4 even parity is 1. Not used since we are correcting byte data.
M
3 0
3 0
AR
YLAND BA L
TI
IVERSITY O F
U M B C
1966
UMBC
MO
RE COUNT Y
19
(April 10, 2000 12:36 pm)
UN
Systems Programming
CMPE 310
Error Correction Hamming Codes (cont). Parity encoded data: 110110010011 If X10 flips from 0 -> 1, then the check gives the location of the bit error as: P 12 11 10 9 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 Flipped 7 0 0 0 0 6 0 0 0 0 5 1 1 1 1 3 0 0 0 0 P1 even parity is 0. P2 even parity is now 1. P3 even parity is 0. P4 even parity is now 1. Since these are NOT 0, there was an error.
The position of the bit flip is given by: P4P3P2P1 is 1010 or 10 decimal.
AR
YLAND BA L
TI
IVERSITY O F
U M B C
1966
UMBC
MO
RE COUNT Y
20
(April 10, 2000 12:36 pm)
UN
Systems Programming
CMPE 310
Parity for Memory Error Correction The 74LS636 corrects errors by storing 5 parity bits with each byte of data. The pinout consists of: 8 data I/O pins 5 check bit I/O pins 2 control pins 2 error outputs Single error flag (SEF) Double error flag (DEF). DEF 1 DB0 2 DB1 3 DB2 4 DB3 5 DB4 6 DB5 7 DB6 8 DB7 9 GND 10 20 19 18 17 16 15 14 13 12 11 VCC SEF S1 S0 CB0 CB1 CB2 CB3 NC CB4
See the text for an example of its use in a circuit.

M
AR
YLAND BA L
TI
IVERSITY O F
U M B C
1966
UMBC
74LS636
MO
RE COUNT Y
21
(April 10, 2000 12:36 pm)
UN
Memory III
CMPE 310
8086 - 80386SX 16-bit Memory Interface These machines differ from the 8088/80188 in several ways: The data bus is 16-bits wide. The IO/M pin is replaced with M/IO (8086/80186) and MRDC and MWTC for 80286 and 80386SX. BHE, Bus High Enable, control signal is added. Address pin A0 (or BLE, Bus Low Enable) is used differently. The 16-bit data bus presents a new problem: The microprocessor must be able to read and write data to any 16-bit location in addition to any 8-bit location. The data bus and memory are divided into banks: High bank Low bank FFFFFE FFFFFF FFFFFD FFFFFC 8 bits 8 bits D7-D0 Odd bytes D15-D8 Even bytes 8 MB 8 MB BHE selects BLE selects 000003 000002 000001 000000
M
AR
YLAND BA L
TI
IVERSITY O F
U M B C
1966
UMBC
MO
(Mar. 6, 2002)
RE COUNT Y
UN
Memory III
CMPE 310
8086 - 80386SX 16-bit Memory Interface BHE and BLE are used to select one or both: BHE 0 0 1 1 BLE 0 1 0 1 Function Both banks enabled for 16-bit transfer High bank enabled for an 8-bit transfer Low bank enabled for an 8-bit transfer No banks selected
Bank selection can be accomplished in two ways: Separate write decoders for each bank (which drive CS). A separate write signal (strobe) to each bank (which drive WE). Note that 8-bit read requests in this scheme are handled by the microprocessor (it selects the bits it wants to read from the 16-bits on the bus). There does not seem to be a big difference between these methods although the book claims that there is. Note in either method that A0 does not connect to memory and bus wire A1 connects to memory pin A0, A2 to A1, etc.
M
AR
YLAND BA L
TI
IVERSITY O F
U M B C
1966
UMBC
MO
(Mar. 6, 2002)
RE COUNT Y
UN
Memory III
CMPE 310
80386SX 16-bit Memory Interface (Separate Decoders) A0 O0 A1 to A16 Address Bus D8 to D15 A15 O7 MWTC WE A17 OE A CS A18 0 3 62512 B 1 CS A19 C 2 CS(64K X 8) 3 CS BHE 4 G1 5 CS A20 6 G2A CS A A21 0 G2B 7 CS B 1 A22 CS 2 A0 O0 C 3 D0 to D7 4 A 15 O7 A23 G1 5 WE G2A 6 OE G2B 7 A CS 0 B 62512 1 CS C 2 MRDC CS (64K X 8) 3 M/IO CS G1 4 5 CS BLE G2A 6 CS G2B 7 CS CS ... ... 74LS138 74LS138
M
AR
YLAND BA L
TI
IVERSITY O F
U M B C
1966
UMBC
(Mar. 6, 2002)
UN
Data Bus
74LS138
Separate Decoders
80386SX
...
...
MO
RE COUNT Y
Memory III
CMPE 310
Memory Interfaces See text for Separate Write Strobe scheme plus some examples of the integration of EPROM and SRAM in a complete system. It is just an application of what weve been covering. 80386DX and 80486 have 32-bit data buses and therefore 4 banks of memory. 32-bit, 16-bit and 8-bit transfers are accomplished by different combinations of the bank selection signals BE3, BE2, BE1, BE0. The Address bits A0 and A1 are used within the microprocessor to generate these signals. They are dont cares in the decoding of the 32-bit address outside the chip (using a PLD such as the PAL 16L8). The high clock rates of these processors usually require wait states for memory access. We will come back to this later.
AR
YLAND BA L
TI
IVERSITY O F
U M B C
1966
UMBC
MO
(Mar. 6, 2002)
RE COUNT Y
UN
Memory III
CMPE 310
Pentium Memory Interface The Pentium, Pentium Pro, Pentium II and III contain a 64-bit data bus. Therefore, 8 decoders or 8 write strobes are needed as well as 8 memory banks. The write strobes are obtained by combining the bank enable signals (BEx) with the MWTC signal. MWTC is generated by combining the M/IO and W/R signals. BE7 WR7 BE6 WR6 BE5 WR5 BE4 W/R WR4 MWTC BE3 M/IO WR3 BE2 BE1 BE0
AR
YLAND BA L
TI
WR2 WR1 WR0 5 (Mar. 6, 2002)
IVERSITY O F
U M B C
1966
UMBC
MO
RE COUNT Y
UN
Systems Design & Programming Pentium Memory Interface WR0
Memory III
CMPE 310
WR1
WR2
D15-D23
WR3
A29 I1 A30 I2 O1 A31 I3 O2 I4 O3 I5 O4 I6 O5 I7 O6 I8 O7 I9 O8 I10 16L8 A19 I1 A20 A21 I2 A22 I3 I4 A23 I5 A24 A25 I6 A26 I7 A27 I8 A28 I9 I10 O1 O2 O3 O4 O5 O6 O7 O8
D0-D7
27512 (64K X 8)
A0 O0 A15 O7 WE CE OE ...
A0 O0 A15 O7 ... 27512 WE CE OE
A0 O0 A15 O7 ... 27512 WE CE OE
A0 O0 A15 O7 ... WE CE OE 27512
D32-D39
D40-D47
27512
27512
27512
D48-D55
WE CE OE WR4
WE CE OE WR5
WE CE OE WR6
WE CE OE WR7
MRDC
M
AR
YLAND BA L
TI
IVERSITY O F
U M B C
1966
UMBC
(Mar. 6, 2002)
UN
27512
D56-D63
16L8
A0 O0 A15 O7 ...
A0 O0 A15 O7 ...
A0 O0 A15 O7 ...
A0 O0 A15 O7 ...
D24-D31
A3-A18
D8-D15
...
...
...
... ...
...
...
...
MO
RE COUNT Y
Memory III
CMPE 310
Pentium Memory Interface In order to map previous memory into addr. space FFF80000H-FFFFFFFFH A29 ;pins 1 2 3 4 5 6 7 8 9 10 A30 I1 O1 I2 A31 I3 O2 A29 A30 A31 NC NC NC NC NC NC GND I4 O3 ;pins 11 12 13 14 15 16 17 18 19 20 I5 O4 U2 CE NC NC NC NC NC NC NC VCC I6 O5 I7 O6 Equations: I8 O7 I9 O8 /CE = /U2 * A29 * A30 * A31 I10 A19 I1 A20 A21 I2 A22 I3 I4 A23 I5 A24 I6 A25 I7 A26 I8 A27 I9 A28 I10 16L8 O1 O2 O3 O4 O5 O6 O7 O8 ;pins 1 2 3 4 5 6 7 8 9 10 A19 A20 A21 A22 A23 A24 A25 A26 A27 GND ;pins 11 12 13 14 15 16 17 18 19 20 A28 U2 NC NC NC NC NC NC NC VCC Equations: /U2 = A19 * A20 * A21 * A22 * A23 * A24 * A25 * A26 * A27 * A28
Use a 16L8 to do the WR0 - WR7 decoding using MWTC and BE0 - BE7. See the text -- Figure 10-35.
M
AR
YLAND BA L
TI
IVERSITY O F
U M B C
1966
UMBC
16L8
MO
(Mar. 6, 2002)
RE COUNT Y
UN
Memory III
CMPE 310
Memory Architecture In order to build an N-word memory where each word is M bits wide (typically 1, 4 or 8 bits), a straightforward approach is to stack memory: S0 S1 S2 N words Word 0 Word 1 Word 2 A word is selected by setting exactly one of the select bits, Sx, high. Storage cell
SN-2 SN-1
Word N-2 Word N-1 Input-Output (M bits)
This approach works well for small memories but has problems for large memories. For example, to build a 1Mword (where word = 8 bits) memory, requires 1M select lines, provided by some off-chip device.
This approach is not practical. What can we do?

M
AR
YLAND BA L
TI
IVERSITY O F
U M B C
1966
UMBC
MO
(Mar. 6, 2002)
RE COUNT Y
UN
Memory III
CMPE 310
Binary encoded address
Decoder
Memory Architecture Add a decoder to solve the package problem: S0 Word 0 S1 Word 1 A0 S2 Word 2 A1 A2 AK-1
Storage cell
SN-2 SN-1 K = log2N
Word N-2 Word N-1
This reduces the number of external address pins from 1M to 20.
one-hot Input-Output (M bits) This does not address the memory aspect ratio problem: The memory is 128,000 time higher than wide (220/23) ! Besides the bizarre shape factor, the design is extremely slow since the vertical wires are VERY long (delay is at least linear to length).
M
AR
YLAND BA L
TI
IVERSITY O F
U M B C
1966
UMBC
MO
(Mar. 6, 2002)
RE COUNT Y
UN
Memory III
CMPE 310
AL-1
Row Decoder
Memory Architecture The vertical and horizontal dimensions are usually very similar, for an aspect ratio of unity. Multiple words are stored in each row and selected simultaneously: Bit line S0 Row address = Storage cell AK to AL-1 S1 AK S2 AK+1 AK+2 Word line
SN-2 SN-1 Column address = A0 to AK-1 A0 AK-1 A column decoder is added to select the desired word from a row.
M
Column decoder Input-Output (M bits) 10
Sense amps and drivers not shown
AR
YLAND BA L
TI
IVERSITY O F
U M B C
1966
UMBC
MO
(Mar. 6, 2002)
RE COUNT Y
UN
Memory III
CMPE 310
Memory Architecture This strategy works well for memories up to 64 Kbits to 256 Kbits. Larger memories start to suffer excess delay along bit and word lines. A third dimension is added to the address space to solve this problem: Block 0 Row Address Block i Block P-1
Column Address Block Address Global Data bus Address: [Row][Block][Col] Global amplier/driver I/O 11 (Mar. 6, 2002) Block selector
AR
YLAND BA L
TI
IVERSITY O F
U M B C
1966
UMBC
MO
RE COUNT Y
UN
Memory III
CMPE 310
Dynamic RAM DRAM requires refreshing every 2 to 4 ms. Refreshing occurs automatically during a read or write. Internal circuitry takes care of refreshing cells that are not accessed over this interval. This special refresh occurs transparently while other memory components operate and is called transparent refresh or cycle stealing. A RAS-only cycle strobes a row address into the DRAM, obtained by 7- or 8bit binary counter. The capacitors are recharged for the selected row by reading the bits out internally and then writing them back. For a 256K X 1 DRAM with 256 rows, a refresh must occur every 15.6us (4ms/256). For the 8086, a read or write occurs every 800ns. This allows 19 memory reads/writes per refresh or 5% of the time.
M
AR
YLAND BA L
TI
IVERSITY O F
U M B C
1966
UMBC
MO
12
(Mar. 6, 2002)
RE COUNT Y
UN
Systems Design & Programming Dynamic RAM A0 A1 A2 A3 A4 A5 A6 A7 A8 RAS WE
Memory III
CMPE 310
Row Latches
256K X 1 DRAM A10-A17 Block 3 Block 2 Block 1 255 254 64K array 64K array 64K array (256 X 256) (256 X 256) (256 X 256) 1 0 8 256-to-1 MUX 256-to-1 MUX 256-to-1 MUX
Block 0 64K array (256 X 256) 256-to-1 MUX
Column Latches
Decoder
A0-A7 MUX S1 S0
DIN DOUT
A9(A0 from input pin on RAS) A8
Dir
CAS
These signals provide the block address.

M
AR
YLAND BA L
TI
IVERSITY O F
U M B C
1966
UMBC
MO
13
(Mar. 6, 2002)
RE COUNT Y
UN
Memory III
CMPE 310
EDO and SDRAM Memory Extended Data Output memory: Any memory access in an EDO memory (including a refresh) stores the 256 bits in a set of latches. Any subsequent access to bytes in this set are immediately available (without the decode time and therefore wait states). This works well because of the principle of spatial locality, and improves system performance by 15 to 25 % ! Synchronous Dynamic RAM: Access times are 10ns (for use with 66MHz bus) and 8ns (for use with 100MHz bus). Standard DRAM access times are 60ns. However, these access times only apply to the 2nd, 3rd and 4th 64-bit reads -- the rst takes the same time as a standard DRAM.
AR
YLAND BA L
TI
IVERSITY O F
U M B C
1966
UMBC
MO
14
(Mar. 6, 2002)
RE COUNT Y
UN
Memory III
CMPE 310
EDO and SDRAM Memory Synchronous Dynamic RAM: However, this improves performance again, particularly for reads into cache block sizes of 256 bits. For example, 256 bit transfer takes three bus cycles for the rst read and three for the next three 64-bit words, for a total of 7 bus cycles. This contrasts with the 3*4 or 12 bus cycles for DRAM or EDO. Measurements show about a 10% increase in performance. DRAM Controllers: A DRAM controller is usually responsible for address multiplexing and generation of the DRAM control signals. These devices tend to get very complex. We will focus on a simpler device, the Intel 82C08, which can control two banks of 256K X 16 DRAM memories for a total of 1 MB.
M
AR
YLAND BA L
TI
IVERSITY O F
U M B C
1966
UMBC
MO
15
(Mar. 6, 2002)
RE COUNT Y
UN
Memory III
CMPE 310
DRAM Controllers: Intel 82C08: Microprocessor bits A1 through A18 (18 bits) drive the 9 Address Low (AL) and 9 Address High (AH) bits of the 82C08. 9 of each of these are strobed onto the address wires A0 through A8 to the memories. Either RAS0/CAS0 or RAS1/CAS1 are strobed depending on the address. This drives a 16-bit word onto the High and Low data buses (if WE is low) or writes an 8 or 16 bit word into the memory otherwise. WE (from the 82C08), BHE and A0 are used to determine if a write is to be performed and which byte(s) (low or high or both) is to be written. Address bit A20 through A23 along with M/IO enable these memories to map onto 1 MByte range (000000H-0FFFFFH).
AR
YLAND BA L
TI
IVERSITY O F
U M B C
1966
UMBC
MO
16
(Mar. 6, 2002)
RE COUNT Y
UN
Systems Design & Programming DRAM Controllers A1 A18 AL0 82C08 AL8 AH0 ... ... A0 A8 R1
Memory III
CMPE 310
(256K X 8) A0 O0 A8 O7 ... A0 O0 A8 O7 ... WE RAS CAS ... ...
AH8 S0 RD RAS0 WR S1 CAS0 RESET RAS1 CLK PCTL CAS1 PE AA/XA A19 BS WE RFRQ PD1 BHE A0 A20 A21 A22 A23 M/IO
M
41256A8
R2
WE RAS CAS
I1 I2 I3 I4 I5 I6 I7 I8 I9 I10
High Data Bus
O1 O2 O3 O4 O5 O6 O7 O8
41256A8
WE RAS CAS WAIT 17
WE RAS CAS
AR
YLAND BA L
TI
IVERSITY O F
U M B C
1966
UMBC
(Mar. 6, 2002)
UN
41256A8
Low Data Bus
A0 O0 A8 O7 ...
A0 O0 A8 O7 ...
16L8
41256A8
...
...
...
MO
RE COUNT Y
Systems Design & Programming DRAM Controllers: 16L8 Programming: WE A0 A20 A21 A22 A23 M/IO I1 I2 I3 I4 I5 I6 I7 I8 I9 I10 O1 O2 O3 O4 O5 O6 O7 O8
Memory III
CMPE 310
16L8
;pins 1 2 3 4 5 6 7 8 9 10 PE WE BHE A0 A20 A21 A22 A23 NC NC GND HWR ;pins 11 12 13 14 15 16 17 18 19 20 LWR MIO CE NC NC NC NC LWR HWR PE VCC Equations: /LWR = /A0 * /WE /HWR = /BHE * /WE /PE = /A20 * /A21 * /A22 * /A23 * MIO
AR
YLAND BA L
TI
IVERSITY O F
U M B C
1966
UMBC
MO
18
(Mar. 6, 2002)
RE COUNT Y
UN
Pin Diagram of 8085

X1 X2 RESET OUT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 SOD SID TRAP RST 7.5 RST 6.5 RST 5.5 INTR _____ INTA AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 VSS 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 Vcc HOLD HLDA CLK ( OUT) READY
___ 1
DMA
_________________
Serial i/p, o/p signals
RESET IN
__
IO / M S RD
___
8085 A
WR ALE S0 A15 A14 A13 A12 A11 A10 A9 A8
M. Krishna Kumar
MAM/M1/LU4/V1/2004
Signal Groups of 8085

+5V XTAL X1 X2 5 4 Vcc Vss A15 A8 AD7 AD0 GND
SID SOD TRAP RESET 7.5 RESET 6.5 RESET 5.5 INTR READY HOLD HLDA
______
High order Address bus Multiplexed address / data bus
ALE S1 S0
____ ____
___
______________
RESET IN
IO / M
RD
INTA RESET OUT

M. Krishna Kumar
WR CLK OUT
2
MAM/M1/LU4/V1/2004
INTA INT R
RES 5.5
RES 6.5
RES 7.5
TRAP
SID
SIO
INTERRUPT CONTROL
SERIAL I / O CONTROL 8 BIT INTERNAL DATA BUS
ACCUMULATOR (8)
TEMP REG(8)
INSTRUCTION REGISTER ( 8 ) R E G. S INSTRUCTIO N DECODER AND MACHINE ENCODING E L W
MULTIPLXER ( 8 ) C ) REG ( 8 REG ( 8 REG ( 8 ) ( 16 )
FLAG ( 5) ARITHEMETIC LOGIC UNIT ( ALU) +5V GND X1 X2 CLK GEN CONTRO L READY R WR AL D E TIMING AND CONTROL (8) FLIP FLOPS
TEMP . REG. B REG (8)
D REG ( 8 E ) ) H REG ( 8 L ) STACK POINTER
PROGRAM COUNTER ( 16 E ) INCREAMENT / DECREAMENT C ADDRESS LATCH ( 16 ) T
STATUS
DMA
ADDRESS BUFFER ( 8 )
DATA / ADDRESS BUFFER ( 8 )
CLK OUT
RESET S0 S1 IO / M HOLD HLDA RESET IN OUT
A 15 A8 ADDRESS BUS
AD7 AD0 ADDRESS / BUFFER BUS
M. Krishna Kumar
MAM/M1/LU4/V1/2004
Flag Registers
D7 S D6 Z D5 D4 AC D3 D2 P D1 D0 CY

INDIVIDUAL B, C, D, E, H, L COMBININATON B & C, D & E, H & L
M. Krishna Kumar
MAM/M1/LU4/V1/2004
AH BH CH GENERAL REGISTERS DH SP BP SI DI
AL BL CL DL ADDRESS BUS ( 20 ) BITS DATA BUS ( 16 ) BITS ES CS SS DS ALU DATA BUS 16 BITS BUS IP 8 0 8
TEMPORARY REGISTERS
CONTRO 6 L LOGIC B U S EU CONTROL SYSTEM Q BUS 8 BIT
ALU
INSTRUCTION QUEUE 1 2 3 4 5 6
FLAGS EXECUTION UNIT ( EU )
BUS INTERFACE UNIT ( BIU)
Fig:
Pin Diagram of 8086

GND AD14 AD13 AD12 AD11 AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 NMI INTR CLK GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 VCC AD15 A16 / S3 A17 / S4 A19/S6
____
A18 / S5
_____
8086 CPU
BHE / S7
_____ _____
MN/MX
___
RD
___
RQ _____
/ GT0 ( HOLD)
____
( HLDA) RQ / GT 1 ___ _______

LOCK (WR)
___
____
___
S 1 ___ S0
______
(DT / R) _____
(DEN)
________
S2
(M / IO )
QS1 (INTA) TEST READY RESET
QS0 (ALE)
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VCC
GND A0 - A15, A16 / S3 A19/S6
INTR
_____
INTA INTERRUPT
______
ADDRESS / DATA BUS D0 - D15 8086 MPU ALE ___ BHE / S7

__
TEST NMI RESET
INTERFACE
HOLD HLDA VCC

____
DMA INTERFACE
MEMORY I/O CONTROLS
M / IO
____
__
DT / R
RD
_____
_____
WR
MN / MX
MODE SELECT
DEN READY
CLK

The Microprocessor 8086 is a 16-bit CPU available in different clock rates and packaged in a 40 pin CERDIP or plastic package. The 8086 operates in single processor or multiprocessor configuration to achieve high performance. The pins serve a particular function in minimum mode (single processor mode ) and other function in maximum mode configuration (multiprocessor mode ). The 8086 signals can be categorised in three groups. The first are the signal having common functions in minimum as well as maximum mode.
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The second are the signals which have special functions for minimum mode and third are the signals having special functions for maximum mode. The following signal descriptions are common for both modes. AD15-AD0 : These are the time multiplexed memory I/O address and data lines. Address remains on the lines during T1 state, while the data is available on the data bus during T2, T3, Tw and T4. These lines are active high and float to a tristate during interrupt acknowledge and local bus hold acknowledge cycles.
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A19/S6,A18/S5,A17/S4,A16/S3 : These are the time multiplexed address and status lines. During T1 these are the most significant address lines for memory operations. During I/O operations, these lines are low. During memory or I/O operations, status information is available on those lines for T2,T3,Tw and T4. The status of the interrupt enable flag bit is updated at the beginning of each clock cycle.
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The S4 and S3 combinedly indicate which segment register is presently being used for memory accesses as in below fig. These lines float to tri-state off during the local bus hold acknowledge. The status line S6 is always low . The address bit are separated from the status bit using latches controlled by the ALE signal.
S4 0 0 1 1 S3 0 1 0 1 Indication Alternate Data Stack Code or none Data
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BHE/S7 : The bus high enable is used to indicate the transfer of data over the higher order ( D15-D8 ) data bus as shown in table. It goes low for the data transfer over D15-D8 and is used to derive chip selects of odd address memory bank or peripherals. BHE is low during T1 for read, write and interrupt acknowledge cycles, whenever a byte is to be transferred on higher byte of data bus. The status information is available during T2, T3 and T4. The signal is active low and tristated during hold. It is low during T1 for the first pulse of the interrupt acknowledge cycle.
BHE 0 0 1 1 A0 0 1 0 1 Indication Whole word address Upper byte bytefrom fromor orto toodd even address Lower byte from or to even address None
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RD Read : This signal on low indicates the peripheral that the processor is performing s memory or I/O read operation. RD is active low and shows the state for T2, T3, Tw of any read cycle. The signal remains tristated during the hold acknowledge. READY : This is the acknowledgement from the slow device or memory that they have completed the data transfer. The signal made available by the devices is synchronized by the 8284A clock generator to provide ready input to the 8086. the signal is active high.
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INTR-Interrupt Request : This is a triggered input. This is sampled during the last clock cycles of each instruction to determine the availability of the request. If any interrupt request is pending, the processor enters the interrupt acknowledge cycle. This can be internally masked by resulting the interrupt enable flag. This signal is active high and internally synchronized. TEST : This input is examined by a WAIT instruction. If the TEST pin goes low, execution will continue, else the processor remains in an idle state. The input is synchronized internally during each clock cycle on leading edge of clock.
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NMI- Nonmaskable interrupt : This is an edge triggered input which causes a Type 2 interrupt. The NMI is not maskable internally by software. A transition from low to high initiates the interrupt response at the end of the current instruction. This input is internally synchronized. RESET : This input causes the processor to terminate the current activity and start execution from FFF0H. The signal is active high and must be active for at least four clock cycles. It restarts execution when the RESET returns low. RESET is also internally synchronized. Vcc +5V power supply for the operation of the internal circuit. GND ground for internal circuit.
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CLK- Clock Input : The clock input provides the basic timing for processor operation and bus control activity. Its an asymmetric square wave with 33% duty cycle. MN/MX : The logic level at this pin decides whether the processor is to operate in either minimum or maximum mode. The following pin functions are for the minimum mode operation of 8086. M/IO Memory/IO : This is a status line logically equivalent to S2 in maximum mode. When it is low, it indicates the CPU is having an I/O operation, and when it is high, it indicates that the CPU is having a memory operation. This line becomes active high in the previous T4 and remains active till final T4 of the current cycle. It is tristated during local bus hold acknowledge .

INTA Interrupt Acknowledge : This signal is used as a read strobe for interrupt acknowledge cycles. i.e. when it goes low, the processor has accepted the interrupt. ALE Address Latch Enable : This output signal indicates the availability of the valid address on the address/data lines, and is connected to latch enable input of latches. This signal is active high and is never tristated. DT/R Data Transmit/Receive: This output is used to decide the direction of data flow through the transreceivers (bidirectional buffers). When the processor sends out data, this signal is high and when the processor is receiving data, this signal is low.
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DEN Data Enable : This signal indicates the availability of valid data over the address/data lines. It is used to enable the transreceivers ( bidirectional buffers ) to separate the data from the multiplexed address/data signal. It is active from the middle of T2 until the middle of T4. This is tristated during hold acknowledge cycle. HOLD, HLDA- Acknowledge : When the HOLD line goes high, it indicates to the processor that another master is requesting the bus access. The processor, after receiving the HOLD request, issues the hold acknowledge signal on HLDA pin, in the middle of the next clock cycle after completing the current bus cycle.
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At the same time, the processor floats the local bus and control lines. When the processor detects the HOLD line low, it lowers the HLDA signal. HOLD is an asynchronous input, and is should be externally synchronized. If the DMA request is made while the CPU is performing a memory or I/O cycle, it will release the local bus during T4 provided : The request occurs on or before T2 state of the current cycle. The current cycle is not operating over the lower byte of a word. The current cycle is not the first acknowledge of an interrupt acknowledge sequence.
1. 2. 3.
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4. A Lock instruction is not being executed. The following pin function are applicable for maximum mode operation of 8086. S2, S1, S0 Status Lines : These are the status lines which reflect the type of operation, being carried out by the processor. These become activity during T4 of the previous cycle and active during T1 and T2 of the current bus cycles.
S2 0 0 0 0 1 1 1 1
M. Krishna Kumar
S1 0 0 1 1 0 0 1 1
S0 0 1 0 1 0 1 0 1
Indication Interrupt Acknowledge Read I/O port Write I/O port Halt Code Access Read memory Write memory Passive
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LOCK : This output pin indicates that other system bus master will be prevented from gaining the system bus, while the LOCK signal is low. The LOCK signal is activated by the LOCK prefix instruction and remains active until the completion of the next instruction. When the CPU is executing a critical instruction which requires the system bus, the LOCK prefix instruction ensures that other processors connected in the system will not gain the control of the bus. The 8086, while executing the prefixed instruction, asserts the bus lock signal output, which may be connected to an external bus controller.

QS1, QS0 Queue Status: These lines give information about the status of the code-prefetch queue. These are active during the CLK cycle after while the queue operation is performed. This modification in a simple fetch and execute architecture of a conventional microprocessor offers an added advantage of pipelined processing of the instructions. The 8086 architecture has 6-byte instruction prefetch queue. Thus even the largest (6-bytes) instruction can be prefetched from the memory and stored in the prefetch. This results in a faster execution of the instructions. In 8085 an instruction is fetched, decoded and executed and only after the execution of this instruction, the next one is fetched.

By prefetching the instruction, there is a considerable speeding up in instruction execution in 8086. This is known as instruction pipelining. At the starting the CS:IP is loaded with the required address from which the execution is to be started. Initially, the queue will be empty an the microprocessor starts a fetch operation to bring one byte (the first byte) of instruction code, if the CS:IP address is odd or two bytes at a time, if the CS:IP address is even. The first byte is a complete opcode in case of some instruction (one byte opcode instruction) and is a part of opcode, in case of some instructions ( two byte opcode instructions), the remaining part of code lie in second byte.

But the first byte of an instruction is an opcode. When the first byte from the queue goes for decoding and interpretation, one byte in the queue becomes empty and subsequently the queue is updated. The microprocessor does not perform the next fetch operation till at least two bytes of instruction queue are emptied. The instruction execution cycle is never broken for fetch operation. After decoding the first byte, the decoding circuit decides whether the instruction is of single opcode byte or double opcode byte. If it is single opcode byte, the next bytes are treated as data bytes depending upon the decoded instruction length, otherwise, the next byte in the queue is treated as the second byte of the instruction opcode.

The second byte is then decoded in continuation with the first byte to decide the instruction length and the number of subsequent bytes to be treated as instruction data. The queue is updated after every byte is read from the queue but the fetch cycle is initiated by BIU only if at least two bytes of the queue are empty and the EU may be concurrently executing the fetched instructions. The next byte after the instruction is completed is again the first opcode byte of the next instruction. A similar procedure is repeated till the complete execution of the program.
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The fetch operation of the next instruction is overlapped with the execution of the current instruction. As in the architecture, there are two separate units, namely Execution unit and Bus interface unit. While the execution unit is busy in executing an instruction, after it is completely decoded, the bus interface unit may be fetching the bytes of the next instruction from memory, depending upon the queue status.
QS1
0 0 1 1
QS0
0 1 0 1
Indication No operation First byte of the opcode from the queue Empty queue Subsequent byte from the queue
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RQ/GT0, RQ/GT1 Request/Grant : These pins are used by the other local bus master in maximum mode, to force the processor to release the local bus at the end of the processor current bus cycle. Each of the pin is bidirectional with RQ/GT0 having higher priority than RQ/GT1. RQ/GT pins have internal pull-up resistors and may be left unconnected. Request/Grant sequence is as follows: A pulse of one clock wide from another bus master requests the bus access to 8086.
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1.
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2. During T4(current) or T1(next) clock cycle, a pulse one clock wide from 8086 to the requesting master, indicates that the 8086 has allowed the local bus to float and that it will enter the hold acknowledge state at next cycle. The CPU bus interface unit is likely to be disconnected from the local bus of the system. A one clock wide pulse from the another master indicates to the 8086 that the hold request is about to end and the 8086 may regain control of the local bus at the next clock cycle. Thus each master to master exchange of the local bus is a sequence of 3 pulses. There must be at least one dead clock cycle after each bus exchange.
3.
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The request and grant pulses are active low. For the bus request those are received while 8086 is performing memory or I/O cycle, the granting of the bus is governed by the rules as in case of HOLD and HLDA in minimum mode.
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General Bus Operation

The 8086 has a combined address and data bus commonly referred as a time multiplexed address and data bus. The main reason behind multiplexing address and data over the same pins is the maximum utilisation of processor pins and it facilitates the use of 40 pin standard DIP package. The bus can be demultiplexed using a few latches and transreceivers, when ever required. Basically, all the processor bus cycles consist of at least four clock cycles. These are referred to as T1, T2, T3, T4. The address is transmitted by the processor during T1. It is present on the bus only for one cycle.
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During T2, i.e. the next cycle, the bus is tristated for changing the direction of bus for the following data read cycle. The data transfer takes place during T3, T4. In case, an address device is slow NOT READY status the wait status Tw are inserted between T3 and T4. These clock states during wait period are called idle states (Ti), wait states (Tw) or inactive states. The processor used these cycles for internal housekeeping. The address latch enable (ALE) signal is emitted during T1 by the processor (minimum mode) or the bus controller (maximum mode) depending upon the status of the MN/MX input.
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The negative edge of this ALE pulse is used to separate the address and the data or status information. In maximum mode, the status lines S0, S1 and S2 are used to indicate the type of operation. Status bits S3 to S7 are multiplexed with higher order address bits and the BHE signal. Address is valid during T1 while status bits S3 to S7 are valid during T2 through T4.
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T1 CLK ALE S2 S0 Add/stat Add/data A0-A15 RD/INTA READY DT/R DEN WR A19-A16 BHE
Memory read cycle T2 T3 Tw
T4
T1
Memory write cycle T2 T3 Tw
T4
S3-S7 Bus reserve for Data In
A19-A16 BHE D15-D0
S3-S7
Data Out D15 D0 A0-A15 Ready
D15-D0
Ready Wait Wait
Memory access time General Bus Operation Cycle in Maximum Mode

8086 16-BIT HMOS MICROPROCESSOR 8086 8086-2 8086-1

Y
Direct Addressing Capability 1 MByte of Memory Architecture Designed for Powerful Assembly Language and Efficient High Level Languages 14 Word by 16-Bit Register Set with Symmetrical Operations 24 Operand Addressing Modes Bit Byte Word and Block Operations 8 and 16-Bit Signed and Unsigned Arithmetic in Binary or Decimal Including Multiply and Divide
Range of Clock Rates 5 MHz for 8086 8 MHz for 8086-2 10 MHz for 8086-1 MULTIBUS System Compatible Interface Available in EXPRESS Standard Temperature Range Extended Temperature Range Available in 40-Lead Cerdip and Plastic Package
(See Packaging Spec Order 231369)
Y Y Y
The Intel 8086 high performance 16-bit CPU is available in three clock rates 5 8 and 10 MHz The CPU is implemented in N-Channel depletion load silicon gate technology (HMOS-III) and packaged in a 40-pin CERDIP or plastic package The 8086 operates in both single processor and multiple processor configurations to achieve high performance levels
231455 2
40 Lead Figure 2 8086 Pin Configuration
Figure 1 8086 CPU Block Diagram
231455 1
September 1990
Order Number 231455-005
8086
Table 1 Pin Description
The following pin function descriptions are for 8086 systems in either minimum or maximum mode The Local Bus in these descriptions is the direct multiplexed bus interface connection to the 8086 (without regard to additional bus buffers)
Symbol AD15 AD0 Pin No 216 39 Type I O Name and Function ADDRESS DATA BUS These lines constitute the time multiplexed memory IO address (T1) and data (T2 T3 TW T4) bus A0 is analogous to BHE for the lower byte of the data bus pins D7 D0 It is LOW during T1 when a byte is to be transferred on the lower portion of the bus in memory or I O operations Eight-bit oriented devices tied to the lower half would normally use A0 to condition chip select functions (See BHE ) These lines are active HIGH and float to 3-state OFF during interrupt acknowledge and local bus hold acknowledge ADDRESS STATUS During T1 these are the four most significant address lines for memory operations During I O operations these lines are LOW During memory and I O operations status information is available on these lines during T2 T3 TW T4 The status of the interrupt enable FLAG bit (S5) is updated at the beginning of each CLK cycle A17 S4 and A16 S3 are encoded as shown This information indicates which relocation register is presently being used for data accessing These lines float to 3-state OFF during local bus hold acknowledge A17 S4 0 (LOW) 0 1 (HIGH) 1 S6 is 0 (LOW) BHE S7 34 O A16 S3 0 1 0 1 Characteristics Alternate Data Stack Code or None Data
A19 A18 A17 A16
S6 S5 S4 S3
3538
BUS HIGH ENABLE STATUS During T1 the bus high enable signal (BHE) should be used to enable data onto the most significant half of the data bus pins D15 D8 Eight-bit oriented devices tied to the upper half of the bus would normally use BHE to condition chip select functions BHE is LOW during T1 for read write and interrupt acknowledge cycles when a byte is to be transferred on the high portion of the bus The S7 status information is available during T2 T3 and T4 The signal is active LOW and floats to 3-state OFF in hold It is LOW during T1 for the first interrupt acknowledge cycle BHE 0 0 1 1 A0 0 1 0 1 Characteristics Whole word Upper byte from to odd address Lower byte from to even address None
RD
32
READ Read strobe indicates that the processor is performing a memory or I O read cycle depending on the state of the S2 pin This signal is used to read devices which reside on the 8086 local bus RD is active LOW during T2 T3 and TW of any read cycle and is guaranteed to remain HIGH in T2 until the 8086 local bus has floated This signal floats to 3-state OFF in hold acknowledge
8086
Table 1 Pin Description (Continued) Symbol READY Pin No 22 Type I Name and Function READY is the acknowledgement from the addressed memory or I O device that it will complete the data transfer The READY signal from memory IO is synchronized by the 8284A Clock Generator to form READY This signal is active HIGH The 8086 READY input is not synchronized Correct operation is not guaranteed if the setup and hold times are not met INTERRUPT REQUEST is a level triggered input which is sampled during the last clock cycle of each instruction to determine if the processor should enter into an interrupt acknowledge operation A subroutine is vectored to via an interrupt vector lookup table located in system memory It can be internally masked by software resetting the interrupt enable bit INTR is internally synchronized This signal is active HIGH TEST input is examined by the Wait instruction If the TEST input is LOW execution continues otherwise the processor waits in an Idle state This input is synchronized internally during each clock cycle on the leading edge of CLK NON-MASKABLE INTERRUPT an edge triggered input which causes a type 2 interrupt A subroutine is vectored to via an interrupt vector lookup table located in system memory NMI is not maskable internally by software A transition from LOW to HIGH initiates the interrupt at the end of the current instruction This input is internally synchronized RESET causes the processor to immediately terminate its present activity The signal must be active HIGH for at least four clock cycles It restarts execution as described in the Instruction Set description when RESET returns LOW RESET is internally synchronized CLOCK provides the basic timing for the processor and bus controller It is asymmetric with a 33% duty cycle to provide optimized internal timing VCC a 5V power supply pin GROUND I MINIMUM MAXIMUM indicates what mode the processor is to operate in The two modes are discussed in the following sections
INTR
18
TEST
23
NMI
17
RESET
21
CLK
19
VCC GND MN MX
40 1 20 33
The following pin function descriptions are for the 8086 8288 system in maximum mode (i e MN MX e VSS) Only the pin functions which are unique to maximum mode are described all other pin functions are as described above
S2 S1 S0 2628 O STATUS active during T4 T1 and T2 and is returned to the passive state (1 1 1) during T3 or during TW when READY is HIGH This status is used by the 8288 Bus Controller to generate all memory and I O access control signals Any change by S2 S1 or S0 during T4 is used to indicate the beginning of a bus cycle and the return to the passive state in T3 or TW is used to indicate the end of a bus cycle
8086
Table 1 Pin Description (Continued) Symbol S2 S1 S0 (Continued) Pin No 2628 Type O Name and Function These signals float to 3-state OFF in hold acknowledge These status lines are encoded as shown S2 0 (LOW) 0 0 0 1 (HIGH) 1 1 1 RQ GT0 RQ GT1 30 31 I O S1 0 0 1 1 0 0 1 1 S0 0 1 0 1 0 1 0 1 Characteristics Interrupt Acknowledge Read I O Port Write I O Port Halt Code Access Read Memory Write Memory Passive
REQUEST GRANT pins are used by other local bus masters to force the processor to release the local bus at the end of the processors current bus cycle Each pin is bidirectional with RQ GT0 having higher priority than RQ GT1 RQ GT pins have internal pull-up resistors and may be left unconnected The request grant sequence is as follows (see Page 2-24) 1 A pulse of 1 CLK wide from another local bus master indicates a local bus request (hold) to the 8086 (pulse 1) 2 During a T4 or T1 clock cycle a pulse 1 CLK wide from the 8086 to the requesting master (pulse 2) indicates that the 8086 has allowed the local bus to float and that it will enter the hold acknowledge state at the next CLK The CPUs bus interface unit is disconnected logically from the local bus during hold acknowledge 3 A pulse 1 CLK wide from the requesting master indicates to the 8086 (pulse 3) that the hold request is about to end and that the 8086 can reclaim the local bus at the next CLK Each master-master exchange of the local bus is a sequence of 3 pulses There must be one dead CLK cycle after each bus exchange Pulses are active LOW If the request is made while the CPU is performing a memory cycle it will release the local bus during T4 of the cycle when all the following conditions are met 1 Request occurs on or before T2 2 Current cycle is not the low byte of a word (on an odd address) 3 Current cycle is not the first acknowledge of an interrupt acknowledge sequence 4 A locked instruction is not currently executing If the local bus is idle when the request is made the two possible events will follow 1 Local bus will be released during the next clock 2 A memory cycle will start within 3 clocks Now the four rules for a currently active memory cycle apply with condition number 1 already satisfied LOCK output indicates that other system bus masters are not to gain control of the system bus while LOCK is active LOW The LOCK signal is activated by the LOCK prefix instruction and remains active until the completion of the next instruction This signal is active LOW and floats to 3-state OFF in hold acknowledge
LOCK
29
8086
Table 1 Pin Description (Continued) Symbol QS1 QS0 Pin No 24 25 Type O Name and Function QUEUE STATUS The queue status is valid during the CLK cycle after which the queue operation is performed QS1 and QS0 provide status to allow external tracking of the internal 8086 instruction queue QS1 0 (LOW) 0 1 (HIGH) 1 QS0 0 1 0 1 Characteristics No Operation First Byte of Op Code from Queue Empty the Queue Subsequent Byte from Queue
The following pin function descriptions are for the 8086 in minimum mode (i e MN MX e VCC) Only the pin functions which are unique to minimum mode are described all other pin functions are as described above
M IO 28 O STATUS LINE logically equivalent to S2 in the maximum mode It is used to distinguish a memory access from an I O access M IO becomes valid in the T4 preceding a bus cycle and remains valid until the final T4 of the cycle (M e HIGH IO e LOW) M IO floats to 3-state OFF in local bus hold acknowledge WRITE indicates that the processor is performing a write memory or write I O cycle depending on the state of the M IO signal WR is active for T2 T3 and TW of any write cycle It is active LOW and floats to 3-state OFF in local bus hold acknowledge INTA is used as a read strobe for interrupt acknowledge cycles It is active LOW during T2 T3 and TW of each interrupt acknowledge cycle ADDRESS LATCH ENABLE provided by the processor to latch the address into the 8282 8283 address latch It is a HIGH pulse active during T1 of any bus cycle Note that ALE is never floated DATA TRANSMIT RECEIVE needed in minimum system that desires to use an 8286 8287 data bus transceiver It is used to control the direction of data flow through the transceiver Logically DT R is equivalent to S1 in the maximum mode and its timing is the same as for M IO (T e HIGH R e LOW ) This signal floats to 3-state OFF in local bus hold acknowledge DATA ENABLE provided as an output enable for the 8286 8287 in a minimum system which uses the transceiver DEN is active LOW during each memory and I O access and for INTA cycles For a read or INTA cycle it is active from the middle of T2 until the middle of T4 while for a write cycle it is active from the beginning of T2 until the middle of T4 DEN floats to 3state OFF in local bus hold acknowledge HOLD indicates that another master is requesting a local bus hold To be acknowledged HOLD must be active HIGH The processor receiving the hold request will issue HLDA (HIGH) as an acknowledgement in the middle of a T4 or Ti clock cycle Simultaneous with the issuance of HLDA the processor will float the local bus and control lines After HOLD is detected as being LOW the processor will LOWer the HLDA and when the processor needs to run another cycle it will again drive the local bus and control lines Hold acknowledge (HLDA) and HOLD have internal pull-up resistors The same rules as for RQ GT apply regarding when the local bus will be released HOLD is not an asynchronous input External synchronization should be provided if the system cannot otherwise guarantee the setup time
WR
29
INTA ALE
24 25
O O
DT R
27
DEN
26
HOLD HLDA
31 30
I O
8086
bytes addressed as 00000(H) to FFFFF(H) The memory is logically divided into code data extra data and stack segments of up to 64K bytes each with each segment falling on 16-byte boundaries (See Figure 3a ) All memory references are made relative to base addresses contained in high speed segment registers The segment types were chosen based on the addressing needs of programs The segment register to be selected is automatically chosen according to the rules of the following table All information in one segment type share the same logical attributes (e g code or data) By structuring memory into relocatable areas of similar characteristics and by automatically selecting segment registers programs are shorter faster and more structured Word (16-bit) operands can be located on even or odd address boundaries and are thus not constrained to even boundaries as is the case in many 16-bit computers For address and data operands the least significant byte of the word is stored in the lower valued address location and the most significant byte in the next higher address location The BIU automatically performs the proper number of memory accesses one if the word operand is on an even byte boundary and two if it is on an odd byte boundary Except for the performance penalty this double access is transparent to the software This performance penalty does not occur for instruction fetches only word operands Physically the memory is organized as a high bank (D15 D8) and a low bank (D7 D0) of 512K 8-bit bytes addressed in parallel by the processors address lines A19 A1 Byte data with even addresses is transferred on the D7 D0 bus lines while odd addressed byte data (A0 HIGH) is transferred on the D15 D8 bus lines The processor provides two enable signals BHE and A0 to selectively allow reading from or writing into either an odd byte location even byte location or both The instruction stream is fetched from memory as words and is addressed internally by the processor to the byte level as necessary
FUNCTIONAL DESCRIPTION General Operation

The internal functions of the 8086 processor are partitioned logically into two processing units The first is the Bus Interface Unit (BIU) and the second is the Execution Unit (EU) as shown in the block diagram of Figure 1 These units can interact directly but for the most part perform as separate asynchronous operational processors The bus interface unit provides the functions related to instruction fetching and queuing operand fetch and store and address relocation This unit also provides the basic bus control The overlap of instruction pre-fetching provided by this unit serves to increase processor performance through improved bus bandwidth utilization Up to 6 bytes of the instruction stream can be queued while waiting for decoding and execution The instruction stream queuing mechanism allows the BIU to keep the memory utilized very efficiently Whenever there is space for at least 2 bytes in the queue the BIU will attempt a word fetch memory cycle This greatly reduces dead time on the memory bus The queue acts as a First-In-First-Out (FIFO) buffer from which the EU extracts instruction bytes as required If the queue is empty (following a branch instruction for example) the first byte into the queue immediately becomes available to the EU The execution unit receives pre-fetched instructions from the BIU queue and provides un-relocated operand addresses to the BIU Memory operands are passed through the BIU for processing by the EU which passes results to the BIU for storage See the Instruction Set description for further register set and architectural descriptions MEMORY ORGANIZATION The processor provides a 20-bit address to memory which locates the byte being referenced The memory is organized as a linear array of up to 1 million Memory Reference Need Instructions Stack Local Data External (Global) Data Segment Register Used CODE (CS) STACK (SS) DATA (DS) EXTRA (ES)
Segment Selection Rule Automatic with all instruction prefetch All stack pushes and pops Memory references relative to BP base register except data references Data references when relative to stack destination of string operation or explicitly overridden Destination of string operations explicitly selected using a segment override
8086
address FFFF0H through FFFFFH are reserved for operations including a jump to the initial program loading routine Following RESET the CPU will always begin execution at location FFFF0H where the jump must be Locations 00000H through 003FFH are reserved for interrupt operations Each of the 256 possible interrupt types has its service routine pointed to by a 4-byte pointer element consisting of a 16-bit segment address and a 16-bit offset address The pointer elements are assumed to have been stored at the respective places in reserved memory prior to occurrence of interrupts
MINIMUM AND MAXIMUM MODES

The requirements for supporting minimum and maximum 8086 systems are sufficiently different that they cannot be done efficiently with 40 uniquely defined pins Consequently the 8086 is equipped with a strap pin (MN MX) which defines the system configuration The definition of a certain subset of the pins changes dependent on the condition of the strap pin When MN MX pin is strapped to GND the 8086 treats pins 24 through 31 in maximum mode An 8288 bus controller interprets status information coded into S0 S2 S2 to generate bus timing and control signals compatible with the MULTIBUS architecture When the MN MX pin is strapped to VCC the 8086 generates bus control signals itself on pins 24 through 31 as shown in parentheses in Figure 2 Examples of minimum mode and maximum mode systems are shown in Figure 4 BUS OPERATION The 8086 has a combined address and data bus commonly referred to as a time multiplexed bus This technique provides the most efficient use of pins on the processor while permitting the use of a standard 40-lead package This local bus can be buffered directly and used throughout the system with address latching provided on memory and I O modules In addition the bus can also be demultiplexed at the processor with a single set of address latches if a standard non-multiplexed bus is desired for the system Each processor bus cycle consists of at least four CLK cycles These are referred to as T1 T2 T3 and T4 (see Figure 5) The address is emitted from the processor during T1 and data transfer occurs on the bus during T3 and T4 T2 is used primarily for changing the direction of the bus during read operations In the event that a NOT READY indication is given by the addressed device Wait states (TW) are inserted between T3 and T4 Each inserted Wait state is of the same duration as a CLK cycle Periods
231455 3
Figure 3a Memory Organization In referencing word data the BIU requires one or two memory cycles depending on whether or not the starting byte of the word is on an even or odd address respectively Consequently in referencing word operands performance can be optimized by locating data on even address boundaries This is an especially useful technique for using the stack since odd address references to the stack may adversely affect the context switching time for interrupt processing or task multiplexing
231455 4
Figure 3b Reserved Memory Locations Certain locations in memory are reserved for specific CPU operations (see Figure 3b) Locations from
8086
231455 5
Figure 4a Minimum Mode 8086 Typical Configuration
231455 6
Figure 4b Maximum Mode 8086 Typical Configuration 8
8086
can occur between 8086 bus cycles These are referred to as Idle states (Ti) or inactive CLK cycles The processor uses these cycles for internal housekeeping During T1 of any bus cycle the ALE (Address Latch Enable) signal is emitted (by either the processor or the 8288 bus controller depending on the MN MX strap) At the trailing edge of this pulse a valid address and certain status information for the cycle may be latched Status bits S0 S1 and S2 are used in maximum mode by the bus controller to identify the type of bus transaction according to the following table
S2 0 (LOW) 0 0 0 1 (HIGH) 1 1 1
S1 0 0 1 1 0 0 1 1
S0 0 1 0 1 0 1 0 1
Characteristics Interrupt Acknowledge Read I O Write I O Halt Instruction Fetch Read Data from Memory Write Data to Memory Passive (no bus cycle)
231455 8
Figure 5 Basic System Timing
8086
Status bits S3 through S7 are multiplexed with highorder address bits and the BHE signal and are therefore valid during T2 through T4 S3 and S4 indicate which segment register (see Instruction Set description) was used for this bus cycle in forming the address according to the following table S4 0 (LOW) 0 1 (HIGH) 1 S3 0 1 0 1 Stack Code or None Data INTERRUPT OPERATIONS S5 is a reflection of the PSW interrupt enable bit S6 e 0 and S7 is a spare status bit I O ADDRESSING In the 8086 I O operations can address up to a maximum of 64K I O byte registers or 32K I O word registers The I O address appears in the same format as the memory address on bus lines A15 A0 The address lines A19 A16 are zero in I O operations The variable I O instructions which use register DX as a pointer have full address capability while the direct I O instructions directly address one or two of the 256 I O byte locations in page 0 of the I O address space I O ports are addressed in the same manner as memory locations Even addressed bytes are transferred on the D7 D0 bus lines and odd addressed bytes on D15 D8 Care must be taken to assure that each register within an 8-bit peripheral located on the lower portion of the bus be addressed as even Interrupt operations fall into two classes software or hardware initiated The software initiated interrupts and software aspects of hardware interrupts are specified in the Instruction Set description Hardware interrupts can be classified as non-maskable or maskable Interrupts result in a transfer of control to a new program location A 256-element table containing address pointers to the interrupt service program locations resides in absolute locations 0 through 3FFH (see Figure 3b) which are reserved for this purpose Each element in the table is 4 bytes in size and corresponds to an interrupt type An interrupting device supplies an 8-bit type number during the interrupt acknowledge sequence which is used to vector through the appropriate element to the new interrupt service program location NON-MASKABLE INTERRUPT (NMI) The processor provides a single non-maskable interrupt pin (NMI) which has higher priority than the maskable interrupt request pin (INTR) A typical use would be to activate a power failure routine The NMI is edge-triggered on a LOW-to-HIGH transition The activation of this pin causes a type 2 interrupt (See Instruction Set description ) NMI is required to have a duration in the HIGH state of greater than two CLK cycles but is not required to be synchronized to the clock Any high-going transition of NMI is latched on-chip and will be serviced at the end of the current instruction or between whole moves of a block-type instruction Worst case response to NMI would be for multiply divide and variable shift instructions There is no specification on the occurrence of the low-going edge it may occur before during or after the servicing of NMI Another high-going edge triggers another response if it occurs after the start of the NMI procedure The signal must be free of logical spikes in general and be free of bounces on the low-going edge to avoid triggering extraneous responses Characteristics Alternate Data (extra segment) NMI asserted prior to the 2nd clock after the end of RESET will not be honored If NMI is asserted after that point and during the internal reset sequence the processor may execute one instruction before responding to the interrupt A hold request active immediately after RESET will be honored before the first instruction fetch All 3-state outputs float to 3-state OFF during RESET Status is active in the idle state for the first clock after RESET becomes active and then floats to 3-state OFF ALE and HLDA are driven low
External Interface
PROCESSOR RESET AND INITIALIZATION Processor initialization or start up is accomplished with activation (HIGH) of the RESET pin The 8086 RESET is required to be HIGH for greater than 4 CLK cycles The 8086 will terminate operations on the high-going edge of RESET and will remain dormant as long as RESET is HIGH The low-going transition of RESET triggers an internal reset sequence for approximately 10 CLK cycles After this interval the 8086 operates normally beginning with the instruction in absolute location FFFF0H (see Figure 3b) The details of this operation are specified in the Instruction Set description of the MCS-86 Family Users Manual The RESET input is internally synchronized to the processor clock At initialization the HIGH-to-LOW transition of RESET must occur no sooner than 50 ms after power-up to allow complete initialization of the 8086 10
8086
MASKABLE INTERRUPT (INTR) The 8086 provides a single interrupt request input (INTR) which can be masked internally by software with the resetting of the interrupt enable FLAG status bit The interrupt request signal is level triggered It is internally synchronized during each clock cycle on the high-going edge of CLK To be responded to INTR must be present (HIGH) during the clock period preceding the end of the current instruction or the end of a whole move for a blocktype instruction During the interrupt response sequence further interrupts are disabled The enable bit is reset as part of the response to any interrupt (INTR NMI software interrupt or single-step) although the FLAGS register which is automatically pushed onto the stack reflects the state of the processor prior to the interrupt Until the old FLAGS register is restored the enable bit will be zero unless specifically set by an instruction During the response sequence (Figure 6) the processor executes two successive (back-to-back) interrupt acknowledge cycles The 8086 emits the LOCK signal from T2 of the first bus cycle until T2 of the second A local bus hold request will not be honored until the end of the second bus cycle In the second bus cycle a byte is fetched from the external interrupt system (e g 8259A PIC) which identifies the source (type) of the interrupt This byte is multiplied by four and used as a pointer into the interrupt vector lookup table An INTR signal left HIGH will be continually responded to within the limitations of the enable bit and sample period The INTERRUPT RETURN instruction includes a FLAGS pop which returns the status of the original interrupt enable bit when it restores the FLAGS
HALT When a software HALT instruction is executed the processor indicates that it is entering the HALT state in one of two ways depending upon which mode is strapped In minimum mode the processor issues one ALE with no qualifying bus control signals In maximum mode the processor issues appropriate HALT status on S2 S1 and S0 and the 8288 bus controller issues one ALE The 8086 will not leave the HALT state when a local bus hold is entered while in HALT In this case the processor reissues the HALT indicator An interrupt request or RESET will force the 8086 out of the HALT state READ MODIFY WRITE (SEMAPHORE) OPERATIONS VIA LOCK The LOCK status information is provided by the processor when directly consecutive bus cycles are required during the execution of an instruction This provides the processor with the capability of performing read modify write operations on memory (via the Exchange Register With Memory instruction for example) without the possibility of another system bus master receiving intervening memory cycles This is useful in multi-processor system configurations to accomplish test and set lock operations The LOCK signal is activated (forced LOW) in the clock cycle following the one in which the software LOCK prefix instruction is decoded by the EU It is deactivated at the end of the last bus cycle of the instruction following the LOCK prefix instruction While LOCK is active a request on a RQ GT pin will be recorded and then honored at the end of the LOCK
231455 9
Figure 6 Interrupt Acknowledge Sequence 11
8086
EXTERNAL SYNCHRONIZATION VIA TEST As an alternative to the interrupts and general I O capabilities the 8086 provides a single softwaretestable input known as the TEST signal At any time the program may execute a WAIT instruction If at that time the TEST signal is inactive (HIGH) program execution becomes suspended while the processor waits for TEST to become active It must remain active for at least 5 CLK cycles The WAIT instruction is re-executed repeatedly until that time This activity does not consume bus cycles The processor remains in an idle state while waiting All 8086 drivers go to 3-state OFF if bus Hold is entered If interrupts are enabled they may occur while the processor is waiting When this occurs the processor fetches the WAIT instruction one extra time processes the interrupt and then re-fetches and reexecutes the WAIT instruction upon returning from the interrupt
SYSTEM TIMING
MINIMUM SYSTEM
The read cycle begins in T1 with the assertion of the Address Latch Enable (ALE) signal The trailing (lowgoing) edge of this signal is used to latch the address information which is valid on the local bus at this time into the address latch The BHE and A0 signals address the low high or both bytes From T1 to T4 the M IO signal indicates a memory or I O operation At T2 the address is removed from the local bus and the bus goes to a high impedance state The read control signal is also asserted at T2 The read (RD) signal causes the addressed device to enable its data bus drivers to the local bus Some time later valid data will be available on the bus and the addressed device will drive the READY line HIGH When the processor returns the read signal to a HIGH level the addressed device will again 3state its bus drivers If a transceiver is required to buffer the 8086 local bus signals DT R and DEN are provided by the 8086 A write cycle also begins with the assertion of ALE and the emission of the address The M IO signal is again asserted to indicate a memory or I O write operation In the T2 immediately following the address emission the processor emits the data to be written into the addressed location This data remains valid until the middle of T4 During T2 T3 and TW the processor asserts the write control signal The write (WR) signal becomes active at the beginning of T2 as opposed to the read which is delayed somewhat into T2 to provide time for the bus to float The BHE and A0 signals are used to select the proper byte(s) of the memory IO word to be read or written according to the following table BHE 0 0 1 1 A0 0 1 0 1 Characteristics Whole word Upper byte from to odd address Lower byte from to even address None
Basic System Timing

Typical system configurations for the processor operating in minimum mode and in maximum mode are shown in Figures 4a and 4b respectively In minimum mode the MN MX pin is strapped to VCC and the processor emits bus control signals in a manner similar to the 8085 In maximum mode the MN MX pin is strapped to VSS and the processor emits coded status information which the 8288 bus controller uses to generate MULTIBUS compatible bus control signals Figure 5 illustrates the signal timing relationships
I O ports are addressed in the same manner as memory location Even addressed bytes are transferred on the D7 D0 bus lines and odd addressed bytes on D15 D8 The basic difference between the interrupt acknowledge cycle and a read cycle is that the interrupt acknowledge signal (INTA) is asserted in place of the read (RD) signal and the address bus is floated (See Figure 6 ) In the second of two successive INTA cycles a byte of information is read from bus
231455 10
Figure 7 8086 Register Model
12
8086
lines D7 D0 as supplied by the inerrupt system logic (i e 8259A Priority Interrupt Controller) This byte identifies the source (type) of the interrupt It is multiplied by four and used as a pointer into an interrupt vector lookup table as described earlier BUS TIMING MEDIUM SIZE SYSTEMS acknowledge or software halt The 8288 thus issues control signals specifying memory read or write I O read or write or interrupt acknowledge The 8288 provides two types of write strobes normal and advanced to be applied as required The normal write strobes have data valid at the leading edge of write The advanced write strobes have the same timing as read strobes and hence data isnt valid at the leading edge of write The transceiver receives the usual DIR and G inputs from the 8288s DT R and DEN The pointer into the interrupt vector table which is passed during the second INTA cycle can derive from an 8259A located on either the local bus or the system bus If the master 8259A Priority Interrupt Controller is positioned on the local bus a TTL gate is required to disable the transceiver when reading from the master 8259A during the interrupt acknowledge sequence and software poll
For medium size systems the MN MX pin is connected to VSS and the 8288 Bus Controller is added to the system as well as a latch for latching the system address and a transceiver to allow for bus loading greater than the 8086 is capable of handling Signals ALE DEN and DT R are generated by the 8288 instead of the processor in this configuration although their timing remains relatively the same The 8086 status outputs (S2 S1 and S0) provide type-of-cycle information and become 8288 inputs This bus cycle information specifies read (code data or I O) write (data or I O) interrupt
13
8086
ABSOLUTE MAXIMUM RATINGS

Ambient Temperature Under Bias Storage Temperature Voltage on Any Pin with Respect to Ground Power Dissipation 0 C to 70 C
b 65 C to a 150 C b 1 0V to a 7V
NOTICE This is a production data sheet The specifications are subject to change without notice
2 5W
WARNING Stressing the device beyond the Absolute Maximum Ratings may cause permanent damage These are stress ratings only Operation beyond the Operating Conditions is not recommended and extended exposure beyond the Operating Conditions may affect device reliability
D C CHARACTERISTICS
(8086 TA e 0 C to 70 C VCC e 5V g 10%) (8086-1 TA e 0 C to 70 C VCC e 5V g 5%) (8086-2 TA e 0 C to 70 C VCC e 5V g 5%) Min
b0 5
Symbol VIL VIH VOL VOH ICC
Parameter Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Power Supply Current 8086 8086-1 8086-2 Input Leakage Current Output Leakage Current Clock Input Low Voltage Clock Input High Voltage Capacitance of Input Buffer (All input except AD0 AD15 RQ GT) Capacitance of I O Buffer (AD0 AD15 RQ GT)
Max
a0 8
Units V V V V
Test Conditions (Note 1) (Notes 1 2) IOL e 2 5 mA IOH e b 400 mA TA e 25 C 0V s VIN s VCC (Note 3) 0 45V s VOUT s VCC
20
VCC a 0 5 0 45
24 340 360 350

g 10 g 10
mA mA mA V V pF
ILI ILO VCL VCH CIN
b0 5
a0 6
39
VCC a 1 0 15
fc e 1 MHz
CIO
15
pF
fc e 1 MHz
NOTES 1 VIL tested with MN MX Pin e 0V VIH tested with MN MX Pin e 5V MN MX Pin is a Strap Pin 2 Not applicable to RQ GT0 and RQ GT1 (Pins 30 and 31) 3 HOLD and HLDA ILI min e 30 mA max e 500 mA
14
8086
A C CHARACTERISTICS
(8086 TA e 0 C to 70 C VCC e 5V g 10%) (8086-1 TA e 0 C to 70 C VCC e 5V g 5%) (8086-2 TA e 0 C to 70 C VCC e 5V g 5%)
MINIMUM COMPLEXITY SYSTEM TIMING REQUIREMENTS Symbol TCLCL TCLCH TCHCL TCH1CH2 TCL2CL1 TDVCL TCLDX TR1VCL Parameter CLK Cycle Period CLK Low Time CLK High Time CLK Rise Time CLK Fall Time Data in Setup Time Data in Hold Time RDY Setup Time into 8284A (See Notes 1 2) RDY Hold Time into 8284A (See Notes 1 2) READY Setup Time into 8086 READY Hold Time into 8086 READY Inactive to CLK (See Note 3) HOLD Setup Time INTR NMI TEST Setup Time (See Note 2) Input Rise Time (Except CLK) Input Fall Time (Except CLK) 30 10 35 8086 Min 200 118 69 10 10 5 10 35 Max 500 8086-1 Min 100 53 39 10 10 20 10 35 Max 500 8086-2 Min 125 68 44 10 10 Max 500 ns ns ns ns ns ns ns ns From 1 0V to 3 5V From 3 5V to 1 0V Units Test Conditions
TCLR1X
ns
TRYHCH TCHRYX TRYLCL THVCH TINVCH
118 30
b8
53 20
b 10
68 20
b8
ns ns ns ns ns
35 30
20 15
20 15
TILIH TIHIL
20 12
20 12
20 12
ns ns
From 0 8V to 2 0V From 2 0V to 0 8V
15
8086
A C CHARACTERISTICS (Continued)
TIMING RESPONSES
Symbol TCLAV TCLAX TCLAZ TLHLL TCLLH TCHLL TLLAX TCLDV TCHDX Parameter Address Valid Delay Address Hold Time Address Float Delay ALE Width ALE Active Delay ALE Inactive Delay Address Hold Time Data Valid Delay Data Hold Time TCHCL-10 10 10 TCLCH-30 10 10 10 0 10 10 TCLCL-45 10 2TCLCL-75 2TCLCL-60 TCLCH-60 20 12 160 165 150 110 110 110 110 8086 Min 10 10 TCLAX TCLCH-20 80 85 TCHCL-10 10 10 TCLCH-25 10 10 10 0 10 10 TCLCL-35 10 2TCLCL-40 2TCLCL-35 TCLCH-35 20 12 60 70 60 50 45 50 50 80 Max 110 8086-1 Min 10 10 10 TCLCH-10 40 45 TCHCL-10 10 10 TCLCH-30 10 10 10 0 10 10 TCLCL-40 10 2TCLCL-50 2TCLCL-40 TCLCH-40 20 12 100 100 80 70 60 70 60 40 Max 50 8086-2 Min 10 10 TCLAX TCLCH-10 50 55 50 Max 60 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns From 0 8V to 2 0V From 2 0V to 0 8V CL e 20100 pF for all 8086 Outputs (In addition to 8086 selfload) Units Test Conditions
TWHDX Data Hold Time After WR TCVCTV Control Active Delay 1 TCHCTV Control Active Delay 2 TCVCTX Control Inactive Delay TAZRL TCLRL TCLRH TRHAV Address Float to READ Active RD Active Delay RD Inactive Delay RD Inactive to Next Address Active
TCLHAV HLDA Valid Delay TRLRH RD Width
TWLWH WR Width TAVAL TOLOH TOHOL Address Valid to ALE Low Output Rise Time Output Fall Time
NOTES 1 Signal at 8284A shown for reference only 2 Setup requirement for asynchronous signal only to guarantee recognition at next CLK 3 Applies only to T2 state (8 ns into T3)
16
8086
A C TESTING INPUT OUTPUT WAVEFORM
A C TESTING LOAD CIRCUIT
231455-11 A C Testing Inputs are driven at 2 4V for a Logic 1 and 0 45V for a Logic 0 Timing measurements are made at 1 5V for both a Logic 1 and 0 231455 12 CL Includes Jig Capacitance
WAVEFORMS
MINIMUM MODE
231455 13
17
8086
WAVEFORMS (Continued)
MINIMUM MODE (Continued)
231455 14 SOFTWARE HALT RD WR INTA e VOH DT R e INDETERMINATE
NOTES 1 All signals switch between VOH and VOL unless otherwise specified 2 RDY is sampled near the end of T2 T3 TW to determine if TW machines states are to be inserted 3 Two INTA cycles run back-to-back The 8086 LOCAL ADDR DATA BUS is floating during both INTA cycles Control signals shown for second INTA cycle 4 Signals at 8284A are shown for reference only 5 All timing measurements are made at 1 5V unless otherwise noted
18
8086
A C CHARACTERISTICS
MAX MODE SYSTEM (USING 8288 BUS CONTROLLER) TIMING REQUIREMENTS Symbol TCLCL TCLCH TCHCL TCH1CH2 TCL2CL1 TDVCL TCLDX TR1VCL Parameter CLK Cycle Period CLK Low Time CLK High Time CLK Rise Time CLK Fall Time Data in Setup Time Data in Hold Time RDY Setup Time into 8284A (Notes 1 2) RDY Hold Time into 8284A (Notes 1 2) READY Setup Time into 8086 READY Hold Time into 8086 READY Inactive to CLK (Note 4) Setup Time for Recognition (INTR NMI TEST) (Note 2) RQ GT Setup Time (Note 5) RQ Hold Time into 8086 Input Rise Time (Except CLK) Input Fall Time (Except CLK) 30 10 35 8086 Min 200 118 69 10 10 5 10 35 Max 500 8086-1 Min 100 53 39 10 10 20 10 35 Max 500 8086-2 Min 125 68 44 10 10 Max 500 ns ns ns ns ns ns ns ns From 1 0V to 3 5V From 3 5V to 1 0V Units Test Conditions
TCLR1X
ns
TRYHCH TCHRYX TRYLCL TINVCH
118 30
b8
53 20
b 10
68 20
b8
ns ns ns ns
30
15
15
TGVCH TCHGX TILIH TIHIL
30 40 20 12
15 20 20 12
15 30 20 12
ns ns ns ns From 0 8V to 2 0V From 2 0V to 0 8V
19
8086
TIMING RESPONSES Symbol TCLML TCLMH TRYHSH Parameter Command Active Delay (See Note 1) Command Inactive Delay (See Note 1) READY Active to Status Passive (See Note 3) Status Active Delay Status Inactive Delay Address Valid Delay Address Hold Time Address Float Delay Status Valid to ALE High (See Note 1) Status Valid to MCE High (See Note 1) CLK Low to ALE Valid (See Note 1) CLK Low to MCE High (See Note 1) ALE Inactive Delay (See Note 1) MCE Inactive Delay (See Note 1) Data Valid Delay Data Hold Time Control Active Delay (See Note 1) Control Inactive Delay (See Note 1) Address Float to READ Active RD Active Delay RD Inactive Delay 10 10 5 10 0 10 10 165 150 45 45 10 10 10 10 TCLAX 80 15 15 8086 Min 10 10 Max 35 35 110 8086-1 Min 10 10 Max 35 35 45 8086-2 Min 10 10 Max 35 35 65 ns ns ns Units Test Conditions
TCHSV TCLSH TCLAV TCLAX TCLAZ TSVLH TSVMCH
110 130 110
10 10 10 10 10
45 55 50
10 10 10 10
60 70 60
ns ns ns ns
40 15 15
TCLAX
50 15 15
ns ns ns
TCLLH TCLMCH TCHLL TCLMCL TCLDV TCHDX TCVNV TCVNX TAZRL TCLRL TCLRH
15 15 15 15 110 10 10 5 10 0 10 10
15 15 15 15 50 10 10 45 45 5 10 0 70 60 10 10
15 15 15 15 60
ns ns ns ns ns ns
CL e 20 100 pF for all 8086 Outputs (In addition to 8086 self-load)
45 45
ns ns ns
100 80
ns ns
20
8086
TIMING RESPONSES (Continued) Symbol TRHAV Parameter 8086 Min RD Inactive to Next TCLCL-45 Address Active 50 Max 8086-1 Min TCLCL-35 50 Max 8086-2 Min TCLCL-40 50 Max ns ns CL e 20 100 pF for all 8086 Outputs (In addition to 8086 self-load) Units Test Conditions
TCHDTL Direction Control Active Delay (Note 1) TCHDTH Direction Control Inactive Delay (Note 1) TCLGL TCLGH TRLRH TOLOH TOHOL GT Active Delay GT Inactive Delay RD Width Output Rise Time Output Fall Time 0 0 2TCLCL-75
30
30
30
ns
85 85
0 0 2TCLCL-40
38 45
0 0 2TCLCL-50
50 50
ns ns ns
20 12
20 12
20 12
ns ns
From 0 8V to 2 0V From 2 0V to 0 8V
NOTES 1 Signal at 8284A or 8288 shown for reference only 2 Setup requirement for asynchronous signal only to guarantee recognition at next CLK 3 Applies only to T3 and wait states 4 Applies only to T2 state (8 ns into T3)
21
8086
WAVEFORMS
MAXIMUM MODE
231455 15
22
8086
MAXIMUM MODE (Continued)
231455 16
NOTES 1 All signals switch between VOH and VOL unless otherwise specified 2 RDY is sampled near the end of T2 T3 TW to determine if TW machines states are to be inserted 3 Cascade address is valid between first and second INTA cycle 4 Two INTA cycles run back-to-back The 8086 LOCAL ADDR DATA BUS is floating during both INTA cycles Control for pointer address is shown for second INTA cycle 5 Signals at 8284A or 8288 are shown for reference only 6 The issuance of the 8288 command and control signals (MRDC MWTC AMWC IORC IOWC AIOWC INTA and DEN) lags the active high 8288 CEN 7 All timing measurements are made at 1 5V unless otherwise noted 8 Status inactive in state just prior to T4
23
8086
ASYNCHRONOUS SIGNAL RECOGNITION
231455 17
NOTE 1 Setup requirements for asynchronous signals only to guarantee recognition at next CLK
BUS LOCK SIGNAL TIMING (MAXIMUM MODE ONLY)
RESET TIMING
231455 18 231455 19
REQUEST GRANT SEQUENCE TIMING (MAXIMUM MODE ONLY)
231455 20
NOTE The coprocessor may not drive the buses outside the region shown without risking contention
24
8086
HOLD HOLD ACKNOWLEDGE TIMING (MINIMUM MODE ONLY)
231455 21
25
8086
Table 2 Instruction Set Summary

Mnemonic and Description DATA TRANSFER MOV e Move Register Memory to from Register Immediate to Register Memory Immediate to Register Memory to Accumulator Accumulator to Memory Register Memory to Segment Register Segment Register to Register Memory PUSH e Push Register Memory Register Segment Register POP e Pop Register Memory Register Segment Register XCHG e Exchange Register Memory with Register Register with Accumulator IN e Input from Fixed Port Variable Port OUT e Output to Fixed Port Variable Port XLAT e Translate Byte to AL LEA e Load EA to Register LDS e Load Pointer to DS LES e Load Pointer to ES LAHF e Load AH with Flags SAHF e Store AH into Flags PUSHF e Push Flags POPF e Pop Flags 1110011w 1110111w 11010111 10001101 11000101 11000100 10011111 10011110 10011100 10011101 mod reg r m mod reg r m mod reg r m port 1110010w 1110110w port 1000011w 1 0 0 1 0 reg mod reg r m 10001111 0 1 0 1 1 reg 0 0 0 reg 1 1 1 mod 0 0 0 r m 11111111 0 1 0 1 0 reg 0 0 0 reg 1 1 0 mod 1 1 0 r m 76543210 100010dw 1100011w 1 0 1 1 w reg 1010000w 1010001w 10001110 10001100 76543210 mod reg r m data data if w e 1 addr-high addr-high data if w e 1 76543210 76543210 Instruction Code
mod 0 0 0 r m data addr-low addr-low mod 0 reg r m mod 0 reg r m
Mnemonics
Intel 1978
26
8086
Table 2 Instruction Set Summary (Continued)

Mnemonic and Description ARITHMETIC ADD e Add Reg Memory with Register to Either Immediate to Register Memory Immediate to Accumulator ADC e Add with Carry Reg Memory with Register to Either Immediate to Register Memory Immediate to Accumulator INC e Increment Register Memory Register AAA e ASCII Adjust for Add BAA e Decimal Adjust for Add SUB e Subtract Reg Memory and Register to Either Immediate from Register Memory Immediate from Accumulator SSB e Subtract with Borrow Reg Memory and Register to Either Immediate from Register Memory Immediate from Accumulator DEC e Decrement Register memory Register NEG e Change sign CMP e Compare Register Memory and Register Immediate with Register Memory Immediate with Accumulator AAS e ASCII Adjust for Subtract DAS e Decimal Adjust for Subtract MUL e Multiply (Unsigned) IMUL e Integer Multiply (Signed) AAM e ASCII Adjust for Multiply DIV e Divide (Unsigned) IDIV e Integer Divide (Signed) AAD e ASCII Adjust for Divide CBW e Convert Byte to Word CWD e Convert Word to Double Word 001110dw 100000sw 0011110w 00111111 00101111 1111011w 1111011w 11010100 1111011w 1111011w 11010101 10011000 10011001 mod 1 0 0 r m mod 1 0 1 r m 00001010 mod 1 1 0 r m mod 1 1 1 r m 00001010 mod reg r m mod 1 1 1 r m data data data if w e 1 data if s w e 01 1111111w 0 1 0 0 1 reg 1111011w mod 0 1 1 r m mod 0 0 1 r m 000110dw 100000sw 000111w mod reg r m mod 0 1 1 r m data data data if w e 1 data if s w e 01 001010dw 100000sw 0010110w mod reg r m mod 1 0 1 r m data data data if w e 1 data if s w e 01 1111111w 0 1 0 0 0 reg 00110111 00100111 mod 0 0 0 r m 000100dw 100000sw 0001010w mod reg r m mod 0 1 0 r m data data data if w e 1 data if s w e 01 000000dw 100000sw 0000010w mod reg r m mod 0 0 0 r m data data data if w e 1 data if s w e 01 76543210 Instruction Code 76543210 76543210 76543210
Mnemonics
Intel 1978
27
8086

Mnemonic and Description LOGIC NOT e Invert SHL SAL e Shift Logical Arithmetic Left SHR e Shift Logical Right SAR e Shift Arithmetic Right ROL e Rotate Left ROR e Rotate Right RCL e Rotate Through Carry Flag Left RCR e Rotate Through Carry Right AND e And Reg Memory and Register to Either Immediate to Register Memory Immediate to Accumulator TEST e And Function to Flags No Result Register Memory and Register Immediate Data and Register Memory Immediate Data and Accumulator OR e Or Reg Memory and Register to Either Immediate to Register Memory Immediate to Accumulator XOR e Exclusive or Reg Memory and Register to Either Immediate to Register Memory Immediate to Accumulator STRING MANIPULATION REP e Repeat MOVS e Move Byte Word CMPS e Compare Byte Word SCAS e Scan Byte Word LODS e Load Byte Wd to AL AX STOS e Stor Byte Wd from AL A CONTROL TRANSFER CALL e Call Direct within Segment Indirect within Segment Direct Intersegment 11101000 11111111 10011010 disp-low mod 0 1 0 r m offset-low seg-low Indirect Intersegment 11111111 mod 0 1 1 r m offset-high seg-high disp-high 1111001z 1010010w 1010011w 1010111w 1010110w 1010101w 001100dw 1000000w 0011010w mod reg r m mod 1 1 0 r m data data data if w e 1 data if w e 1 000010dw 1000000w 0000110w mod reg r m mod 0 0 1 r m data data data if w e 1 data if w e 1 1000010w 1111011w 1010100w mod reg r m mod 0 0 0 r m data data data if w e 1 data if w e 1 001000dw 1000000w 0010010w mod reg r m mod 1 0 0 r m data data data if w e 1 data if w e 1 76543210 1111011w 110100vw 110100vw 110100vw 110100vw 110100vw 110100vw 110100vw Instruction Code 76543210 mod 0 1 0 r m mod 1 0 0 r m mod 1 0 1 r m mod 1 1 1 r m mod 0 0 0 r m mod 0 0 1 r m mod 0 1 0 r m mod 0 1 1 r m 76543210 76543210
Mnemonics
Intel 1978
28
8086

Mnemonic and Description JMP e Unconditional Jump Direct within Segment Direct within Segment-Short Indirect within Segment Direct Intersegment 76543210 11101001 11101011 11111111 11101010 Instruction Code 76543210 disp-low disp mod 1 0 0 r m offset-low seg-low Indirect Intersegment RET e Return from CALL Within Segment Within Seg Adding Immed to SP Intersegment Intersegment Adding Immediate to SP JE JZ e Jump on Equal Zero JL JNGE e Jump on Less Not Greater or Equal JLE JNG e Jump on Less or Equal Not Greater JB JNAE e Jump on Below Not Above or Equal JBE JNA e Jump on Below or Equal Not Above JP JPE e Jump on Parity Parity Even JO e Jump on Overflow JS e Jump on Sign JNE JNZ e Jump on Not Equal Not Zero JNL JGE e Jump on Not Less Greater or Equal JNLE JG e Jump on Not Less or Equal Greater JNB JAE e Jump on Not Below Above or Equal JNBE JA e Jump on Not Below or Equal Above JNP JPO e Jump on Not Par Par Odd JNO e Jump on Not Overflow JNS e Jump on Not Sign LOOP e Loop CX Times LOOPZ LOOPE e Loop While Zero Equal LOOPNZ LOOPNE e Loop While Not Zero Equal JCXZ e Jump on CX Zero INT e Interrupt Type Specified Type 3 INTO e Interrupt on Overflow IRET e Interrupt Return 11001101 11001100 11001110 11001111 type 11000011 11000010 11001011 11001010 01110100 01111100 01111110 01110010 01110110 01111010 01110000 01111000 01110101 01111101 01111111 01110011 01110111 01111011 01110001 01111001 11100010 11100001 11100000 11100011 data-low disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp data-high data-low data-high 11111111 mod 1 0 1 r m offset-high seg-high 76543210 disp-high
29
8086

Mnemonic and Description 76543210 PROCESSOR CONTROL CLC e Clear Carry CMC e Complement Carry STC e Set Carry CLD e Clear Direction STD e Set Direction CLI e Clear Interrupt STI e Set Interrupt HLT e Halt WAIT e Wait ESC e Escape (to External Device) LOCK e Bus Lock Prefix 11111000 11110101 11111001 11111100 11111101 11111010 11111011 11110100 10011011 11011xxx 11110000 mod x x x r m Instruction Code 76543210
NOTES AL e 8-bit accumulator AX e 16-bit accumulator CX e Count register DS e Data segment ES e Extra segment Above below refers to unsigned value Greater e more positive Less e less positive (more negative) signed values if d e 1 then to reg if d e 0 then from reg if w e 1 then word instruction if w e 0 then byte instruction if mod e 11 then r m is treated as a REG field if mod e 00 then DISP e 0 disp-low and disp-high are absent if mod e 01 then DISP e disp-low sign-extended to 16 bits disp-high is absent if mod e 10 then DISP e disp-high disp-low if r m e 000 then EA e (BX) a (SI) a DISP if r m e 001 then EA e (BX) a (DI) a DISP if r m e 010 then EA e (BP) a (SI) a DISP if r m e 011 then EA e (BP) a (DI) a DISP if r m e 100 then EA e (SI) a DISP if r m e 101 then EA e (DI) a DISP if r m e 110 then EA e (BP) a DISP if r m e 111 then EA e (BX) a DISP DISP follows 2nd byte of instruction (before data if required) except if mod e 00 and r m e 110 then EA e disp-high disp-low Mnemonics Intel 1978
if s w e 01 then 16 bits of immediate data form the operand if s w e 11 then an immediate data byte is sign extended to form the 16-bit operand if v e 0 then count e 1 if v e 1 then count in (CL) e dont care x z is used for string primitives for comparison with ZF FLAG SEGMENT OVERRIDE PREFIX
0 0 1 reg 1 1 0
REG is assigned according to the following table
16-Bit (w e 1) 000 001 010 011 100 101 110 111 AX CX DX BX SP BP SI DI
8-Bit (w e 0) 000 001 010 011 100 101 110 111 AL CL DL BL AH CH DH BH
Segment 00 ES 01 CS 10 SS 11 DS
Instructions which reference the flag register file as a 16-bit object use the symbol FLAGS to represent the file
FLAGS e X X X X (OF) (DF) (IF) (TF) (SF) (ZF) X (AF) X (PF) X (CF)
DATA SHEET REVISION REVIEW

The following list represents key differences between this and the -004 data sheet Please review this summary carefully 1 The Intel 8086 implementation technology (HMOS) has been changed to (HMOS-III) 2 Delete all changes from 1985 Handbook Specification sentences
30
8086/88 Chip Set
CMPE 310
8086/88 Device Specications Both are packaged in DIP (Dual In-Line Packages). 8086: 16-bit microprocessor with a 16-bit data bus 8088: 16-bit microprocessor with an 8-bit data bus.
Both are 5V parts: 8086: Draws a maximum supply current of 360mA. 8086: Draws a maximum supply current of 340mA. 80C86/80C88: CMOS version draws 10mA with temp spec -40 to 225degF.
Input/Output current levels: OUTPUT INPUT Logic level Voltage Logic level Voltage Current Current 0 0 0.45V max +2mA max 0.8V max +/- 10uA max 1 1 2.4V min - 400uA max 2.0V min +/- 10uA max
Yields a 350mV noise immunity for logic 0 (Output max can be as high as 450mV while input max can be no higher than 800mV). This limits the loading on the outputs.
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(Feb. 20, 2002)
1966
UMBC
8086/88 Chip Set
CMPE 310
8086/88 Pinout
8086 CPU
MIN MODE (MAX MODE)
GND AD14 AD13 AD12 AD11 AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 NMI INTR CLK GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 (RQ/GT0) (RQ/GT1) (LOCK) (S2) (S1) (S0) (QS0) (QS1) 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
VCC AD15 A16/S3 A17/S4 A18/S5 A19/S6 BHE/S7 MN/MX RD Hold HLDA WR M/IO DT/R DEN ALE INTA TEST READY RESET
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(Feb. 20, 2002)
1966
UMBC
8086/88 Chip Set
CMPE 310
8086/88 Pinout Pin functions: AD15-AD0 Multiplexed address(ALE=1)/data bus(ALE=0). A19/S6-A16/S3 (multiplexed) High order 4 bits of the 20-bit address OR status bits S6-S3. M/IO Indicates if address is a Memory or IO address. RD When 0, data bus is driven by memory or an I/O device. WR Microprocessor is driving data bus to memory or an I/O device. When 0, data bus contains valid data. ALE (Address latch enable) When 1, address data bus contains a memory or I/O address. DT/R (Data Transmit/Receive) Data bus is transmitting/receiving data. DEN (Data bus Enable) Activates external data bus buffers. 3 (Feb. 20, 2002)
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1966
UMBC
8086/88 Chip Set
CMPE 310
8086/88 Pinout Pin functions: S7, S6, S5, S4, S3, S2, S1, S0 S7: Logic 1, S6: Logic 0. S5: Indicates condition of IF ag bits. S4-S3: Indicate which segment is accessed during current bus cycle: S3 0 1 0 1 Code or no segment Data segment Function Interrupt Ack I/O Read I/O Write Halt S2 1 1 1 1 S1 0 0 1 1 S0 0 1 0 1 Function Opcode Fetch Memory Read Memory Write Passive S0 0 1 0 1 Function Extra segment Stack segment
S4 0 0 1 1
S2, S1, S0: Indicate function of current bus cycle (decoded by 8288).
S2 0 0
S1 0 0
0 0
1 1
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(Feb. 20, 2002)
1966
UMBC
8086/88 Chip Set
CMPE 310
8086/88 Pinout Pin functions: INTR When 1 and IF=1, microprocessor prepares to service interrupt. INTA becomes active after current instruction completes. INTA Interrupt Acknowledge generated by the microprocessor in response to INTR. Causes the interrupt vector to be put onto the data bus. NMI Non-maskable interrupt. Similar to INTR except IF ag bit is not consulted and interrupt is vector 2.
CLK Clock input must have a duty cycle of 33% (high for 1/3 and low for 2/ 3s) VCC/GND Power supply (5V) and GND (0V).
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(Feb. 20, 2002)
1966
UMBC
8086/88 Chip Set
CMPE 310
8086/88 Pinout Pin functions: MN/MX Select minimum (5V) or maximum mode (0V) of operation. BHE Bus High Enable. Enables the most signicant data bus bits (D15-D8)
during a read or write operation.
READY Used to insert wait states (controlled by memory and IO for reads/ writes) into the microprocessor. RESET Microprocessor resets if this pin is held high for 4 clock periods. Instruction execution begins at FFFF0H and IF ag is cleared.
TEST An input that is tested by the WAIT instruction. Commonly connected to the 8087 coprocessor.
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(Feb. 20, 2002)
1966
UMBC
8086/88 Chip Set
CMPE 310
8086/88 Pinout Pin functions: HOLD Requests a direct memory access (DMA). When 1, microprocessor stops and places address, data and control bus in high-impedance state. HLDA (Hold Acknowledge) Indicates that the microprocessor has entered the hold state. RO/GT1 and RO/GT0 Request/grant pins request/grant direct memory accesses (DMA) during maximum mode operation.
LOCK Lock output is used to lock peripherals off the system. Activated by using the LOCK: prex on any instruction. QS1 and QS0 The queue status bits show status of internal instruction queue. Provided for access by the numeric coprocessor (8087).
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(Feb. 20, 2002)
1966
UMBC
8086/88 Chip Set
CMPE 310
8284A Clock Generator Basic functions: Clock generation. RESET synchronization. READY synchronization. Peripheral clock signal.
Connection of the 8284 and the 8086.
8086
CSYNC 1 2 3 4 5 6 CLK 7 8 9
8284A
18 X1 17 16 15 X2 14 13 F/C 12 11 10 RESET
Crystal OSC 15MHz
CLK RESET
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(Feb. 20, 2002)
1966
UMBC
8086/88 Chip Set
CMPE 310
8284A Clock Generator RES DQ Schmitt trigger X1 X2 XTAL OSC OSC (EFI input to other 8284As) RESET
8284A
CSYNC PCLK AEN1 RDY1 READY RDY2 AEN2 CLK GND 18 17 16 15 14 13 12 11 10
1 2 3 4 5 6 7 8 9
VCC X1 X2 ASYNC EFI F/C OSC RES RESET
F/C 2-to-1 mux
EFI CSYNC
divby-3 cnter +3
divby-2 cnter +2
PCLK
RDY1 DQ ASYNC 9 DQ
CLK READY
AEN1 RDY2
AEN2
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(Feb. 20, 2002)
1966
UMBC
8086/88 Chip Set
CMPE 310
8284A Clock Generator Clock generation: Crystal is connected to X1 and X2. XTAL OSC generates square wave signal at crystals frequency which feeds: An inverting buffer (output OSC) which is used to drive the EFI input of other 8284As. 2-to-1 MUX F/C selects XTAL or EFI external input.
The MUX drives a divide-by-3 counter (15MHz to 5MHz). This drives: The READY ipop (READY synchronization). A second divide-by-2 counter (2.5MHz clk for peripheral components). The RESET ipop. CLK which drives the 8086 CLK input.
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10
(Feb. 20, 2002)
1966
UMBC
8086/88 Chip Set
CMPE 310
8284A Clock Generator RESET: Negative edge-triggered ipop applies the RESET signal to the 8086 on the falling edge. The 8086 samples the RESET pin on the rising edge. CSYNC: Used with multiple processors. 18 X1 CSYNC 1 Crystal 17 2 OSC 16 3 15MHz 15 X2 4 +5V 14 5 Reset F/C 13 6 10K switch 12 7 CLK 11 RES 8 10 RESET 9 10uF RESET
CLK
8086
8284A
RC = 10K*10uF ~= 100msec
Correct reset timing requires that the RESET input to the microprocessor becomes a logic 1 NO LATER than 4 clocks after power up and stay high for at least 50us. 11 (Feb. 20, 2002)
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1966
UMBC
8086/88 Chip Set
CMPE 310
BUS Buffering and Latching Demultiplexing the Buses: Computer systems have three buses: Address Data Control
The Address and Data bus are multiplexed (shared) due to pin limitations on the 8086. The ALE pin controls a set of latches.
All signals MUST be buffered. Latches buffer for A0-A15.
Control and A16-A19 + BHE are buffered separately.
Data bus buffers must be bi-directional buffers (BB).
BHE: Selects the high-order memory bank.
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12
(Feb. 20, 2002)
1966
UMBC
8086/88 Chip Set
CMPE 310
BUS Buffering and Latching Buffer BHE A19 A16 A15

A8
Address Bus
A7
G Latches
Latches
A0 D15 Data Bus BB GD D 8 D7 BB GD D 0
VCC AD15 A16/S3 A17/S4 A18/S5 A19/S6 BHE/S7 MN/MX RD Hold HLDA WR M/IO DT/R DEN ALE INTA TEST READY RESET
8086 CPU
GND AD14 AD13 AD12 AD11 AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 NMI INTR CLK GND Buffer 13
Control (Feb. 20, 2002)
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1966
UMBC
8086/88 Chip Set
CMPE 310
BUS Timing Writing: Dump address on address bus. Dump data on data bus. Issue a write (WR) and set M/IO to 1. T1 One Bus Cycle T3 T2 T4
CLK
Address Address
Valid Address Data written to memory
Address/Data
WR Simplied 8086 Write Bus Cycle
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14
(Feb. 20, 2002)
1966
UMBC
8086/88 Chip Set
CMPE 310
BUS Timing Reading: Dump address on address bus. Issue a read (RD) and set M/IO to 1. Wait for memory access cycle. T1 One Bus Cycle T3 T2 T4
CLK
Address Address
Valid Address Data from memory
Address/Data
RD Simplied 8086 Read Bus Cycle
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15
(Feb. 20, 2002)
1966
UMBC
8086/88 Chip Set
CMPE 310
BUS Timing Bus Timing: 200ns T1 T4

A19-A16 S7-S3 Float Data In Float AD15-AD0
800ns T2 T3
Tw
CLK
A19-A16/S6-S3 Address setup Data Setup
AD15-AD0
M/IO
ALE
DT/R
RD DEN READY Bus Timing for a Read Operation
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16
(Feb. 20, 2002)
1966
UMBC
8086/88 Chip Set
CMPE 310
BUS Timing During T1:
The address is placed on the Address/Data bus. Control signals M/IO, ALE and DT/R specify memory or I/O, latch the address onto the address bus and set the direction of data transfer on data bus. During T2:
8086 issues the RD or WR signal, DEN, and, for a write, the data. DEN enables the memory or I/O device to receive the data for writes and the 8086 to receive the data for reads. During T3:
This cycle is provided to allow memory to access data. READY is sampled at the end of T2.
If low, T3 becomes a wait state.
Otherwise, the data bus is sampled at the end of T3.
During T4:
All bus signals are deactivated, in preparation for next bus cycle. Data is sampled for reads, writes occur for writes. 17 (Feb. 20, 2002)
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1966
UMBC
8086/88 Chip Set
CMPE 310
BUS Timing Timing: Each BUS CYCLE on the 8086 equals four system clocking periods (T states). The clock rate is 5MHz, therefore one Bus Cycle is 800ns. The transfer rate is 1.25MHz.
Memory specs (memory access time) must match constraints of system timing.
For example, bus timing for a read operation shows almost 600ns are needed to read data. However, memory must access faster due to setup times, e.g. Address setup and data setup. This subtracts off about 150ns. Therefore, memory must access in at least 450ns minus another 3040ns guard band for buffers and decoders.
420ns DRAM required for the 8086.
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18
(Feb. 20, 2002)
1966
UMBC
8086/88 Chip Set
CMPE 310
BUS Timing READY: An input to the 8086 that causes wait states for slower memory and I/O components. A wait state (TW) is an extra clock period inserted between T2 and T3 to
CLK
AD15-AD0 Float
lengthen the bus cycle. For example, this extends a 460ns bus cycle (at 5MHz clock) to 660ns. 800ns 200ns Tw T3 T2 T1 T4
Data In Float
AD15-AD0 READY OK
Data In
READY
Fail
Sampled again Wait State timing Text discusses role of 8284A and timing requirements for the 8086. 19 (Feb. 20, 2002)
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1966
UMBC
8086/88 Chip Set
CMPE 310
MIN and MAX Mode Controlled through the MN/MX pin. Minimum mode is cheaper since all control signals for memory and I/ O are generated by the microprocessor. Maximum mode is designed to be used when a coprocessor (8087) exists in the system.
Some of the control signals must be generated externally, due to redenition of certain control pins on the 8086. The following pins are lost when the 8086 operates in Maximum mode. ALE WR IO/M DT/R DEN INTA
This requires an external bus controller: The 8288 Bus Controller.
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20
(Feb. 20, 2002)
1966
UMBC
8086/88 Chip Set
CMPE 310
8288 Bus Controller 8086 Status
8288
Command Signal Generator MRDC MWTC AMWC IORC IOWC AIOWC INTA
S0 S1 S2 Status Decoder
Control Input
IOB VCC CLK S0 S1 S2 DT/R MCE/PDN ALE DEN AEN CEN MRDC INTA AMWC IORC MWTC AIOWC GND IOWC
CLK AEN CEN IOB Control Logic Control Signal Generator
DT/R DEN MCE/PDEN ALE
Separate signals are used for I/O (IORC and IOWC) and memory (MRDC and MWTC). Also provided are advanced memory (AIOWC) and I/O (AIOWC) write strobes plus INTA. 21 (Feb. 20, 2002)
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1966
UMBC
8086/88 Chip Set
CMPE 310
MAX Mode 8086 System VCC CLK READY RESET S0 S1 S2 8086 CPU AD0-AD15 Latches T OE 8286 Transceiver Data INT STB
8284A RES
GND
S0 CLK MRDC S1 MWTC S2 8288 DEN IORC DT/R IOWC ALE INTA Address
RD WR 8259A Interrupt Controller RAM
IRQ 0-7
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22
(Feb. 20, 2002)
1966
UMBC

U Proccessors

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Computer

Early Computer - ENIAC

6000 different switches and cables!

Stored Program Concept

Charles Babbage also proposed a mechanical device that could

store a program, Analytical Engine in 1822

First Stored Program Computer - EDVAC

Random Access Core Developed

Modern Computer Model

CPU - Central Processing Unit = Microprocessor

Memory - Stores Information (DRAM, ROM)

I/O - Input/Output Devices - Peripherals (KBD, PRN)

Bus - Set of Parallel wires (Address Bus, Data Bus)

Fetch and Execute Cycle

CPU Stores Data Internally

4. CPU Interprets Data as an Instruction (FETCH/EXECUTE*)

CPU Performs the Instruction (EXECUTE)

Machine Dependent bytes (8086)

Inside the CPU - Arithmetic Logic Unit

Combinational Logic Circuit

Two Classes of Outputs

General Arithmetic Circuit

Arithmetic Logic Unit (ALU)

Inside the CPU - Control Unit

Generally Composed of Subcircuits

I/O Devices - (Input/Output)

Intel x86 Microprocessors

Intel x86 Microprocessors

Intel x86 Family Tree

Internal architecture of 8086 microprocessor

Instr. Decode; Bus Controller

SYSTEM BUS (Internal)

Operating modes for Pentium

SYTEM MANAGEMENT MODE (SMM):

Advanced technologies used in Pentium (1)

Advanced technologies used in Pentium (2)

Floating Point Optimization

Compared with I486: separate instruction and data c

Improvements in Pentium Pro

Deep branch prediction (DBP)

Bigger L2 cache (512KB, 2MB) Pipeline: 31 stages

Dual (Multi) Core Processors

80x86 Internal Architecture

Computer Operation Model

8086 Architecture Specifics

FETCH GET DATA

8086 Internal Architecture

8086 Overall Architecture

Instruction Pipeline EXECUTION UNIT EU

BUS INTERFACE UNIT BIU

System Bus (PC Bus)

Instr. Decode; Bus Controller

SYSTEM BUS (Internal)

Content of the EU: Content of the BIU: .

BIU Bus Interface Unit (Resp: signals and data/instruction

Accumulator Base Counter Data

Code Segment Data Segment Stack Segment Extra Segment

For 32 bit processors: AX register (16b) EAX (32b)

8086/8088 Register File (cont)

IP Contains Address of NEXT Instruction to be Fetched

AX, BX, CX, DX

Accumulator Base Counter Data

Some Special uses for Certain Instructions

AX = ALoperand(8) (DX,AX) = AXoperand(16). Eg:..